Add capability to parser and retrieve max DP link supported rate from
link-frequencies property of dp_out endpoint.

Changes in v6:
-- second patch after split parser patch into two patches

Changes in v7:
-- without checking cnt against DP_MAX_NUM_DP_LANES to retrieve link rate

Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
---
 drivers/gpu/drm/msm/dp/dp_parser.c | 19 +++++++++++++++++--
 drivers/gpu/drm/msm/dp/dp_parser.h |  2 ++
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c
index b5f7e70..037dad8 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -94,15 +94,28 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
 static int dp_parser_misc(struct dp_parser *parser)
 {
 	struct device_node *of_node = parser->pdev->dev.of_node;
+	struct device_node *endpoint;
+	u64 frequency;
 	int cnt;
 
 	/*
 	 * data-lanes is the property of dp_out endpoint
 	 */
 	cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES);
-	if (cnt > 0)
+	if (cnt > 0) {
 		parser->max_dp_lanes = cnt;
-	else {
+
+		endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
+		cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
+		if (cnt > 0) {
+			of_property_read_u64_index(endpoint, "link-frequencies",
+							cnt - 1, &frequency);
+			frequency /= 10;	/* from symbol rate to link rate */
+			parser->max_dp_link_rate = (frequency / 1000); /* kbits */
+		} else {
+			parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 540000 khz */
+		}
+	} else {
 		/*
 		 * legacy code, data-lanes is the property of mdss_dp node
 		 */
@@ -111,6 +124,8 @@ static int dp_parser_misc(struct dp_parser *parser)
 			parser->max_dp_lanes = cnt;
 		else
 			parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
+
+		parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 540000 khz */
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h
index 866c1a8..3ddf639 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.h
+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
@@ -15,6 +15,7 @@
 #define DP_LABEL "MDSS DP DISPLAY"
 #define DP_MAX_PIXEL_CLK_KHZ	675000
 #define DP_MAX_NUM_DP_LANES	4
+#define DP_LINK_RATE_HBR2       540000
 
 enum dp_pm_type {
 	DP_CORE_PM,
@@ -119,6 +120,7 @@ struct dp_parser {
 	struct dp_io io;
 	struct dp_display_data disp_data;
 	u32 max_dp_lanes;
+	u32 max_dp_link_rate;
 	struct drm_bridge *next_bridge;
 
 	int (*parse)(struct dp_parser *parser);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

On 5 December 2022 22:14:29 GMT+03:00, Kuogee Hsieh <quic_khsieh@quicinc.com> wrote:
>Add capability to parser and retrieve max DP link supported rate from
>link-frequencies property of dp_out endpoint.
>
>Changes in v6:
>-- second patch after split parser patch into two patches
>
>Changes in v7:
>-- without checking cnt against DP_MAX_NUM_DP_LANES to retrieve link rate
>
>Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
>---
> drivers/gpu/drm/msm/dp/dp_parser.c | 19 +++++++++++++++++--
> drivers/gpu/drm/msm/dp/dp_parser.h |  2 ++
> 2 files changed, 19 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c
>index b5f7e70..037dad8 100644
>--- a/drivers/gpu/drm/msm/dp/dp_parser.c
>+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
>@@ -94,15 +94,28 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
> static int dp_parser_misc(struct dp_parser *parser)
> {
> 	struct device_node *of_node = parser->pdev->dev.of_node;
>+	struct device_node *endpoint;
>+	u64 frequency;
> 	int cnt;
> 
> 	/*
> 	 * data-lanes is the property of dp_out endpoint
> 	 */
> 	cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES);
>-	if (cnt > 0)
>+	if (cnt > 0) {
> 		parser->max_dp_lanes = cnt;
>-	else {
>+
>+		endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
>+		cnt = of_property_count_u64_elems(endpoint, "link-frequencies");

Missing of_node_put()

>+		if (cnt > 0) {
>+			of_property_read_u64_index(endpoint, "link-frequencies",
>+							cnt - 1, &frequency);
>+			frequency /= 10;	/* from symbol rate to link rate */
>+			parser->max_dp_link_rate = (frequency / 1000); /* kbits */
>+		} else {
>+			parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 540000 khz */
>+		}
>+	} else {
> 		/*
> 		 * legacy code, data-lanes is the property of mdss_dp node
> 		 */
>@@ -111,6 +124,8 @@ static int dp_parser_misc(struct dp_parser *parser)
> 			parser->max_dp_lanes = cnt;
> 		else
> 			parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
>+
>+		parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 540000 khz */

Please, don't mix the dp lanes and dp link rate code. It would be much easier to read. And you can remove the duplicate assignment statements too.

> 	}
> 
> 	return 0;
>diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h
>index 866c1a8..3ddf639 100644
>--- a/drivers/gpu/drm/msm/dp/dp_parser.h
>+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
>@@ -15,6 +15,7 @@
> #define DP_LABEL "MDSS DP DISPLAY"
> #define DP_MAX_PIXEL_CLK_KHZ	675000
> #define DP_MAX_NUM_DP_LANES	4
>+#define DP_LINK_RATE_HBR2       540000
> 
> enum dp_pm_type {
> 	DP_CORE_PM,
>@@ -119,6 +120,7 @@ struct dp_parser {
> 	struct dp_io io;
> 	struct dp_display_data disp_data;
> 	u32 max_dp_lanes;
>+	u32 max_dp_link_rate;
> 	struct drm_bridge *next_bridge;
> 
> 	int (*parse)(struct dp_parser *parser);

-- 
With best wishes
Dmitry