Update the documentation for the new features:
1. Slow Memory Bandwidth allocation (SMBA).
With this feature, the QOS enforcement policies can be applied
to the external slow memory connected to the host. QOS enforcement
is accomplished by assigning a Class Of Service (COS) to a processor
and specifying allocations or limits for that COS for each resource
to be allocated.
2. Bandwidth Monitoring Event Configuration (BMEC).
The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes
are set to count all the total and local reads/writes respectively.
With the introduction of slow memory, the two counters are not
enough to count all the different types are memory events. With the
feature BMEC, the users have the option to configure mbm_total_bytes
and mbm_local_bytes to count the specific type of events.
Also add configuration instructions with examples.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
Documentation/x86/resctrl.rst | 130 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 128 insertions(+), 2 deletions(-)
diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst
index 71a531061e4e..b4fe54f219b6 100644
--- a/Documentation/x86/resctrl.rst
+++ b/Documentation/x86/resctrl.rst
@@ -17,14 +17,16 @@ AMD refers to this feature as AMD Platform Quality of Service(AMD QoS).
This feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cpuinfo
flag bits:
-============================================= ================================
+=============================================== ================================
RDT (Resource Director Technology) Allocation "rdt_a"
CAT (Cache Allocation Technology) "cat_l3", "cat_l2"
CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2"
CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc"
MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"
MBA (Memory Bandwidth Allocation) "mba"
-============================================= ================================
+SMBA (Slow Memory Bandwidth Allocation) "smba"
+BMEC (Bandwidth Monitoring Event Configuration) "bmec"
+=============================================== ================================
To use the feature mount the file system::
@@ -161,6 +163,73 @@ with the following files:
"mon_features":
Lists the monitoring events if
monitoring is enabled for the resource.
+ Example::
+
+ # cat /sys/fs/resctrl/info/L3_MON/mon_features
+ llc_occupancy
+ mbm_total_bytes
+ mbm_local_bytes
+
+ If the system supports Bandwidth Monitoring Event
+ Configuration (BMEC), then the bandwidth events will
+ be configurable. The output will be::
+
+ # cat /sys/fs/resctrl/info/L3_MON/mon_features
+ llc_occupancy
+ mbm_total_bytes
+ mbm_total_config
+ mbm_local_bytes
+ mbm_local_config
+
+"mbm_total_config", "mbm_local_config":
+ These files contain the current event configuration for the events
+ mbm_total_bytes and mbm_local_bytes, respectively, when the
+ Bandwidth Monitoring Event Configuration (BMEC) feature is supported.
+ The event configuration settings are domain specific. Changing the
+ configuration on one CPU in a domain would affect the whole domain.
+
+ Following are the types of events supported:
+
+ ==== ========================================================
+ Bits Description
+ ==== ========================================================
+ 6 Dirty Victims from the QOS domain to all types of memory
+ 5 Reads to slow memory in the non-local NUMA domain
+ 4 Reads to slow memory in the local NUMA domain
+ 3 Non-temporal writes to non-local NUMA domain
+ 2 Non-temporal writes to local NUMA domain
+ 1 Reads to memory in the non-local NUMA domain
+ 0 Reads to memory in the local NUMA domain
+ ==== ========================================================
+
+ By default, the mbm_total_bytes configuration is set to 0x7f to count
+ all the event types and the mbm_local_bytes configuration is set to
+ 0x15 to count all the local memory events.
+
+ Example::
+
+ To view the current configuration, run the command.
+ # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
+ 0:0x7f;1:0x7f;2:0x7f;3:0x7f
+
+ # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config
+ 0:0x15;1:0x15;3:0x15;4:0x15
+
+ To change the mbm_total_bytes to count only reads on domain 0,
+ run the command. The bits 0,1,4 and 5 needs to set.
+
+ # echo "0:0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_config
+
+ # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
+ 0:0x33;1:0x7f;2:0x7f;3:0x7f
+
+ To change the mbm_local_bytes to count all the slow memory reads on
+ domain 1, run the command. The bits 4 and 5 needs to set.
+
+ # echo "1:0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_config
+
+ # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config
+ 0:0x15;1:0x30;3:0x15;4:0x15
"max_threshold_occupancy":
Read/write file provides the largest value (in
@@ -264,6 +333,7 @@ When monitoring is enabled all MON groups will also contain:
the sum for all tasks in the CTRL_MON group and all tasks in
MON groups. Please see example section for more details on usage.
+
Resource allocation rules
-------------------------
@@ -464,6 +534,24 @@ Memory bandwidth domain is L3 cache.
MB:<cache_id0>=bw_MBps0;<cache_id1>=bw_MBps1;...
+Slow Memory bandwidth Allocation (when supported)
+-------------------------------------------------
+Currently, CXL.memory is the only supported "slow" memory device.
+With the support of SMBA feature the hardware enables bandwidth
+allocation on the slow memory devices. If there are multiple slow
+memory devices in the system, then the throttling logic groups all
+the slow sources together and applies the limit on them as a whole.
+
+The presence of the SMBA feature(with CXL.memory) is independent
+of whether slow memory device is actually present in the system.
+If there is no slow memory in the system, then setting a SMBA limit
+will have no impact on the performance of the system.
+
+Slow Memory b/w domain is L3 cache.
+::
+
+ SMBA:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...
+
Reading/writing the schemata file
---------------------------------
Reading the schemata file will show the state of all resources
@@ -479,6 +567,44 @@ which you wish to change. E.g.
L3DATA:0=fffff;1=fffff;2=3c0;3=fffff
L3CODE:0=fffff;1=fffff;2=fffff;3=fffff
+Reading/writing the schemata file (on AMD systems)
+--------------------------------------------------
+Reading the schemata file will show the state of all resources
+on all domains. When writing the memory bandwidth allocation you
+only need to specify those values in an absolute number expressed
+in 1/8 GB/s increments. To allocate bandwidth limit of 2GB, you
+need to specify the value 16 (16 * 1/8 = 2). E.g.
+::
+
+ # cat schemata
+ MB:0=2048;1=2048;2=2048;3=2048
+ L3:0=ffff;1=ffff;2=ffff;3=ffff
+
+ # echo "MB:1=16" > schemata
+ # cat schemata
+ MB:0=2048;1= 16;2=2048;3=2048
+ L3:0=ffff;1=ffff;2=ffff;3=ffff
+
+Reading/writing the schemata file (on AMD systems) with slow memory
+-------------------------------------------------------------------
+Reading the schemata file will show the state of all resources
+on all domains. When writing the memory bandwidth allocation you
+only need to specify those values in an absolute number expressed
+in 1/8 GB/s increments. To allocate bandwidth limit of 8GB, you
+need to specify the value 64 (64 * 1/8 = 8). E.g.
+::
+
+ # cat schemata
+ SMBA:0=2048;1=2048;2=2048;3=2048
+ MB:0=2048;1=2048;2=2048;3=2048
+ L3:0=ffff;1=ffff;2=ffff;3=ffff
+
+ # echo "SMBA:1=64" > schemata
+ # cat schemata
+ SMBA:0=2048;1= 64;2=2048;3=2048
+ MB:0=2048;1=2048;2=2048;3=2048
+ L3:0=ffff;1=ffff;2=ffff;3=ffff
+
Cache Pseudo-Locking
====================
CAT enables a user to specify the amount of cache space that an
Hi Babu, In subject: resctrl_ui.rst -> resctrl.rst On 9/27/2022 1:27 PM, Babu Moger wrote: > Update the documentation for the new features: > 1. Slow Memory Bandwidth allocation (SMBA). > With this feature, the QOS enforcement policies can be applied > to the external slow memory connected to the host. QOS enforcement > is accomplished by assigning a Class Of Service (COS) to a processor > and specifying allocations or limits for that COS for each resource > to be allocated. > > 2. Bandwidth Monitoring Event Configuration (BMEC). > The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes > are set to count all the total and local reads/writes respectively. > With the introduction of slow memory, the two counters are not > enough to count all the different types are memory events. With the types are memory events -> types of memory events? > feature BMEC, the users have the option to configure mbm_total_bytes > and mbm_local_bytes to count the specific type of events. > > Also add configuration instructions with examples. > > Signed-off-by: Babu Moger <babu.moger@amd.com> > --- ... > + > +"mbm_total_config", "mbm_local_config": > + These files contain the current event configuration for the events > + mbm_total_bytes and mbm_local_bytes, respectively, when the > + Bandwidth Monitoring Event Configuration (BMEC) feature is supported. > + The event configuration settings are domain specific. Changing the > + configuration on one CPU in a domain would affect the whole domain. This contradicts the implementation done in this series where the configuration is changed on every CPU in the domain. Reinette
Hi Reinette, On 9/29/22 17:10, Reinette Chatre wrote: > Hi Babu, > > In subject: resctrl_ui.rst -> resctrl.rst > > On 9/27/2022 1:27 PM, Babu Moger wrote: >> Update the documentation for the new features: >> 1. Slow Memory Bandwidth allocation (SMBA). >> With this feature, the QOS enforcement policies can be applied >> to the external slow memory connected to the host. QOS enforcement >> is accomplished by assigning a Class Of Service (COS) to a processor >> and specifying allocations or limits for that COS for each resource >> to be allocated. >> >> 2. Bandwidth Monitoring Event Configuration (BMEC). >> The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes >> are set to count all the total and local reads/writes respectively. >> With the introduction of slow memory, the two counters are not >> enough to count all the different types are memory events. With the > types are memory events -> types of memory events? Ok Sure > >> feature BMEC, the users have the option to configure mbm_total_bytes >> and mbm_local_bytes to count the specific type of events. >> >> Also add configuration instructions with examples. >> >> Signed-off-by: Babu Moger <babu.moger@amd.com> >> --- > ... > >> + >> +"mbm_total_config", "mbm_local_config": >> + These files contain the current event configuration for the events >> + mbm_total_bytes and mbm_local_bytes, respectively, when the >> + Bandwidth Monitoring Event Configuration (BMEC) feature is supported. >> + The event configuration settings are domain specific. Changing the >> + configuration on one CPU in a domain would affect the whole domain. > This contradicts the implementation done in this series where the > configuration is changed on every CPU in the domain. How about this? The event configuration settings are domain specific and will affect all the CPUs in the domain. Thanks Babu
Hi Babu, On 10/3/2022 7:28 AM, Moger, Babu wrote: > Hi Reinette, > > On 9/29/22 17:10, Reinette Chatre wrote: >> Hi Babu, >> >> In subject: resctrl_ui.rst -> resctrl.rst >> >> On 9/27/2022 1:27 PM, Babu Moger wrote: >>> Update the documentation for the new features: >>> 1. Slow Memory Bandwidth allocation (SMBA). >>> With this feature, the QOS enforcement policies can be applied >>> to the external slow memory connected to the host. QOS enforcement >>> is accomplished by assigning a Class Of Service (COS) to a processor >>> and specifying allocations or limits for that COS for each resource >>> to be allocated. >>> >>> 2. Bandwidth Monitoring Event Configuration (BMEC). >>> The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes >>> are set to count all the total and local reads/writes respectively. >>> With the introduction of slow memory, the two counters are not >>> enough to count all the different types are memory events. With the >> types are memory events -> types of memory events? > Ok Sure >> >>> feature BMEC, the users have the option to configure mbm_total_bytes >>> and mbm_local_bytes to count the specific type of events. >>> >>> Also add configuration instructions with examples. >>> >>> Signed-off-by: Babu Moger <babu.moger@amd.com> >>> --- >> ... >> >>> + >>> +"mbm_total_config", "mbm_local_config": >>> + These files contain the current event configuration for the events >>> + mbm_total_bytes and mbm_local_bytes, respectively, when the >>> + Bandwidth Monitoring Event Configuration (BMEC) feature is supported. >>> + The event configuration settings are domain specific. Changing the >>> + configuration on one CPU in a domain would affect the whole domain. >> This contradicts the implementation done in this series where the >> configuration is changed on every CPU in the domain. > > How about this? > > The event configuration settings are domain specific and will affect all the CPUs in the domain. There remains a disconnect between this and the implementation that writes the configuration to every CPU. You could make this change to the documentation but then the implementation needs more than "Update MSR_IA32_EVT_CFG_BASE MSR on all the CPUs in cpu_mask" - that comment needs to highlight that the implementation does not follow the architecture and scope rules nor how configuration changes are made in the rest of the driver and why. Previously [1] you indicated that this is based on guidance from hardware team so perhaps you could document it as a hardware quirk related to this feature? At the minimum it should acknowledge the disconnect. Reinette [1] https://lore.kernel.org/lkml/3511f4f6-d043-9a22-7779-af2c2983b6a2@amd.com/
Hi Reinette, Already responded to this but i don't see my response in archives yet. On 10/3/22 10:36, Reinette Chatre wrote: > Hi Babu, > > On 10/3/2022 7:28 AM, Moger, Babu wrote: >> Hi Reinette, >> >> On 9/29/22 17:10, Reinette Chatre wrote: >>> Hi Babu, >>> >>> In subject: resctrl_ui.rst -> resctrl.rst >>> >>> On 9/27/2022 1:27 PM, Babu Moger wrote: >>>> Update the documentation for the new features: >>>> 1. Slow Memory Bandwidth allocation (SMBA). >>>> With this feature, the QOS enforcement policies can be applied >>>> to the external slow memory connected to the host. QOS enforcement >>>> is accomplished by assigning a Class Of Service (COS) to a processor >>>> and specifying allocations or limits for that COS for each resource >>>> to be allocated. >>>> >>>> 2. Bandwidth Monitoring Event Configuration (BMEC). >>>> The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes >>>> are set to count all the total and local reads/writes respectively. >>>> With the introduction of slow memory, the two counters are not >>>> enough to count all the different types are memory events. With the >>> types are memory events -> types of memory events? >> Ok Sure >>>> feature BMEC, the users have the option to configure mbm_total_bytes >>>> and mbm_local_bytes to count the specific type of events. >>>> >>>> Also add configuration instructions with examples. >>>> >>>> Signed-off-by: Babu Moger <babu.moger@amd.com> >>>> --- >>> ... >>> >>>> + >>>> +"mbm_total_config", "mbm_local_config": >>>> + These files contain the current event configuration for the events >>>> + mbm_total_bytes and mbm_local_bytes, respectively, when the >>>> + Bandwidth Monitoring Event Configuration (BMEC) feature is supported. >>>> + The event configuration settings are domain specific. Changing the >>>> + configuration on one CPU in a domain would affect the whole domain. >>> This contradicts the implementation done in this series where the >>> configuration is changed on every CPU in the domain. >> How about this? >> >> The event configuration settings are domain specific and will affect all the CPUs in the domain. > There remains a disconnect between this and the implementation that writes the > configuration to every CPU. > > You could make this change to the documentation but then the > implementation needs more than "Update MSR_IA32_EVT_CFG_BASE MSR on all > the CPUs in cpu_mask" - that comment needs to highlight that the > implementation does not follow the architecture and scope rules nor how > configuration changes are made in the rest of the driver and why. Previously [1] > you indicated that this is based on guidance from hardware team so perhaps you > could document it as a hardware quirk related to this feature? At the minimum > it should acknowledge the disconnect. ok. I could document this in the code patch 9([PATCH v5 09/12] x86/resctrl: Add sysfs interface to write mbm_total_bytes event configuration. Something like this. /* + * Update MSR_IA32_EVT_CFG_BASE MSR on all the CPUs in cpu_mask. + * The MSR MSR_IA32_EVT_CFG_BASE is domain specific. Writing the + * MSR on one CPU will affect all the CPUs in the domain. + * However, the hardware team recommends to update the MSR on + * all the CPU threads. It is not clear in the document yet. * * Doc will be updated in the next revision. + */ + on_each_cpu_mask(cpu_mask, mon_event_config_write, &mon_info, 1); + Thanks Babu
Hi Babu, On 10/4/2022 7:00 AM, Moger, Babu wrote: > On 10/3/22 10:36, Reinette Chatre wrote: >> On 10/3/2022 7:28 AM, Moger, Babu wrote: >>> On 9/29/22 17:10, Reinette Chatre wrote: >>>> Hi Babu, >>>> >>>> In subject: resctrl_ui.rst -> resctrl.rst >>>> >>>> On 9/27/2022 1:27 PM, Babu Moger wrote: >>>>> Update the documentation for the new features: >>>>> 1. Slow Memory Bandwidth allocation (SMBA). >>>>> With this feature, the QOS enforcement policies can be applied >>>>> to the external slow memory connected to the host. QOS enforcement >>>>> is accomplished by assigning a Class Of Service (COS) to a processor >>>>> and specifying allocations or limits for that COS for each resource >>>>> to be allocated. >>>>> >>>>> 2. Bandwidth Monitoring Event Configuration (BMEC). >>>>> The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes >>>>> are set to count all the total and local reads/writes respectively. >>>>> With the introduction of slow memory, the two counters are not >>>>> enough to count all the different types are memory events. With the >>>> types are memory events -> types of memory events? >>> Ok Sure >>>>> feature BMEC, the users have the option to configure mbm_total_bytes >>>>> and mbm_local_bytes to count the specific type of events. >>>>> >>>>> Also add configuration instructions with examples. >>>>> >>>>> Signed-off-by: Babu Moger <babu.moger@amd.com> >>>>> --- >>>> ... >>>> >>>>> + >>>>> +"mbm_total_config", "mbm_local_config": >>>>> + These files contain the current event configuration for the events >>>>> + mbm_total_bytes and mbm_local_bytes, respectively, when the >>>>> + Bandwidth Monitoring Event Configuration (BMEC) feature is supported. >>>>> + The event configuration settings are domain specific. Changing the >>>>> + configuration on one CPU in a domain would affect the whole domain. >>>> This contradicts the implementation done in this series where the >>>> configuration is changed on every CPU in the domain. >>> How about this? >>> >>> The event configuration settings are domain specific and will affect all the CPUs in the domain. >> There remains a disconnect between this and the implementation that writes the >> configuration to every CPU. >> >> You could make this change to the documentation but then the >> implementation needs more than "Update MSR_IA32_EVT_CFG_BASE MSR on all >> the CPUs in cpu_mask" - that comment needs to highlight that the >> implementation does not follow the architecture and scope rules nor how >> configuration changes are made in the rest of the driver and why. Previously [1] >> you indicated that this is based on guidance from hardware team so perhaps you >> could document it as a hardware quirk related to this feature? At the minimum >> it should acknowledge the disconnect. > > ok. I could document this in the code patch 9([PATCH v5 09/12] > x86/resctrl: Add sysfs interface to write mbm_total_bytes event configuration. > Something like this. > > /* > + * Update MSR_IA32_EVT_CFG_BASE MSR on all the CPUs in cpu_mask. Since multiple MSRs are impacted, how about: "Update MSR_IA32_EVT_CFG_BASE MSRs ..." > + * The MSR MSR_IA32_EVT_CFG_BASE is domain specific. Writing the "The MSRs offset from MSR MSR_IA32_EVT_CFG_BASE are scoped at the domain level. Writing any of these MSRs on one CPU is supposed to be observed by all CPUs in the domain." > + * MSR on one CPU will affect all the CPUs in the domain. Since this is not the case, perhaps it should be " ... is supposed to affect all the CPUs ..." instead? > + * However, the hardware team recommends to update the MSR on > + * all the CPU threads. It is not clear in the document yet. To be consistent, could "CPU threads" be "CPUs"? Could you please be specific about which document you refer to? Although, I do not think that writing the last part about "the document" adds value here. You are representing AMD with this submission and you document that you are following the guidance from the hardware team in this regard. I think that is sufficient. > * * Doc will be updated in the next revision. This is a change that will be made to the kernel source ... what does "next revision" mean when somebody reads this comment in a few years? Putting all of the above together, how about: "Update MSR_IA32_EVT_CFG_BASE MSRs on all the CPUs in cpu_mask. The MSRs offset from MSR MSR_IA32_EVT_CFG_BASE are scoped at the domain level. Writing any of these MSRs on one CPU is supposed to be observed by all CPUs in the domain. However, the hardware team recommends to update these MSRs on all the CPUs in the domain." Reinette
On Tue, Sep 27, 2022 at 03:27:00PM -0500, Babu Moger wrote:
> + Following are the types of events supported:
> +
> + ==== ========================================================
> + Bits Description
> + ==== ========================================================
> + 6 Dirty Victims from the QOS domain to all types of memory
> + 5 Reads to slow memory in the non-local NUMA domain
> + 4 Reads to slow memory in the local NUMA domain
> + 3 Non-temporal writes to non-local NUMA domain
> + 2 Non-temporal writes to local NUMA domain
> + 1 Reads to memory in the non-local NUMA domain
> + 0 Reads to memory in the local NUMA domain
> + ==== ========================================================
> +
> + By default, the mbm_total_bytes configuration is set to 0x7f to count
> + all the event types and the mbm_local_bytes configuration is set to
> + 0x15 to count all the local memory events.
> +
> + Example::
> +
> + To view the current configuration, run the command.
> + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
> + 0:0x7f;1:0x7f;2:0x7f;3:0x7f
> +
> + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config
> + 0:0x15;1:0x15;3:0x15;4:0x15
> +
> + To change the mbm_total_bytes to count only reads on domain 0,
> + run the command. The bits 0,1,4 and 5 needs to set.
> +
> + # echo "0:0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_config
> +
> + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
> + 0:0x33;1:0x7f;2:0x7f;3:0x7f
> +
> + To change the mbm_local_bytes to count all the slow memory reads on
> + domain 1, run the command. The bits 4 and 5 needs to set.
> +
> + # echo "1:0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_config
> +
> + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config
> + 0:0x15;1:0x30;3:0x15;4:0x15
>
Hi Babu,
The description text for each snippets above shouldn't in the code
block. Also, split the block into three code blocks in the lists:
---- >8 ----
diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst
index b4fe54f219b6f3..ec578b069276ce 100644
--- a/Documentation/x86/resctrl.rst
+++ b/Documentation/x86/resctrl.rst
@@ -206,25 +206,26 @@ with the following files:
all the event types and the mbm_local_bytes configuration is set to
0x15 to count all the local memory events.
- Example::
+ Examples:
+
+ * To view the current configuration::
- To view the current configuration, run the command.
# cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
0:0x7f;1:0x7f;2:0x7f;3:0x7f
# cat /sys/fs/resctrl/info/L3_MON/mbm_local_config
0:0x15;1:0x15;3:0x15;4:0x15
- To change the mbm_total_bytes to count only reads on domain 0,
- run the command. The bits 0,1,4 and 5 needs to set.
+ * To change the mbm_total_bytes to count only reads on domain 0
+ (the bits 0, 1, 4 and 5 needs to be set)::
# echo "0:0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_config
# cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
0:0x33;1:0x7f;2:0x7f;3:0x7f
- To change the mbm_local_bytes to count all the slow memory reads on
- domain 1, run the command. The bits 4 and 5 needs to set.
+ * To change the mbm_local_bytes to count all the slow memory reads on
+ domain 1 (the bits 4 and 5 needs to be set)::
# echo "1:0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_config
Also, there isn't description of mapping from bits from the supported events
table to the bytes input for mbm_{total,local}_config.
> +Slow Memory b/w domain is L3 cache.
> +::
> +
> + SMBA:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...
> +
What b/w stands for in the context above?
> Reading/writing the schemata file
> ---------------------------------
> Reading the schemata file will show the state of all resources
> @@ -479,6 +567,44 @@ which you wish to change. E.g.
> L3DATA:0=fffff;1=fffff;2=3c0;3=fffff
> L3CODE:0=fffff;1=fffff;2=fffff;3=fffff
>
> +Reading/writing the schemata file (on AMD systems)
> +--------------------------------------------------
> +Reading the schemata file will show the state of all resources
> +on all domains. When writing the memory bandwidth allocation you
> +only need to specify those values in an absolute number expressed
> +in 1/8 GB/s increments. To allocate bandwidth limit of 2GB, you
> +need to specify the value 16 (16 * 1/8 = 2). E.g.
> <snipped>...
> +Reading the schemata file will show the state of all resources
> +on all domains. When writing the memory bandwidth allocation you
> +only need to specify those values in an absolute number expressed
> +in 1/8 GB/s increments. To allocate bandwidth limit of 8GB, you
> +need to specify the value 64 (64 * 1/8 = 8). E.g.
s/E.g./For example:/
Thanks.
--
An old man doll... just what I always wanted! - Clara
Hi Sanjaya,
On 9/27/22 23:25, Bagas Sanjaya wrote:
> On Tue, Sep 27, 2022 at 03:27:00PM -0500, Babu Moger wrote:
>> + Following are the types of events supported:
>> +
>> + ==== ========================================================
>> + Bits Description
>> + ==== ========================================================
>> + 6 Dirty Victims from the QOS domain to all types of memory
>> + 5 Reads to slow memory in the non-local NUMA domain
>> + 4 Reads to slow memory in the local NUMA domain
>> + 3 Non-temporal writes to non-local NUMA domain
>> + 2 Non-temporal writes to local NUMA domain
>> + 1 Reads to memory in the non-local NUMA domain
>> + 0 Reads to memory in the local NUMA domain
>> + ==== ========================================================
>> +
>> + By default, the mbm_total_bytes configuration is set to 0x7f to count
>> + all the event types and the mbm_local_bytes configuration is set to
>> + 0x15 to count all the local memory events.
>> +
>> + Example::
>> +
>> + To view the current configuration, run the command.
>> + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
>> + 0:0x7f;1:0x7f;2:0x7f;3:0x7f
>> +
>> + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config
>> + 0:0x15;1:0x15;3:0x15;4:0x15
>> +
>> + To change the mbm_total_bytes to count only reads on domain 0,
>> + run the command. The bits 0,1,4 and 5 needs to set.
>> +
>> + # echo "0:0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_config
>> +
>> + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
>> + 0:0x33;1:0x7f;2:0x7f;3:0x7f
>> +
>> + To change the mbm_local_bytes to count all the slow memory reads on
>> + domain 1, run the command. The bits 4 and 5 needs to set.
>> +
>> + # echo "1:0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_config
>> +
>> + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config
>> + 0:0x15;1:0x30;3:0x15;4:0x15
>>
> Hi Babu,
>
> The description text for each snippets above shouldn't in the code
> block. Also, split the block into three code blocks in the lists:
Did you mean, I need to remove similar texts from code?
>
> ---- >8 ----
> diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst
> index b4fe54f219b6f3..ec578b069276ce 100644
> --- a/Documentation/x86/resctrl.rst
> +++ b/Documentation/x86/resctrl.rst
> @@ -206,25 +206,26 @@ with the following files:
> all the event types and the mbm_local_bytes configuration is set to
> 0x15 to count all the local memory events.
>
> - Example::
> + Examples:
> +
> + * To view the current configuration::
>
> - To view the current configuration, run the command.
> # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
> 0:0x7f;1:0x7f;2:0x7f;3:0x7f
>
> # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config
> 0:0x15;1:0x15;3:0x15;4:0x15
>
> - To change the mbm_total_bytes to count only reads on domain 0,
> - run the command. The bits 0,1,4 and 5 needs to set.
> + * To change the mbm_total_bytes to count only reads on domain 0
> + (the bits 0, 1, 4 and 5 needs to be set)::
>
> # echo "0:0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_config
>
> # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
> 0:0x33;1:0x7f;2:0x7f;3:0x7f
>
> - To change the mbm_local_bytes to count all the slow memory reads on
> - domain 1, run the command. The bits 4 and 5 needs to set.
> + * To change the mbm_local_bytes to count all the slow memory reads on
> + domain 1 (the bits 4 and 5 needs to be set)::
>
> # echo "1:0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_config
>
Thanks for the diff. I cannot get this right for some reason. I will
probably send the diff before the final series.
>
> Also, there isn't description of mapping from bits from the supported events
> table to the bytes input for mbm_{total,local}_config.
It is already there. Is that not clear?
+ Following are the types of events supported:
+
+ ==== ========================================================
+ Bits Description
+ ==== ========================================================
+ 6 Dirty Victims from the QOS domain to all types of memory
+ 5 Reads to slow memory in the non-local NUMA domain
+ 4 Reads to slow memory in the local NUMA domain
+ 3 Non-temporal writes to non-local NUMA domain
+ 2 Non-temporal writes to local NUMA domain
+ 1 Reads to memory in the non-local NUMA domain
+ 0 Reads to memory in the local NUMA domain
+ ==== ========================================================
>
>> +Slow Memory b/w domain is L3 cache.
>> +::
>> +
>> + SMBA:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...
>> +
> What b/w stands for in the context above?
b/w is bandwidth. I will correct it.
>
>> Reading/writing the schemata file
>> ---------------------------------
>> Reading the schemata file will show the state of all resources
>> @@ -479,6 +567,44 @@ which you wish to change. E.g.
>> L3DATA:0=fffff;1=fffff;2=3c0;3=fffff
>> L3CODE:0=fffff;1=fffff;2=fffff;3=fffff
>>
>> +Reading/writing the schemata file (on AMD systems)
>> +--------------------------------------------------
>> +Reading the schemata file will show the state of all resources
>> +on all domains. When writing the memory bandwidth allocation you
>> +only need to specify those values in an absolute number expressed
>> +in 1/8 GB/s increments. To allocate bandwidth limit of 2GB, you
>> +need to specify the value 16 (16 * 1/8 = 2). E.g.
>> <snipped>...
>> +Reading the schemata file will show the state of all resources
>> +on all domains. When writing the memory bandwidth allocation you
>> +only need to specify those values in an absolute number expressed
>> +in 1/8 GB/s increments. To allocate bandwidth limit of 8GB, you
>> +need to specify the value 64 (64 * 1/8 = 8). E.g.
> s/E.g./For example:/
Thanks
Babu Moger
On 9/28/22 22:23, Moger, Babu wrote:
>> Hi Babu,
>>
>> The description text for each snippets above shouldn't in the code
>> block. Also, split the block into three code blocks in the lists:
> Did you mean, I need to remove similar texts from code?
I mean extracting code description from the code block, see the diff below.
>>
>> ---- >8 ----
>> diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst
>> index b4fe54f219b6f3..ec578b069276ce 100644
>> --- a/Documentation/x86/resctrl.rst
>> +++ b/Documentation/x86/resctrl.rst
>> @@ -206,25 +206,26 @@ with the following files:
>> all the event types and the mbm_local_bytes configuration is set to
>> 0x15 to count all the local memory events.
>>
>> - Example::
>> + Examples:
>> +
>> + * To view the current configuration::
>>
>> - To view the current configuration, run the command.
>> # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
>> 0:0x7f;1:0x7f;2:0x7f;3:0x7f
>>
>> # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config
>> 0:0x15;1:0x15;3:0x15;4:0x15
>>
>> - To change the mbm_total_bytes to count only reads on domain 0,
>> - run the command. The bits 0,1,4 and 5 needs to set.
>> + * To change the mbm_total_bytes to count only reads on domain 0
>> + (the bits 0, 1, 4 and 5 needs to be set)::
>>
>> # echo "0:0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_config
>>
>> # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
>> 0:0x33;1:0x7f;2:0x7f;3:0x7f
>>
>> - To change the mbm_local_bytes to count all the slow memory reads on
>> - domain 1, run the command. The bits 4 and 5 needs to set.
>> + * To change the mbm_local_bytes to count all the slow memory reads on
>> + domain 1 (the bits 4 and 5 needs to be set)::
>>
>> # echo "1:0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_config
>>
>
> Thanks for the diff. I cannot get this right for some reason. I will
> probably send the diff before the final series.
>
>
OK.
>>
>> Also, there isn't description of mapping from bits from the supported events
>> table to the bytes input for mbm_{total,local}_config.
>
> It is already there. Is that not clear?
No. I don't see why setting bits 0, 1, 4, and 5 on domain 0 translates to
`0:0x33`, for example.
>>
>>> +Slow Memory b/w domain is L3 cache.
>>> +::
>>> +
>>> + SMBA:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...
>>> +
>> What b/w stands for in the context above?
> b/w is bandwidth. I will correct it.
OK.
Thanks for replying.
--
An old man doll... just what I always wanted! - Clara
Hi Sanjaya,
On 9/29/22 03:48, Bagas Sanjaya wrote:
> On 9/28/22 22:23, Moger, Babu wrote:
>>> Hi Babu,
>>>
>>> The description text for each snippets above shouldn't in the code
>>> block. Also, split the block into three code blocks in the lists:
>> Did you mean, I need to remove similar texts from code?
> I mean extracting code description from the code block, see the diff below.
>
>>> ---- >8 ----
>>> diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst
>>> index b4fe54f219b6f3..ec578b069276ce 100644
>>> --- a/Documentation/x86/resctrl.rst
>>> +++ b/Documentation/x86/resctrl.rst
>>> @@ -206,25 +206,26 @@ with the following files:
>>> all the event types and the mbm_local_bytes configuration is set to
>>> 0x15 to count all the local memory events.
>>>
>>> - Example::
>>> + Examples:
>>> +
>>> + * To view the current configuration::
>>>
>>> - To view the current configuration, run the command.
>>> # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
>>> 0:0x7f;1:0x7f;2:0x7f;3:0x7f
>>>
>>> # cat /sys/fs/resctrl/info/L3_MON/mbm_local_config
>>> 0:0x15;1:0x15;3:0x15;4:0x15
>>>
>>> - To change the mbm_total_bytes to count only reads on domain 0,
>>> - run the command. The bits 0,1,4 and 5 needs to set.
>>> + * To change the mbm_total_bytes to count only reads on domain 0
>>> + (the bits 0, 1, 4 and 5 needs to be set)::
>>>
>>> # echo "0:0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_config
>>>
>>> # cat /sys/fs/resctrl/info/L3_MON/mbm_total_config
>>> 0:0x33;1:0x7f;2:0x7f;3:0x7f
>>>
>>> - To change the mbm_local_bytes to count all the slow memory reads on
>>> - domain 1, run the command. The bits 4 and 5 needs to set.
>>> + * To change the mbm_local_bytes to count all the slow memory reads on
>>> + domain 1 (the bits 4 and 5 needs to be set)::
>>>
>>> # echo "1:0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_config
>>>
>> Thanks for the diff. I cannot get this right for some reason. I will
>> probably send the diff before the final series.
>>
>>
> OK.
>
>>> Also, there isn't description of mapping from bits from the supported events
>>> table to the bytes input for mbm_{total,local}_config.
>> It is already there. Is that not clear?
> No. I don't see why setting bits 0, 1, 4, and 5 on domain 0 translates to
> `0:0x33`, for example.
It is 110011b(binary) which is 0x33. I can make that little more clear.
Thanks
Babu
>
>>>> +Slow Memory b/w domain is L3 cache.
>>>> +::
>>>> +
>>>> + SMBA:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...
>>>> +
>>> What b/w stands for in the context above?
>> b/w is bandwidth. I will correct it.
> OK.
>
> Thanks for replying.
>
--
Thanks
Babu Moger
On 9/29/22 20:22, Moger, Babu wrote:
>>>> Also, there isn't description of mapping from bits from the supported events
>>>> table to the bytes input for mbm_{total,local}_config.
>>> It is already there. Is that not clear?
>> No. I don't see why setting bits 0, 1, 4, and 5 on domain 0 translates to
>> `0:0x33`, for example.
>
> It is 110011b(binary) which is 0x33. I can make that little more clear.
>
Ah! I see that flipping bits in order to to set the flag. Thanks for
the explanation.
--
An old man doll... just what I always wanted! - Clara
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