.../bindings/pwm/mediatek,pwm-disp.yaml | 71 +++++++++++++++++++ .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 44 ------------ 2 files changed, 71 insertions(+), 44 deletions(-) create mode 100755 Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
From: Xinlei Lee <xinlei.lee@mediatek.corp-partner.google.com>
Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format as suggested by maintainer
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.corp-partner.google.com>
---
.../bindings/pwm/mediatek,pwm-disp.yaml | 71 +++++++++++++++++++
.../devicetree/bindings/pwm/pwm-mtk-disp.txt | 44 ------------
2 files changed, 71 insertions(+), 44 deletions(-)
create mode 100755 Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
new file mode 100755
index 000000000000..edf2a2e9ea72
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek PWM Controller Device Tree Bindings
+
+maintainers:
+ - Jitao Shi <jitao.shi@mediatek.com>
+ - Xinlei Lee <xinlei.lee@mediatek.com>
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt2701-disp-pwm
+ - mediatek,mt6595-disp-pwm
+ - mediatek,mt8173-disp-pwm
+ - mediatek,mt8183-disp-pwm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ "#pwm-cells":
+ description:
+ Number of cells in a PWM specifier.
+
+ clocks:
+ items:
+ - description: Main Clock
+ - description: Mm Clock
+
+ clock-names:
+ items:
+ - const: main
+ - const: mm
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - power-domains
+ - "#pwm-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mt8183-power.h>
+
+ pwm: pwm@1100e000 {
+ compatible = "mediatek,mt8183-disp-pwm";
+ reg = <0x1100e000 0x1000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ #pwm-cells = <2>;
+ clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
+ <&infracfg CLK_INFRA_DISP_PWM>;
+ clock-names = "main", "mm";
+ };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
deleted file mode 100644
index 902b271891ae..000000000000
--- a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-MediaTek display PWM controller
-
-Required properties:
- - compatible: should be "mediatek,<name>-disp-pwm":
- - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
- - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
- - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
- - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
- - reg: physical base address and length of the controller's registers.
- - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
- the cell format.
- - clocks: phandle and clock specifier of the PWM reference clock.
- - clock-names: must contain the following:
- - "main": clock used to generate PWM signals.
- - "mm": sync signals from the modules of mmsys.
- - pinctrl-names: Must contain a "default" entry.
- - pinctrl-0: One property must exist for each entry in pinctrl-names.
- See pinctrl/pinctrl-bindings.txt for details of the property values.
-
-Example:
- pwm0: pwm@1401e000 {
- compatible = "mediatek,mt8173-disp-pwm",
- "mediatek,mt6595-disp-pwm";
- reg = <0 0x1401e000 0 0x1000>;
- #pwm-cells = <2>;
- clocks = <&mmsys CLK_MM_DISP_PWM026M>,
- <&mmsys CLK_MM_DISP_PWM0MM>;
- clock-names = "main", "mm";
- pinctrl-names = "default";
- pinctrl-0 = <&disp_pwm0_pins>;
- };
-
- backlight_lcd: backlight_lcd {
- compatible = "pwm-backlight";
- pwms = <&pwm0 0 1000000>;
- brightness-levels = <
- 0 16 32 48 64 80 96 112
- 128 144 160 176 192 208 224 240
- 255
- >;
- default-brightness-level = <9>;
- power-supply = <&mt6397_vio18_reg>;
- enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
- };
--
2.18.0
On Wed, Feb 16, 2022 at 5:43 PM <xinlei.lee@mediatek.com> wrote:
>
> From: Xinlei Lee <xinlei.lee@mediatek.corp-partner.google.com>
>
> Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format as suggested by maintainer
>
> Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.corp-partner.google.com>
> ---
> .../bindings/pwm/mediatek,pwm-disp.yaml | 71 +++++++++++++++++++
> .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 44 ------------
> 2 files changed, 71 insertions(+), 44 deletions(-)
> create mode 100755 Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
>
> diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> new file mode 100755
> index 000000000000..edf2a2e9ea72
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek PWM Controller Device Tree Bindings
> +
> +maintainers:
> + - Jitao Shi <jitao.shi@mediatek.com>
> + - Xinlei Lee <xinlei.lee@mediatek.com>
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt2701-disp-pwm
> + - mediatek,mt6595-disp-pwm
> + - mediatek,mt8173-disp-pwm
> + - mediatek,mt8183-disp-pwm
mt8183 was not in the original text file binding. Please split this out.
Also, the combination "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm"
is missing.
ChenYu
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + "#pwm-cells":
> + description:
> + Number of cells in a PWM specifier.
> +
> + clocks:
> + items:
> + - description: Main Clock
> + - description: Mm Clock
> +
> + clock-names:
> + items:
> + - const: main
> + - const: mm
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - power-domains
> + - "#pwm-cells"
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mt8183-power.h>
> +
> + pwm: pwm@1100e000 {
> + compatible = "mediatek,mt8183-disp-pwm";
> + reg = <0x1100e000 0x1000>;
> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + #pwm-cells = <2>;
> + clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
> + <&infracfg CLK_INFRA_DISP_PWM>;
> + clock-names = "main", "mm";
> + };
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
> deleted file mode 100644
> index 902b271891ae..000000000000
> --- a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -MediaTek display PWM controller
> -
> -Required properties:
> - - compatible: should be "mediatek,<name>-disp-pwm":
> - - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
> - - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
> - - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
> - - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
> - - reg: physical base address and length of the controller's registers.
> - - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
> - the cell format.
> - - clocks: phandle and clock specifier of the PWM reference clock.
> - - clock-names: must contain the following:
> - - "main": clock used to generate PWM signals.
> - - "mm": sync signals from the modules of mmsys.
> - - pinctrl-names: Must contain a "default" entry.
> - - pinctrl-0: One property must exist for each entry in pinctrl-names.
> - See pinctrl/pinctrl-bindings.txt for details of the property values.
> -
> -Example:
> - pwm0: pwm@1401e000 {
> - compatible = "mediatek,mt8173-disp-pwm",
> - "mediatek,mt6595-disp-pwm";
> - reg = <0 0x1401e000 0 0x1000>;
> - #pwm-cells = <2>;
> - clocks = <&mmsys CLK_MM_DISP_PWM026M>,
> - <&mmsys CLK_MM_DISP_PWM0MM>;
> - clock-names = "main", "mm";
> - pinctrl-names = "default";
> - pinctrl-0 = <&disp_pwm0_pins>;
> - };
> -
> - backlight_lcd: backlight_lcd {
> - compatible = "pwm-backlight";
> - pwms = <&pwm0 0 1000000>;
> - brightness-levels = <
> - 0 16 32 48 64 80 96 112
> - 128 144 160 176 192 208 224 240
> - 255
> - >;
> - default-brightness-level = <9>;
> - power-supply = <&mt6397_vio18_reg>;
> - enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
> - };
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
On 16/02/2022 10:32, xinlei.lee@mediatek.com wrote: > From: Xinlei Lee <xinlei.lee@mediatek.corp-partner.google.com> > > Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format as suggested by maintainer > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.corp-partner.google.com> > --- > .../bindings/pwm/mediatek,pwm-disp.yaml | 71 +++++++++++++++++++ > .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 44 ------------ > 2 files changed, 71 insertions(+), 44 deletions(-) > create mode 100755 Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml > delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt > > diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml > new file mode 100755 > index 000000000000..edf2a2e9ea72 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek PWM Controller Device Tree Bindings This is a Display PWM, not a generic PWM. > + > +maintainers: > + - Jitao Shi <jitao.shi@mediatek.com> > + - Xinlei Lee <xinlei.lee@mediatek.com> > + My comment about pwm schema was ignored. Please include pwm.yaml. > +properties: > + compatible: > + enum: > + - mediatek,mt2701-disp-pwm > + - mediatek,mt6595-disp-pwm > + - mediatek,mt8173-disp-pwm > + - mediatek,mt8183-disp-pwm > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + "#pwm-cells": > + description: > + Number of cells in a PWM specifier. Need a const. Description can be skipped, it's obvious. Best regards, Krzysztof
On Wed, 16 Feb 2022 17:32:48 +0800, xinlei.lee@mediatek.com wrote: > From: Xinlei Lee <xinlei.lee@mediatek.corp-partner.google.com> > > Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format as suggested by maintainer > > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.corp-partner.google.com> > --- > .../bindings/pwm/mediatek,pwm-disp.yaml | 71 +++++++++++++++++++ > .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 44 ------------ > 2 files changed, 71 insertions(+), 44 deletions(-) > create mode 100755 Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml > delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/1593550 pwm@1400a000: compatible:0: 'mediatek,mt7623-disp-pwm' is not one of ['mediatek,mt2701-disp-pwm', 'mediatek,mt6595-disp-pwm', 'mediatek,mt8173-disp-pwm', 'mediatek,mt8183-disp-pwm'] arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dt.yaml arch/arm/boot/dts/mt7623n-rfb-emmc.dt.yaml pwm@1400a000: compatible: ['mediatek,mt7623-disp-pwm', 'mediatek,mt2701-disp-pwm'] is too long arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dt.yaml arch/arm/boot/dts/mt7623n-rfb-emmc.dt.yaml pwm@1400a000: 'oneOf' conditional failed, one must be fixed: arch/arm/boot/dts/mt2701-evb.dt.yaml arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dt.yaml arch/arm/boot/dts/mt7623n-rfb-emmc.dt.yaml pwm@1400a000: 'power-domains' is a required property arch/arm/boot/dts/mt2701-evb.dt.yaml arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dt.yaml arch/arm/boot/dts/mt7623n-rfb-emmc.dt.yaml pwm@1401e000: compatible: ['mediatek,mt8173-disp-pwm', 'mediatek,mt6595-disp-pwm'] is too long arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-evb.dt.yaml pwm@1401e000: 'oneOf' conditional failed, one must be fixed: arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-evb.dt.yaml pwm@1401e000: 'power-domains' is a required property arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-evb.dt.yaml pwm@1401f000: compatible: ['mediatek,mt8173-disp-pwm', 'mediatek,mt6595-disp-pwm'] is too long arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dt.yaml arch/arm64/boot/dts/mediatek/mt8173-evb.dt.yaml
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