drivers/clk/imx/clk-frac-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
From: Wang Qing <wangqing@vivo.com>
do_div() does a 64-by-32 division.
When the divisor is u64, do_div() truncates it to 32 bits, this means it
can test non-zero and be truncated to zero for division.
fix do_div.cocci warning:
WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead.
Signed-off-by: Wang Qing <wangqing@vivo.com>
---
drivers/clk/imx/clk-frac-pll.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
index c703056..90b25e3
--- a/drivers/clk/imx/clk-frac-pll.c
+++ b/drivers/clk/imx/clk-frac-pll.c
@@ -129,11 +129,11 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
parent_rate *= 8;
rate *= 2;
temp64 = rate;
- do_div(temp64, parent_rate);
+ div64_u64(temp64, parent_rate);
divfi = temp64;
temp64 = rate - divfi * parent_rate;
temp64 *= PLL_FRAC_DENOM;
- do_div(temp64, parent_rate);
+ div64_u64(temp64, parent_rate);
divff = temp64;
temp64 = parent_rate;
--
2.7.4
From: Qing Wang <wangqing@vivo.com> > Sent: 09 February 2022 08:37 > > From: Wang Qing <wangqing@vivo.com> > > do_div() does a 64-by-32 division. > When the divisor is u64, do_div() truncates it to 32 bits, this means it > can test non-zero and be truncated to zero for division. What is the domain of parent_rate? Unless it can exceed 2^32 do_div() is correct. Ignore checkpatch. > > fix do_div.cocci warning: > WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead. > > Signed-off-by: Wang Qing <wangqing@vivo.com> > --- > drivers/clk/imx/clk-frac-pll.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c > index c703056..90b25e3 > --- a/drivers/clk/imx/clk-frac-pll.c > +++ b/drivers/clk/imx/clk-frac-pll.c > @@ -129,11 +129,11 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, > parent_rate *= 8; > rate *= 2; > temp64 = rate; > - do_div(temp64, parent_rate); > + div64_u64(temp64, parent_rate); > divfi = temp64; > temp64 = rate - divfi * parent_rate; > temp64 *= PLL_FRAC_DENOM; > - do_div(temp64, parent_rate); > + div64_u64(temp64, parent_rate); > divff = temp64; > > temp64 = parent_rate; > -- > 2.7.4 - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
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