Documentation/arm64/silicon-errata.rst | 6 + arch/arm64/Kconfig | 59 ++++++++++ arch/arm64/include/asm/cputype.h | 2 + arch/arm64/kernel/cpu_errata.c | 27 +++++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 114 ++++++++++++++----- drivers/hwtracing/coresight/coresight-trbe.h | 8 -- 7 files changed, 183 insertions(+), 36 deletions(-)
This series adds three different workarounds in the TRBE driver for Cortex-A510 specific erratas. But first, this adds Cortex-A510 specific cpu part number definition in the platform. This series applies on 5.17-rc1. Relevant errata documents can be found here. https://developer.arm.com/documentation/SDEN2397239/900 https://developer.arm.com/documentation/SDEN2397589/900 Changes in V3: https://lore.kernel.org/all/1641872346-3270-1-git-send-email-anshuman.khandual@arm.com/ - Moved the comment inside trbe_needs_drain_after_disable() - Moved the comment inside trbe_needs_ctxt_sync_after_enable() Changes in V2: https://lore.kernel.org/all/1641517808-5735-1-git-send-email-anshuman.khandual@arm.com/ Accommodated most review comments from the previous version. - Split all patches into CPU errata definition, detection and TRBE workarounds - s/TRBE_WORKAROUND_SYSREG_WRITE_FAILURE/TRBE_NEEDS_DRAIN_AFTER_DISABLE - s/TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE/TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE - s/trbe_may_fail_sysreg_write()/trbe_needs_drain_after_disable() - s/trbe_may_corrupt_with_enable()/trbe_needs_ctxt_sync_after_enable() - Updated Kconfig help message for config ARM64_ERRATUM_1902691 - Updated error message for trbe_is_broken() detection - Added new trblimitr parameter to set_trbe_enabled(), improving performance - Added COMPILE_TEST dependency in the errata, until TRBE part is available Changes in V1: https://lore.kernel.org/lkml/1641359159-22726-1-git-send-email-anshuman.khandual@arm.com/ Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki Poulose <suzuki.poulose@arm.com> Cc: coresight@lists.linaro.org Cc: linux-doc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Anshuman Khandual (7): arm64: Add Cortex-A510 CPU part definition arm64: errata: Add detection for TRBE ignored system register writes arm64: errata: Add detection for TRBE invalid prohibited states arm64: errata: Add detection for TRBE trace data corruption coresight: trbe: Work around the ignored system register writes coresight: trbe: Work around the invalid prohibited states coresight: trbe: Work around the trace data corruption Documentation/arm64/silicon-errata.rst | 6 + arch/arm64/Kconfig | 59 ++++++++++ arch/arm64/include/asm/cputype.h | 2 + arch/arm64/kernel/cpu_errata.c | 27 +++++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/coresight-trbe.c | 114 ++++++++++++++----- drivers/hwtracing/coresight/coresight-trbe.h | 8 -- 7 files changed, 183 insertions(+), 36 deletions(-) -- 2.25.1
On Tue, Jan 25, 2022 at 07:50:30PM +0530, Anshuman Khandual wrote: > This series adds three different workarounds in the TRBE driver for > Cortex-A510 specific erratas. But first, this adds Cortex-A510 specific cpu > part number definition in the platform. This series applies on 5.17-rc1. > > Relevant errata documents can be found here. > > https://developer.arm.com/documentation/SDEN2397239/900 > https://developer.arm.com/documentation/SDEN2397589/900 > > Changes in V3: > > https://lore.kernel.org/all/1641872346-3270-1-git-send-email-anshuman.khandual@arm.com/ > > - Moved the comment inside trbe_needs_drain_after_disable() > - Moved the comment inside trbe_needs_ctxt_sync_after_enable() > > Changes in V2: > > https://lore.kernel.org/all/1641517808-5735-1-git-send-email-anshuman.khandual@arm.com/ > > Accommodated most review comments from the previous version. > > - Split all patches into CPU errata definition, detection and TRBE workarounds > - s/TRBE_WORKAROUND_SYSREG_WRITE_FAILURE/TRBE_NEEDS_DRAIN_AFTER_DISABLE > - s/TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE/TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE > - s/trbe_may_fail_sysreg_write()/trbe_needs_drain_after_disable() > - s/trbe_may_corrupt_with_enable()/trbe_needs_ctxt_sync_after_enable() > - Updated Kconfig help message for config ARM64_ERRATUM_1902691 > - Updated error message for trbe_is_broken() detection > - Added new trblimitr parameter to set_trbe_enabled(), improving performance > - Added COMPILE_TEST dependency in the errata, until TRBE part is available > > Changes in V1: > > https://lore.kernel.org/lkml/1641359159-22726-1-git-send-email-anshuman.khandual@arm.com/ > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Suzuki Poulose <suzuki.poulose@arm.com> > Cc: coresight@lists.linaro.org > Cc: linux-doc@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > > Anshuman Khandual (7): > arm64: Add Cortex-A510 CPU part definition > arm64: errata: Add detection for TRBE ignored system register writes > arm64: errata: Add detection for TRBE invalid prohibited states > arm64: errata: Add detection for TRBE trace data corruption > coresight: trbe: Work around the ignored system register writes > coresight: trbe: Work around the invalid prohibited states > coresight: trbe: Work around the trace data corruption > > Documentation/arm64/silicon-errata.rst | 6 + > arch/arm64/Kconfig | 59 ++++++++++ > arch/arm64/include/asm/cputype.h | 2 + > arch/arm64/kernel/cpu_errata.c | 27 +++++ > arch/arm64/tools/cpucaps | 3 + > drivers/hwtracing/coresight/coresight-trbe.c | 114 ++++++++++++++----- > drivers/hwtracing/coresight/coresight-trbe.h | 8 -- > 7 files changed, 183 insertions(+), 36 deletions(-) I have applied this set and sent a pull request to Catalin for the arm64 portion. Thanks, Mathieu > > -- > 2.25.1 >
Hi Mathieu, On Thu, Jan 27, 2022 at 01:22:20PM -0700, Mathieu Poirier wrote: > On Tue, Jan 25, 2022 at 07:50:30PM +0530, Anshuman Khandual wrote: > > Anshuman Khandual (7): > > arm64: Add Cortex-A510 CPU part definition > > arm64: errata: Add detection for TRBE ignored system register writes > > arm64: errata: Add detection for TRBE invalid prohibited states > > arm64: errata: Add detection for TRBE trace data corruption > > coresight: trbe: Work around the ignored system register writes > > coresight: trbe: Work around the invalid prohibited states > > coresight: trbe: Work around the trace data corruption > > > > Documentation/arm64/silicon-errata.rst | 6 + > > arch/arm64/Kconfig | 59 ++++++++++ > > arch/arm64/include/asm/cputype.h | 2 + > > arch/arm64/kernel/cpu_errata.c | 27 +++++ > > arch/arm64/tools/cpucaps | 3 + > > drivers/hwtracing/coresight/coresight-trbe.c | 114 ++++++++++++++----- > > drivers/hwtracing/coresight/coresight-trbe.h | 8 -- > > 7 files changed, 183 insertions(+), 36 deletions(-) > > I have applied this set and sent a pull request to Catalin for the arm64 > portion. Well, I'm happy for the whole series to go in via Greg's tree or however the coresight patches go in (that's why I acked them). The last three patches depend on the first four, so you might as well send them all together. I'd split the series only if there's a conflict with the arm64 tree (I haven't checked). -- Catalin
On Fri, 28 Jan 2022 at 03:51, Catalin Marinas <catalin.marinas@arm.com> wrote: > > Hi Mathieu, > > On Thu, Jan 27, 2022 at 01:22:20PM -0700, Mathieu Poirier wrote: > > On Tue, Jan 25, 2022 at 07:50:30PM +0530, Anshuman Khandual wrote: > > > Anshuman Khandual (7): > > > arm64: Add Cortex-A510 CPU part definition > > > arm64: errata: Add detection for TRBE ignored system register writes > > > arm64: errata: Add detection for TRBE invalid prohibited states > > > arm64: errata: Add detection for TRBE trace data corruption > > > coresight: trbe: Work around the ignored system register writes > > > coresight: trbe: Work around the invalid prohibited states > > > coresight: trbe: Work around the trace data corruption > > > > > > Documentation/arm64/silicon-errata.rst | 6 + > > > arch/arm64/Kconfig | 59 ++++++++++ > > > arch/arm64/include/asm/cputype.h | 2 + > > > arch/arm64/kernel/cpu_errata.c | 27 +++++ > > > arch/arm64/tools/cpucaps | 3 + > > > drivers/hwtracing/coresight/coresight-trbe.c | 114 ++++++++++++++----- > > > drivers/hwtracing/coresight/coresight-trbe.h | 8 -- > > > 7 files changed, 183 insertions(+), 36 deletions(-) > > > > I have applied this set and sent a pull request to Catalin for the arm64 > > portion. > > Well, I'm happy for the whole series to go in via Greg's tree or however > the coresight patches go in (that's why I acked them). The last three > patches depend on the first four, so you might as well send them all > together. I'd split the series only if there's a conflict with the arm64 > tree (I haven't checked). > Very well - thanks for the follow up. > -- > Catalin
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