[v1] x86_64: Show CR4.PSE on auxiliaries like on BSP

[PATCH] x86_64: Show CR4.PSE on auxiliaries like on BSP

Posted by Hugh Dickins 2 years, 4 months ago

Set CR4.PSE in secondary_startup_64: the Intel SDM is clear that it does
not matter whether it's 0 or 1 when 4-level-pts are enabled, but it's
distracting to find CR4 different on BSP and auxiliaries - on x86_64,
BSP alone got to add the PSE bit, in probe_page_size_mask().

Signed-off-by: Hugh Dickins <hughd@google.com>
---
 arch/x86/kernel/head_64.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index c5b9289837dc..72e36739c407 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -181,8 +181,8 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
 	movl	$0, %ecx
 #endif
 
-	/* Enable PAE mode, PGE and LA57 */
-	orl	$(X86_CR4_PAE | X86_CR4_PGE), %ecx
+	/* Enable PAE mode, PSE, PGE and LA57 */
+	orl	$(X86_CR4_PAE | X86_CR4_PSE | X86_CR4_PGE), %ecx
 #ifdef CONFIG_X86_5LEVEL
 	testl	$1, __pgtable_l5_enabled(%rip)
 	jz	1f
-- 
2.35.3

Re: [PATCH] x86_64: Show CR4.PSE on auxiliaries like on BSP

Posted by Peter Zijlstra 2 years, 4 months ago

On Mon, Aug 14, 2023 at 07:53:18PM -0700, Hugh Dickins wrote:
> Set CR4.PSE in secondary_startup_64: the Intel SDM is clear that it does
> not matter whether it's 0 or 1 when 4-level-pts are enabled, but it's
> distracting to find CR4 different on BSP and auxiliaries - on x86_64,
> BSP alone got to add the PSE bit, in probe_page_size_mask().

Specifically I think the point is that PSE bit is completely without
meaning in long mode IIRC.

But yes, having the same CR4 bits set across BSP and APs is definitely
sane.

Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>

> Signed-off-by: Hugh Dickins <hughd@google.com>
> ---
>  arch/x86/kernel/head_64.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
> index c5b9289837dc..72e36739c407 100644
> --- a/arch/x86/kernel/head_64.S
> +++ b/arch/x86/kernel/head_64.S
> @@ -181,8 +181,8 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
>  	movl	$0, %ecx
>  #endif
>  
> -	/* Enable PAE mode, PGE and LA57 */
> -	orl	$(X86_CR4_PAE | X86_CR4_PGE), %ecx
> +	/* Enable PAE mode, PSE, PGE and LA57 */
> +	orl	$(X86_CR4_PAE | X86_CR4_PSE | X86_CR4_PGE), %ecx
>  #ifdef CONFIG_X86_5LEVEL
>  	testl	$1, __pgtable_l5_enabled(%rip)
>  	jz	1f
> -- 
> 2.35.3
>

[tip: x86/mm] x86_64: Show CR4.PSE on auxiliaries like on BSP

Posted by tip-bot2 for Hugh Dickins 2 years, 2 months ago

The following commit has been merged into the x86/mm branch of tip:

Commit-ID:     f4c5ca9850124fb5715eff06cffb1beed837500c
Gitweb:        https://git.kernel.org/tip/f4c5ca9850124fb5715eff06cffb1beed837500c
Author:        Hugh Dickins <hughd@google.com>
AuthorDate:    Mon, 14 Aug 2023 19:53:18 -07:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Sun, 24 Sep 2023 13:23:54 +02:00

x86_64: Show CR4.PSE on auxiliaries like on BSP

Set CR4.PSE in secondary_startup_64: the Intel SDM is clear that it does
not matter whether it's 0 or 1 when 4-level-pts are enabled, but it's
distracting to find CR4 different on BSP and auxiliaries - on x86_64,
BSP alone got to add the PSE bit, in probe_page_size_mask().

Peter Zijlstra adds:

   "I think the point is that PSE bit is completely without
    meaning in long mode.

    But yes, having the same CR4 bits set across BSP and APs is
    definitely sane."

Signed-off-by: Hugh Dickins <hughd@google.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/103ad03a-8c93-c3e2-4226-f79af4d9a074@google.com
---
 arch/x86/kernel/head_64.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index ea69959..3ddce02 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -180,8 +180,8 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
 	movl	$0, %ecx
 #endif
 
-	/* Enable PAE mode, PGE and LA57 */
-	orl	$(X86_CR4_PAE | X86_CR4_PGE), %ecx
+	/* Enable PAE mode, PSE, PGE and LA57 */
+	orl	$(X86_CR4_PAE | X86_CR4_PSE | X86_CR4_PGE), %ecx
 #ifdef CONFIG_X86_5LEVEL
 	testl	$1, __pgtable_l5_enabled(%rip)
 	jz	1f