The LAN7801 is designed exclusively for external PHYs (unlike the
LAN7800/LAN7850 which have internal PHYs), but lan78xx_mdio_init()
restricts PHY scanning to MDIO addresses 0-7 by setting phy_mask to
~(0xFF). This prevents discovery of external PHYs wired to addresses
outside that range.

One such case is the DP83TC814 100BASE-T1 PHY, which is typically
configured at MDIO address 10 via PHYAD bootstrap pins and goes
undetected with the current mask.

Set phy_mask to 0 for the LAN7801 so that all 32 MDIO addresses are
scanned during bus registration, allowing any external PHY to be
discovered regardless of its address.

Signed-off-by: Martin Pålsson <martin@poleshift.se>
---
 drivers/net/usb/lan78xx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/usb/lan78xx.c b/drivers/net/usb/lan78xx.c
index 00397a807393..9d8f1ff7028d 100644
--- a/drivers/net/usb/lan78xx.c
+++ b/drivers/net/usb/lan78xx.c
@@ -2094,8 +2094,8 @@ static int lan78xx_mdio_init(struct lan78xx_net *dev)
 		dev->mdiobus->phy_mask = ~(1 << 1);
 		break;
 	case ID_REV_CHIP_ID_7801_:
-		/* scan thru PHYAD[2..0] */
-		dev->mdiobus->phy_mask = ~(0xFF);
+		/* scan all 32 MDIO addresses for external PHYs */
+		dev->mdiobus->phy_mask = 0;
 		break;
 	}
 

---
base-commit: ee5492fd88cfc079c19fbeac78e9e53b7f6c04f3
change-id: 20260214-lan78xx-phy-mask-fix-a4260de15a4c

Best regards,
-- 
Martin Pålsson <martin@poleshift.se>

On Sat, Feb 14, 2026 at 12:15:21PM +0000, Martin Pålsson wrote:
> The LAN7801 is designed exclusively for external PHYs (unlike the
> LAN7800/LAN7850 which have internal PHYs), but lan78xx_mdio_init()
> restricts PHY scanning to MDIO addresses 0-7 by setting phy_mask to
> ~(0xFF). This prevents discovery of external PHYs wired to addresses
> outside that range.
> 
> One such case is the DP83TC814 100BASE-T1 PHY, which is typically
> configured at MDIO address 10 via PHYAD bootstrap pins and goes
> undetected with the current mask.
> 
> Set phy_mask to 0 for the LAN7801 so that all 32 MDIO addresses are
> scanned during bus registration, allowing any external PHY to be
> discovered regardless of its address.
> 
> Signed-off-by: Martin Pålsson <martin@poleshift.se>

Since you are submitting this for net, it should have a Fixes: tag.

Also, since this is a 100Base PHY, i assume dev->interface needs to be
PHY_INTERFACE_MODE_MII? But it looks like lan78xx_get_phy() is hard
coding it to PHY_INTERFACE_MODE_RGMII_ID for the 7801. How is this
working out for you?

	Andrew

Hi Andrew.

Thank you for reviewing.

As for the PHY interface mode: the RGMII configuration (including TX/RX 
clock internal delays) is set via the configuration EEPROM on the 
device, so PHY_INTERFACE_MODE_RGMII_ID as set by lan78xx_get_phy() is 
correct for this hardware. The DP83TC814 supports RGMII and the link 
works well as-is, so no change is needed there.

I will resend with the Fixes: tag added.


Best regards

Martin


On 2/16/26 3:54 AM, Andrew Lunn wrote:
> On Sat, Feb 14, 2026 at 12:15:21PM +0000, Martin Pålsson wrote:
>> The LAN7801 is designed exclusively for external PHYs (unlike the
>> LAN7800/LAN7850 which have internal PHYs), but lan78xx_mdio_init()
>> restricts PHY scanning to MDIO addresses 0-7 by setting phy_mask to
>> ~(0xFF). This prevents discovery of external PHYs wired to addresses
>> outside that range.
>>
>> One such case is the DP83TC814 100BASE-T1 PHY, which is typically
>> configured at MDIO address 10 via PHYAD bootstrap pins and goes
>> undetected with the current mask.
>>
>> Set phy_mask to 0 for the LAN7801 so that all 32 MDIO addresses are
>> scanned during bus registration, allowing any external PHY to be
>> discovered regardless of its address.
>>
>> Signed-off-by: Martin Pålsson <martin@poleshift.se>
> Since you are submitting this for net, it should have a Fixes: tag.
>
> Also, since this is a 100Base PHY, i assume dev->interface needs to be
> PHY_INTERFACE_MODE_MII? But it looks like lan78xx_get_phy() is hard
> coding it to PHY_INTERFACE_MODE_RGMII_ID for the 7801. How is this
> working out for you?
>
> 	Andrew

-- 
Best regards / Bästa hälsningar / Mit freundlichen Grüßen

Martin Pålsson
Poleshift AB - Local Automotive Ethernet Solutions
+46 706 26 49 90
martin@poleshift.se

On Mon, Feb 16, 2026 at 05:04:55AM +0000, Martin Pålsson wrote:
> Hi Andrew.
> 
> Thank you for reviewing.
> 
> As for the PHY interface mode: the RGMII configuration (including TX/RX
> clock internal delays) is set via the configuration EEPROM on the device, so
> PHY_INTERFACE_MODE_RGMII_ID as set by lan78xx_get_phy() is correct for this
> hardware. The DP83TC814 supports RGMII and the link works well as-is, so no
> change is needed there.

Ah, i was not expecting a 100Mbps PHY to be using RGMII. But if that
is what it is doing, then fine.

> I will resend with the Fixes: tag added.

Thanks
	Andrew