arch/x86/kernel/cpu/amd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
print_s5_reset_status_mmio() expects to read FCH MMIO on baremetal. VMs
don't have emulated FCH registers, so there is nothing to check. Add an
early exit when running on a hypervisor.
The real motivation is Xen PV domUs can't boot on Zen CPUs. PV domUs
PTE contain system physical addresses - they don't have concept of guest
physical addresses. domUs can only map physical addresses they are
assigned, so a domU fails to map the FCH MMIO addresses. However
set_pte() does not return failure, so ioremap() returns a pointer while
the PTEs are unpopulated. print_s5_reset_status_mmio() faults when
reading through the pointer, breaking the boot. This change fixes Xen
PV domUs booting on Zen CPUs.
dom0 can map the FCH MMIO, but it has X86_FEATURE_HYPERVISOR set. With
this change, it no longer prints the reset reason.
Fixes: ab8131028710 ("x86/CPU/AMD: Print the reason for the last reset")
Cc: stable@vger.kernel.org
Suggested-by: Borislav Petkov <bp@alien8.de>
Signed-off-by: Jason Andryuk <jason.andryuk@amd.com>
---
dom0 could work, but that would require a xen_initial_domain() check.
I've wondered about a different approach: We can't directly check for a
device for the FCH_PM_BASE memory, but maybe we could check for a PCI
ISA Bridge with PCI_VENDOR_ID_AMD. That might be close enough to
indicate real hardware? But it would still be a heuristic, so I'm not
sure how much better that would be.
---
arch/x86/kernel/cpu/amd.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 40463bad1078..580ccc2ce5fc 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1357,7 +1357,8 @@ static __init int print_s5_reset_status_mmio(void)
u32 value;
int i;
- if (!cpu_feature_enabled(X86_FEATURE_ZEN))
+ if (!cpu_feature_enabled(X86_FEATURE_ZEN) ||
+ cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
return 0;
addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value));
--
2.34.1
On 11/3/26 19:30, Jason Andryuk wrote:
> print_s5_reset_status_mmio() expects to read FCH MMIO on baremetal. VMs
> don't have emulated FCH registers, so there is nothing to check. Add an
> early exit when running on a hypervisor.
>
> The real motivation is Xen PV domUs can't boot on Zen CPUs. PV domUs
> PTE contain system physical addresses - they don't have concept of guest
> physical addresses. domUs can only map physical addresses they are
> assigned, so a domU fails to map the FCH MMIO addresses. However
> set_pte() does not return failure, so ioremap() returns a pointer while
> the PTEs are unpopulated. print_s5_reset_status_mmio() faults when
> reading through the pointer, breaking the boot. This change fixes Xen
> PV domUs booting on Zen CPUs.
>
> dom0 can map the FCH MMIO, but it has X86_FEATURE_HYPERVISOR set. With
> this change, it no longer prints the reset reason.
>
> Fixes: ab8131028710 ("x86/CPU/AMD: Print the reason for the last reset")
> Cc: stable@vger.kernel.org
> Suggested-by: Borislav Petkov <bp@alien8.de>
> Signed-off-by: Jason Andryuk <jason.andryuk@amd.com>
> ---
> dom0 could work, but that would require a xen_initial_domain() check.
>
> I've wondered about a different approach: We can't directly check for a
> device for the FCH_PM_BASE memory, but maybe we could check for a PCI
> ISA Bridge with PCI_VENDOR_ID_AMD. That might be close enough to
> indicate real hardware? But it would still be a heuristic, so I'm not
> sure how much better that would be.
> ---
> arch/x86/kernel/cpu/amd.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> index 40463bad1078..580ccc2ce5fc 100644
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -1357,7 +1357,8 @@ static __init int print_s5_reset_status_mmio(void)
> u32 value;
> int i;
>
> - if (!cpu_feature_enabled(X86_FEATURE_ZEN))
> + if (!cpu_feature_enabled(X86_FEATURE_ZEN) ||
> + cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
> return 0;
>
> addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value));
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
On Tue, Nov 03, 2026 at 08:30:25PM -0500, Jason Andryuk wrote:
> print_s5_reset_status_mmio() expects to read FCH MMIO on baremetal. VMs
> don't have emulated FCH registers, so there is nothing to check. Add an
> early exit when running on a hypervisor.
>
> The real motivation is Xen PV domUs can't boot on Zen CPUs. PV domUs
> PTE contain system physical addresses - they don't have concept of guest
> physical addresses. domUs can only map physical addresses they are
> assigned, so a domU fails to map the FCH MMIO addresses. However
> set_pte() does not return failure, so ioremap() returns a pointer while
> the PTEs are unpopulated. print_s5_reset_status_mmio() faults when
> reading through the pointer, breaking the boot. This change fixes Xen
> PV domUs booting on Zen CPUs.
>
> dom0 can map the FCH MMIO, but it has X86_FEATURE_HYPERVISOR set. With
> this change, it no longer prints the reset reason.
>
> Fixes: ab8131028710 ("x86/CPU/AMD: Print the reason for the last reset")
> Cc: stable@vger.kernel.org
> Suggested-by: Borislav Petkov <bp@alien8.de>
> Signed-off-by: Jason Andryuk <jason.andryuk@amd.com>
> ---
> dom0 could work, but that would require a xen_initial_domain() check.
>
> I've wondered about a different approach: We can't directly check for a
> device for the FCH_PM_BASE memory, but maybe we could check for a PCI
> ISA Bridge with PCI_VENDOR_ID_AMD. That might be close enough to
> indicate real hardware? But it would still be a heuristic, so I'm not
> sure how much better that would be.
Maybe, I had an older version that used the smbus device / i2c driver.
https://lore.kernel.org/all/20230407203720.18184-1-yazen.ghannam@amd.com/
Is this available in dom0?
> ---
> arch/x86/kernel/cpu/amd.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> index 40463bad1078..580ccc2ce5fc 100644
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -1357,7 +1357,8 @@ static __init int print_s5_reset_status_mmio(void)
> u32 value;
> int i;
>
> - if (!cpu_feature_enabled(X86_FEATURE_ZEN))
> + if (!cpu_feature_enabled(X86_FEATURE_ZEN) ||
> + cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
> return 0;
>
> addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value));
> --
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Thanks,
Yazen
On 2026-11-04 10:18, Yazen Ghannam wrote:
> On Tue, Nov 03, 2026 at 08:30:25PM -0500, Jason Andryuk wrote:
>> print_s5_reset_status_mmio() expects to read FCH MMIO on baremetal. VMs
>> don't have emulated FCH registers, so there is nothing to check. Add an
>> early exit when running on a hypervisor.
>>
>> The real motivation is Xen PV domUs can't boot on Zen CPUs. PV domUs
>> PTE contain system physical addresses - they don't have concept of guest
>> physical addresses. domUs can only map physical addresses they are
>> assigned, so a domU fails to map the FCH MMIO addresses. However
>> set_pte() does not return failure, so ioremap() returns a pointer while
>> the PTEs are unpopulated. print_s5_reset_status_mmio() faults when
>> reading through the pointer, breaking the boot. This change fixes Xen
>> PV domUs booting on Zen CPUs.
>>
>> dom0 can map the FCH MMIO, but it has X86_FEATURE_HYPERVISOR set. With
>> this change, it no longer prints the reset reason.
>>
>> Fixes: ab8131028710 ("x86/CPU/AMD: Print the reason for the last reset")
>> Cc: stable@vger.kernel.org
>> Suggested-by: Borislav Petkov <bp@alien8.de>
>> Signed-off-by: Jason Andryuk <jason.andryuk@amd.com>
>> ---
>> dom0 could work, but that would require a xen_initial_domain() check.
>>
>> I've wondered about a different approach: We can't directly check for a
>> device for the FCH_PM_BASE memory, but maybe we could check for a PCI
>> ISA Bridge with PCI_VENDOR_ID_AMD. That might be close enough to
>> indicate real hardware? But it would still be a heuristic, so I'm not
>> sure how much better that would be.
>
> Maybe, I had an older version that used the smbus device / i2c driver.
> https://lore.kernel.org/all/20230407203720.18184-1-yazen.ghannam@amd.com/
>
> Is this available in dom0?
lspci shows 00:14.0 FCH SMBus Controller
Kernel driver in use: piix4_smbus
Kernel modules: i2c_piix4, sp5100_tco
so, yes, it seems so.
>> ---
>> arch/x86/kernel/cpu/amd.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
>> index 40463bad1078..580ccc2ce5fc 100644
>> --- a/arch/x86/kernel/cpu/amd.c
>> +++ b/arch/x86/kernel/cpu/amd.c
>> @@ -1357,7 +1357,8 @@ static __init int print_s5_reset_status_mmio(void)
>> u32 value;
>> int i;
>>
>> - if (!cpu_feature_enabled(X86_FEATURE_ZEN))
>> + if (!cpu_feature_enabled(X86_FEATURE_ZEN) ||
>> + cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
>> return 0;
>>
>> addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value));
>> --
>
> Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Thanks,
Jason
On 04.11.26 02:30, Jason Andryuk wrote:
> print_s5_reset_status_mmio() expects to read FCH MMIO on baremetal. VMs
> don't have emulated FCH registers, so there is nothing to check. Add an
> early exit when running on a hypervisor.
>
> The real motivation is Xen PV domUs can't boot on Zen CPUs. PV domUs
> PTE contain system physical addresses - they don't have concept of guest
> physical addresses. domUs can only map physical addresses they are
> assigned, so a domU fails to map the FCH MMIO addresses. However
> set_pte() does not return failure, so ioremap() returns a pointer while
> the PTEs are unpopulated. print_s5_reset_status_mmio() faults when
> reading through the pointer, breaking the boot. This change fixes Xen
> PV domUs booting on Zen CPUs.
>
> dom0 can map the FCH MMIO, but it has X86_FEATURE_HYPERVISOR set. With
> this change, it no longer prints the reset reason.
>
> Fixes: ab8131028710 ("x86/CPU/AMD: Print the reason for the last reset")
> Cc: stable@vger.kernel.org
> Suggested-by: Borislav Petkov <bp@alien8.de>
> Signed-off-by: Jason Andryuk <jason.andryuk@amd.com>
Reviewed-by: Juergen Gross <jgross@suse.com>
Juergen
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