[PATCH v3] arm: Fix PT_PT table descriptor value and comment

Gabriel Quintáns Souto posted 1 patch 4 days, 23 hours ago
Failed in applying to current master (apply log)
xen/arch/arm/arm32/mmu/head.S | 2 +-
xen/arch/arm/arm64/mmu/head.S | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
[PATCH v3] arm: Fix PT_PT table descriptor value and comment
Posted by Gabriel Quintáns Souto 4 days, 23 hours ago
Per ARMv7-A/ARMv8-A ARM, bits [11:2] of table descriptors are
ignored by hardware. The original comment incorrectly described
block/page descriptor fields which are not present in table
descriptors.

Use the minimal valid encoding for table descriptors by setting
PT_PT to 0x3.

This updates both arm32 and arm64 for consistency.

Signed-off-by: Gabriel Quintáns Souto <gabi.qs.mail@gmail.com>
---
Changes in v3:
- Use 0x3 instead of 0x403

Changes in v2:
- Apply fix to both arm32 and arm64
- Use 0x403 instead of 0x743
---
 xen/arch/arm/arm32/mmu/head.S | 2 +-
 xen/arch/arm/arm64/mmu/head.S | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/arm32/mmu/head.S b/xen/arch/arm/arm32/mmu/head.S
index cab7be0621..3731322f7e 100644
--- a/xen/arch/arm/arm32/mmu/head.S
+++ b/xen/arch/arm/arm32/mmu/head.S
@@ -8,7 +8,7 @@
 #include <asm/page.h>
 #include <asm/early_printk.h>
 
-#define PT_PT     0x403 /* AF=1 T=1 P=1 (bits [11:2] ignored in table descriptors) */
+#define PT_PT     0x3   /* T=1 P=1 */
 #define PT_MEM    0xf7d /* nG=1 AF=1 SH=11 AP=01 NS=1 ATTR=111 T=0 P=1 */
 #define PT_MEM_L3 0xf7f /* nG=1 AF=1 SH=11 AP=01 NS=1 ATTR=111 T=1 P=1 */
 #define PT_DEV    0xe71 /* nG=1 AF=1 SH=10 AP=01 NS=1 ATTR=100 T=0 P=1 */
diff --git a/xen/arch/arm/arm64/mmu/head.S b/xen/arch/arm/arm64/mmu/head.S
index 375d703d9b..8e514d2114 100644
--- a/xen/arch/arm/arm64/mmu/head.S
+++ b/xen/arch/arm/arm64/mmu/head.S
@@ -8,7 +8,7 @@
 #include <asm/page.h>
 #include <asm/early_printk.h>
 
-#define PT_PT     0x403 /* AF=1 T=1 P=1 (bits [11:2] ignored in table descriptors) */
+#define PT_PT     0x3   /* T=1 P=1 */
 #define PT_MEM    0xf7d /* nG=1 AF=1 SH=11 AP=01 NS=1 ATTR=111 T=0 P=1 */
 #define PT_MEM_L3 0xf7f /* nG=1 AF=1 SH=11 AP=01 NS=1 ATTR=111 T=1 P=1 */
 #define PT_DEV    0xe71 /* nG=1 AF=1 SH=10 AP=01 NS=1 ATTR=100 T=0 P=1 */
-- 
2.54.0


Re: [PATCH v3] arm: Fix PT_PT table descriptor value and comment
Posted by Julien Grall 4 days, 12 hours ago
Hi Gabriel,

For the future, when sending a new version, please create a new thread 
rather than in reply to the latest response.

On 18/05/2026 22:00, Gabriel Quintáns Souto wrote:
> Per ARMv7-A/ARMv8-A ARM, bits [11:2] of table descriptors are
> ignored by hardware. The original comment incorrectly described
> block/page descriptor fields which are not present in table
> descriptors.

Do you have more details why this change? Is this to strictly follow the 
Arm Arm?

In the ideal situation we should have the page table descriptors 
consistent between the assembly and the C version (see 
mfn_to_xen_entry()). They were diverging before and this is still 
diverging. If we are concerned about setting AF here, then we ought to 
modify the C versions as well.

It could be done separately though.

> 
> Use the minimal valid encoding for table descriptors by setting
> PT_PT to 0x3.
> 
> This updates both arm32 and arm64 for consistency.
 > > Signed-off-by: Gabriel Quintáns Souto <gabi.qs.mail@gmail.com>

Reviewed-by: Julien Grall <julien@xen.org>

Cheers,

-- 
Julien Grall


Re: [PATCH v3] arm: Fix PT_PT table descriptor value and comment
Posted by Orzel, Michal 4 days, 12 hours ago

On 18-May-26 23:00, Gabriel Quintáns Souto wrote:
> Per ARMv7-A/ARMv8-A ARM, bits [11:2] of table descriptors are
> ignored by hardware. The original comment incorrectly described
> block/page descriptor fields which are not present in table
> descriptors.
> 
> Use the minimal valid encoding for table descriptors by setting
> PT_PT to 0x3.
> 
> This updates both arm32 and arm64 for consistency.
> 
> Signed-off-by: Gabriel Quintáns Souto <gabi.qs.mail@gmail.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>

~Michal