From: Penny Zheng <Penny.Zheng@arm.com>
As MPU systems only have one secure state, we have to use secure EL2
hypervisor timer for Xen in secure EL2.
Signed-off-by: Penny Zheng <penny.zheng@arm.com>
Signed-off-by: Wei Chen <wei.chen@arm.com>
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Signed-off-by: Harry Ramsey <harry.ramsey@arm.com>
Reviewed-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
Acked-by: Michal Orzel <michal.orzel@amd.com>
---
v4:
- No changes
v3:
- Add Ayan R-by
- Add Michal A-by
v2:
- Remove unncessary kconfig attribute.
- Remove unncessary hypervisor timer macro.
---
xen/arch/arm/include/asm/arm64/sysregs.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h
index 7dfd20414d..19d409d3eb 100644
--- a/xen/arch/arm/include/asm/arm64/sysregs.h
+++ b/xen/arch/arm/include/asm/arm64/sysregs.h
@@ -462,6 +462,17 @@
#define ZCR_ELx_LEN_SIZE 9
#define ZCR_ELx_LEN_MASK 0x1ff
+#ifdef CONFIG_MPU
+/*
+ * The Armv8-R AArch64 architecture always executes code in Secure
+ * state with EL2 as the highest exception level.
+ *
+ * Hypervisor timer registers for Secure EL2.
+ */
+#define CNTHP_CTL_EL2 CNTHPS_CTL_EL2
+#define CNTHP_CVAL_EL2 CNTHPS_CVAL_EL2
+#endif
+
#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */
#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */
#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */
--
2.43.0