From nobody Mon Jan 26 09:20:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=arm.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 176840089942621.82117890649124; Wed, 14 Jan 2026 06:28:19 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1203212.1518506 (Exim 4.92) (envelope-from ) id 1vg1qp-0003lx-94; Wed, 14 Jan 2026 14:27:59 +0000 Received: by outflank-mailman (output) from mailman id 1203212.1518506; Wed, 14 Jan 2026 14:27:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vg1qp-0003lO-3D; Wed, 14 Jan 2026 14:27:59 +0000 Received: by outflank-mailman (input) for mailman id 1203212; Wed, 14 Jan 2026 14:27:57 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vg1qn-0002lw-NE for xen-devel@lists.xenproject.org; Wed, 14 Jan 2026 14:27:57 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id 38598b2a-f155-11f0-b15e-2bf370ae4941; Wed, 14 Jan 2026 15:27:57 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BD49D1655; Wed, 14 Jan 2026 06:27:49 -0800 (PST) Received: from e134099.cambridge.arm.com (e134099.arm.com [10.1.198.34]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0AF2E3F632; Wed, 14 Jan 2026 06:27:54 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 38598b2a-f155-11f0-b15e-2bf370ae4941 From: Harry Ramsey To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Luca Fancellu , Ayan Kumar Halder Subject: [PATCH v4 5/6] arm: Use secure hypervisor timer in MPU system Date: Wed, 14 Jan 2026 14:27:33 +0000 Message-ID: <20260114142734.239197-6-harry.ramsey@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260114142734.239197-1-harry.ramsey@arm.com> References: <20260114142734.239197-1-harry.ramsey@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1768400901427158500 Content-Type: text/plain; charset="utf-8" From: Penny Zheng As MPU systems only have one secure state, we have to use secure EL2 hypervisor timer for Xen in secure EL2. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Harry Ramsey Reviewed-by: Ayan Kumar Halder Acked-by: Michal Orzel --- v4: - No changes v3: - Add Ayan R-by - Add Michal A-by v2: - Remove unncessary kconfig attribute. - Remove unncessary hypervisor timer macro. --- xen/arch/arm/include/asm/arm64/sysregs.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index 7dfd20414d..19d409d3eb 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,17 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +#ifdef CONFIG_MPU +/* + * The Armv8-R AArch64 architecture always executes code in Secure + * state with EL2 as the highest exception level. + * + * Hypervisor timer registers for Secure EL2. + */ +#define CNTHP_CTL_EL2 CNTHPS_CTL_EL2 +#define CNTHP_CVAL_EL2 CNTHPS_CVAL_EL2 +#endif + #define REGION_TEXT_PRBAR 0x38 /* SH=3D11 AP=3D10 XN=3D00 */ #define REGION_RO_PRBAR 0x3A /* SH=3D11 AP=3D10 XN=3D10 */ #define REGION_DATA_PRBAR 0x32 /* SH=3D11 AP=3D00 XN=3D10 */ --=20 2.43.0