This series introduces bugs fixes that were found while bringing up CI
support for the HiFive Premier P550 board with a basic smoke test. The
board-support series itself will follow separately as it depends on
PLIC/vPLIC and dom0less support that have not been upstreamed yet. This
series carries only the independent fixes found along the way, none of them
need the board-support series to apply.
This series:
1: Rename PTE "permissions" to "pte_flags"
2: Always preset A/D bits in G-stage PTEs
3: Fix A/D bit handling in Xen's page-table mappings
4: Use pte_is_valid() in pte_is_mapping()
CI pipeline:
https://gitlab.com/xen-project/people/baptleduc/xen/-/pipelines/2900391526
---
Changes since v3:
- Drop v3 patches 1, 6 already upstreamed:
861e44a3ba8e ("xen/riscv: make Zihintpause no longer a required
extension")
469d83d42f5c ("docs/riscv: sync required ISA extensions with
required_extensions[]")
- Add trailers (A-by and/or R-by).
- Rename patch 3 to ("xen/riscv: always preset A/D bits in G-stage PTEs")
as it now always presets A/D bits instead of distinguish Svadu/Svade DT
bindings cases.
- Address review comments.
- Link to v3: https://patch.msgid.link/1790699381.8631fc262581453bbf619ec5b2062170.1a0ee00218b000b504@vates.tech
---
Changes since v2:
- Drop v2 patches 5 and 6, already upstreamed:
d8ca89f26c8a ("xen/riscv: flush speculatively cached Bare-mode TLB entries in turn_on_mmu()")
08a898b93d21 ("xen/riscv: fix level_map_mask truncation on load_start")
- Drop "xen/riscv: make Svpbmt no longer a required extension".
It relaxed Svpbmt so boards without it, like the HiFive P550, could boot.
But without Svpbmt, DMA-noncoherent devices do not snoop the CPU caches
and can read stale data from DRAM. Mainline Linux has the same problem,
which is explained and reproducible in [1]. Fixing it needs a lot of
machinery we do not need yet, and Svpbmt is mandatory in RVA23, so
keeping it required is simpler and safer. An RFC will follow with a fix
inspired by [2].
- Add three new patches:
docs/riscv: sync required ISA extensions with required_extensions[]
xen/riscv: rename PTE "permissions" to "pte_flags"
xen/riscv: use pte_is_valid() in pte_is_mapping()
- Address review comments.
[1] https://github.com/davidlohr/vanilla-kernel-sifive-p550/tree/master
[2] https://lwn.net/Articles/996819/
---
Changes since v1:
- address ML comments
- rename some patchs
- add new patch-fix: 242dd1f890e4 ("xen/riscv: fix level_map_mask
truncation on load_start") discovered when working on Spacemit K3 support
---
To: xen-devel@lists.xenproject.org
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Anthony PERARD <anthony.perard@vates.tech>
Cc: Michal Orzel <michal.orzel@amd.com>
Cc: Jan Beulich <jbeulich@suse.com>
Cc: Julien Grall <julien@xen.org>
Cc: Roger Pau Monné <roger@xenproject.org>
Cc: Stefano Stabellini <sstabellini@kernel.org>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Connor Davis <connojdavis@gmail.com>
Cc: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Cc: Zheng Zhang <Zheng Zhang <zhangzheng@iscas.ac.cn>
---
Baptiste Le Duc (4):
xen/riscv: rename PTE "permissions" to "pte_flags"
xen/riscv: always preset A/D bits in G-stage PTEs
xen/riscv: fix A/D bits in Xen's page-table mappings
xen/riscv: use pte_is_valid() in pte_is_mapping()
xen/arch/riscv/cpufeature.c | 1 -
xen/arch/riscv/include/asm/mm.h | 5 +++--
xen/arch/riscv/include/asm/page.h | 35 ++++++++++++++++----------------
xen/arch/riscv/mm.c | 14 ++++++-------
xen/arch/riscv/p2m.c | 42 ++++++++++-----------------------------
5 files changed, 37 insertions(+), 60 deletions(-)
---
base-commit: 4c1aba82cff95ab11f7fe4af8965a06703537288
change-id: 20260902-riscv-fix-boot-missing-ext-a79c23bad694
Best regards,
--
Baptiste Le Duc <baptiste.le-duc@vates.tech>