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Thu, 01 Oct 2026 09:07:29 +0000 Received: from leducb.home (lfbn-gre-1-371-96.w90-112.abo.wanadoo.fr [90.112.87.96]) (Authenticated sender: baptiste.le-duc) by mail2.vates.fr (Postfix) with ESMTPSA id 7AEC782407; Thu, 1 Oct 2026 11:07:28 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=hIXBqLlDxx0K/kQnZq8JWDabTK1TpS/NxsX703pn8ic=; h=from:subject:date:message-id:to:cc:mime-version:content-type:content-transfer-encoding:in-reply-to:references:feedback-id; b=H3+O53pYPeRZ9qrUglXRshbWWs397qeocUlaJUObrmfCZ8sfVX9ZgGQqIqBTIs06KI4b3YkH7 aQN0O1JEdDdpUxBpwUF5oTLVs7Qf0OGvRUO5SUdRN2dGE3DOBsJqzaHkNvXDdAfwTiroF03mtVf vlc+IlBj7OwWBn1o02I0t3xqArX1FbcFYx0UOGiez5WO+asR7SZQpC0cRfLevCU5969iFAv3Xt5 gO/DBvU/nwP7FiE0L/JAR3rfCI4F01UGyiOnspQE98frIeAEp1Xy8MJhsu1Od23WHmsF40Swmgc La5VN/qDHT5J/62Om+bSICbRwQ1702FkTPp04DEP7h1Q== X-Zone-Loop: 2004158124ce4150e84e21f7f2c5d74ccb3b91e1583f x-campaign-type: default x-transaction-id: 0f6fabbf-ea14-4bbe-8d6c-5c8504b73a66 x-swg-uid: 01-4623a960-a353-4396-94b7-ca4492c5c873 X-Mailer: Sweego Message-ID: <1790845649.8631fc262581453bbf619ec5b2062170.1a0f6b801920003f66@vates.tech> x-swg-bid: 1790845649.8631fc262581453bbf619ec5b2062170.1a0f6b801920003f66 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Baptiste Le Duc To: xen-devel@lists.xenproject.org Cc: Baptiste Le Duc , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Alistair Francis , Connor Davis , Oleksii Kurochko Subject: [PATCH v4 1/4] xen/riscv: rename PTE "permissions" to "pte_flags" Date: Thu, 1 Oct 2026 11:07:20 +0200 In-Reply-To: <1790845467.8631fc262581453bbf619ec5b2062170.1a0f6b5397a0003f66@vates.tech> References: <1790845467.8631fc262581453bbf619ec5b2062170.1a0f6b5397a0003f66@vates.tech> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1790845141; l=3824; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=XdiiczWFyM/LIOzMORFXdmlnH1HzIt2R6VuUNrV2b20=; b=zSkFUNXea73u4ALYVErAA0YFHJ6H5j9PC7kfm/v/aFUM/NiaZducfZe4uz43GsxUbm1YyQnsn NqcNyHeILROCMkDkEwnEXSBfcxbozateW2s8FIrLeoGbQ7JztEFGtzX X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1790845648690 X-purgate-ID: tlsNG-42698a/1790845652-1BAD09EA-4C94B252/10/78276251493 X-purgate-type: spam X-purgate-size: 3826 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1790845677627158500 paddr_to_pte()'s "permissions" parameter, the matching local in setup_initial_mapping() and p2m_set_permission() don't only deal with permission bits: they also handle PTE_VALID, PTE_USER, PTE_ACCESSED and PTE_DIRTY. Rename them to "pte_flags" and p2m_set_pte_flags() respectively. No functional change. Requested-by: Jan Beulich Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc Acked-by: Jan Beulich Reviewed-by: Oleksii Kurochko --- Changes since v3: - apply nits: fix indention and line length --- Changes since v2: - new patch --- xen/arch/riscv/include/asm/mm.h | 5 +++-- xen/arch/riscv/mm.c | 12 +++++------- xen/arch/riscv/p2m.c | 4 ++-- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/m= m.h index 9e28c24954..1ac66283ec 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -22,9 +22,10 @@ extern vaddr_t directmap_virt_start; #define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) =20 static inline pte_t paddr_to_pte(paddr_t paddr, - unsigned int permissions) + unsigned int pte_flags) { - return (pte_t) { .pte =3D (paddr_to_pfn(paddr) << PTE_PPN_SHIFT) | per= missions }; + return (pte_t) { .pte =3D (paddr_to_pfn(paddr) << PTE_PPN_SHIFT) | + pte_flags }; } =20 static inline paddr_t pte_to_paddr(pte_t pte) diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 610d111945..a9bce48f4a 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -140,22 +140,20 @@ static void __init setup_initial_mapping(struct mmu_d= esc *mmu_desc, case 1: /* Level 0 */ { unsigned long paddr =3D (page_addr - map_start) + pa_start; - unsigned int permissions =3D PTE_LEAF_DEFAULT; + unsigned int pte_flags =3D PTE_LEAF_DEFAULT; unsigned long addr =3D is_identity_mapping ? page_addr : virt_to_maddr(page_addr= ); pte_t pte_to_be_written; =20 index =3D pt_index(0, page_addr); =20 - if ( is_kernel_text(addr) || - is_kernel_inittext(addr) ) - permissions =3D - PTE_EXECUTABLE | PTE_READABLE | PTE_VALID; + if ( is_kernel_text(addr) || is_kernel_inittext(addr) ) + pte_flags =3D PTE_EXECUTABLE | PTE_READABLE | PTE_VALI= D; =20 if ( is_kernel_rodata(addr) ) - permissions =3D PTE_READABLE | PTE_VALID; + pte_flags =3D PTE_READABLE | PTE_VALID; =20 - pte_to_be_written =3D paddr_to_pte(paddr, permissions); + pte_to_be_written =3D paddr_to_pte(paddr, pte_flags); =20 if ( !pte_is_valid(pgtbl[index]) ) pgtbl[index] =3D pte_to_be_written; diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index 1cea86512c..f7b380b90a 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -584,7 +584,7 @@ static inline void p2m_clean_pte(pte_t *p, bool clean_c= ache) p2m_write_pte(p, pte, clean_cache); } =20 -static void p2m_set_permission(pte_t *e, p2m_type_t t) +static void p2m_set_pte_flags(pte_t *e, p2m_type_t t) { e->pte &=3D ~PTE_ACCESS_MASK; =20 @@ -676,7 +676,7 @@ static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, break; } =20 - p2m_set_permission(&e, t); + p2m_set_pte_flags(&e, t); p2m_set_type(&e, t, ctx); } else --=20 2.55.0 From nobody Fri Oct 23 15:34:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1790845674; cv=none; d=zohomail.com; s=zohoarc; b=lls42TqI01hD6/z4MrSUacXlmuOJy0UKtE8mjDpOX7yi2fx/aoKk6P+thEJkM+tRCOiKQJOSknwapNdTU7PKDk9qG1ozsbN+zH+KDejmXo6jqER1jptTy135N97ChwRfb92OESyLI3vo4Fx0iF2dnnssOJLVmCpDo/85AcslOH4= ARC-Message-Signature: i=1; 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charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1790845141; l=5658; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=PoPk/QVFnUoQZeUjxpShJhErKRSH6TrnENPhLu0P/bs=; b=IFSNIfvThy14TSkfMCyitW62vTTvi+Da75QiD9IOIAH6EbRluogl3jupFz+MNHNRCCfOLJv5J mSN2TilZOhTAT72YWtxXjake4w8s++yjR+QHEiwDCBqvxQAOXlJkHrX X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1790845649169 X-purgate-ID: tlsNG-c1860d/1790845655-CE94287B-0F4A9DD1/0/0 X-purgate-type: clean X-purgate-size: 5660 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1790845675808158500 A RISC-V implementation can manage the PTE A/D bits in one of two ways: 1) Update the 'A' and 'D' PTE bits in hardware (ratified as Svadu). 2) Generate a page fault when 'A' and/or 'D' is clear, so that software can set them (ratified as Svade). p2m_set_pte_flags() presets A/D in G-stage PTEs only when the device tree advertises Svade. Platforms that use scheme (2) without advertising Svade, such as the HiFive Premier P550, then hit guest-page faults that Xen does not handle. Always preset A/D in G-stage PTEs so scheme (2) never faults. This is harmless with (1): software just does what hardware would have done on first access. Drop the now-unused svade entry from riscv_isa_ext[], and the TODO about handling A/D faults, since nothing uses that information yet. Fixes: ff14053983b0 ("xen/riscv: Implement p2m_pte_from_mfn() and support P= BMT configuration") Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc --- Changes since v3: - always preset A/D bits in G-stage mappings instead of keying off the DT: it may not reflect what the hardware actually does. - change commit title/message. - drop svade as it is now-unused. --- Changes since v2: - change commit title. - preset A/D bits in p2m_set_pte_flags() if (!svadu || svade), instead of setting RISCV_ISA_EXT_svade in the riscv_isa bitmap for cases 1, 2 and 4. - riscv_resolve_ad_scheme() now only warns when both Svade and Svadu are present and SBI FWFT is missing; drop the dead 'svadu && svade' operand. - repeat XENLOG_WARNING on each line of the warning. - drop ASSERT(svade !=3D svadu) from p2m_set_pte_flags(). - only add the sbi_probe_extension() declaration to sbi.h. - rework the comment in p2m_set_pte_flags(). --- Changes since v1: - change commit title - expose RISCV_ISA_EXT_svadu so the two extensions can be told apart. - move the Svade/Svadu resolution to a new riscv_resolve_ad_scheme(), called once from riscv_fill_hwcap(). - expose sbi_probe_extension() (was static) to probe for SBI FWFT. - stop presetting A/D bits unconditionally in p2m_set_permission(), do it only when Svade is present. --- xen/arch/riscv/cpufeature.c | 1 - xen/arch/riscv/p2m.c | 38 ++++++++------------------------------ 2 files changed, 8 insertions(+), 31 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index aaf544d13f..6d3c15a37f 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -199,7 +199,6 @@ static const struct riscv_isa_ext_entry __initconstrel = riscv_isa_ext[] =3D { RISCV_ISA_EXT_ENTRY(smstateen, ANY), RISCV_ISA_EXT_ENTRY(ssaia, ANY), RISCV_ISA_EXT_ENTRY(sstc, NONE), - RISCV_ISA_EXT_ENTRY(svade, NONE), RISCV_ISA_EXT_ENTRY(svpbmt, NONE), }; =20 diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index f7b380b90a..14cae7dcd7 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -591,38 +591,16 @@ static void p2m_set_pte_flags(pte_t *e, p2m_type_t t) e->pte |=3D PTE_USER; =20 /* - * Two schemes to manage the A and D bits are defined: - * =E2=80=A2 The Svade extension: when a virtual page is accessed an= d the A bit - * is clear, or is written and the D bit is clear, a page-fault - * exception is raised. - * =E2=80=A2 When the Svade extension is not implemented, the follow= ing scheme - * applies. - * When a virtual page is accessed and the A bit is clear, the PTE= is - * updated to set the A bit. When the virtual page is written and = the - * D bit is clear, the PTE is updated to set the D bit. When G-sta= ge - * address translation is in use and is not Bare, the G-stage virt= ual - * pages may be accessed or written by implicit accesses to VS-lev= el - * memory management data structures, such as page tables. - * Thereby to avoid a page-fault in case of Svade is available, it is - * necessary to set A and D bits. + * A RISC-V implementation can either: + * 1) Update the 'A' and 'D' PTE bits in hardware. + * 2) Generate a page fault when 'A' and/or 'D' is clear, so that + * software can set them. * - * TODO: For now, it=E2=80=99s fine to simply set the A/D bits, since = OpenSBI - * delegates page faults to a lower privilege mode and so OpenSBI - * isn't expect to handle page-faults occured in lower modes. - * By setting the A/D bits here, page faults that would otherwise - * be generated due to unset A/D bits will not occur in Xen. - * - * Currently, Xen on RISC-V does not make use of the information - * that could be obtained from handling such page faults, which - * could otherwise be useful for several use cases such as demand - * paging, cache-flushing optimizations, memory access tracking,= etc. - * - * To support the more general case and the optimizations mentio= ned - * above, it would be better to stop setting the A/D bits here a= nd - * instead handle page faults that occur due to unset A/D bits. + * Xen supports both, so set 'A' and 'D' up front to avoid the faults + * of (2). This is harmless with (1): software just does what hardware + * would have done on first access. */ - if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_svade) ) - e->pte |=3D PTE_ACCESSED | PTE_DIRTY; + e->pte |=3D PTE_ACCESSED | PTE_DIRTY; =20 switch ( t ) { --=20 2.55.0 From nobody Fri Oct 23 15:34:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1790845686; cv=none; d=zohomail.com; s=zohoarc; b=b2NLRR44KmsU7eYnu+7xmln6+VN+Fh/ufhq5FKm8ByWBs8637m91Qe6BewJHmVcJo0BMptT58AKitn4BhK7xMsydHeNmGvvcNiTcZ7ZZ994ZmL/kqsECP7gamALVstDxD0uTDuSj5Hp/jKNOUvpD5vKXWVrQgM8LrMQyWojWzWg= ARC-Message-Signature: i=1; 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charset="utf-8" X-Developer-Signature: v=1; a=ed25519-sha256; t=1790845141; l=7385; i=baptiste.le-duc@vates.tech; s=20260810; h=from:subject:message-id; bh=dwsW0rW2RXWzTl0I0RDM6CrL2fok5jqVeN/cSdcD6mc=; b=NImNhHyOZvEnef7AUZniCiif1O8wmWuC7RcJfWGY1oz6sNaQ/pdpZzymOku4WRqNnftWlkZWE hjPhDlxl7xpCOdbVcCiiLg31XRM5Tr5ecugFSfyU5JO7GTiNEQTLHSm X-Developer-Key: i=baptiste.le-duc@vates.tech; a=ed25519; pk=N+BbdvMXRzrCuX/ieh4RWodiAKcLNvI+KjflcZ0oXCo= Content-Transfer-Encoding: quoted-printable X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1790845649469 X-purgate-ID: tlsNG-42698a/1790845657-A92CC9EA-3C85C45A/0/0 X-purgate-type: clean X-purgate-size: 7387 X-ZohoMail-DKIM: pass (identity @vates.tech) X-ZM-MESSAGEID: 1790845687814158500 Xen does not handle page faults caused by clear A/D bits, so it presets them when creating PTEs. pt_update_entry() does so, but three places build leaf PTEs directly without going through it: setup_initial_mapping() (the boot page tables), check_pgtbl_mode_support() (the temporary root entry used to probe SATP mode support) and arch_pmap_map() (the fixmap). Without Svadu, all three fault on first access. For check_pgtbl_mode_support(), the fault is raised by the instruction fetch right after the SATP write, before any trap handler is set. Add PTE_ACCESSED and PTE_DIRTY to PAGE_HYPERVISOR_RO, and build PAGE_HYPERVISOR_RW and PAGE_HYPERVISOR_RX on top of it. PTE_DIRTY is set in all cases for consistency with pt_update_entry() which sets it at runtime. This fixes arch_pmap_map() for free, since it already builds its PTE from PAGE_HYPERVISOR_RW. Switch setup_initial_mapping() to use these macros for its default, text and rodata permissions, and check_pgtbl_mode_support() to use PAGE_HYPERVISOR_RX for its temporary root entry. The latter drops PTE_WRITABLE, going from RWX to RX, but this is harmless, as that entry only has to make the current instruction stream fetchable between the two CSR_SATP writes, and nothing writes through it. Drop the now-redundant PTE_LEAF_DEFAULT, since converting the last open-coded site above leaves it with no user outside page.h itself. pte_is_table() and pte_is_mapping() both assert that a PTE doesn't use one of the two reserved encodings, (V=3D1, W=3D1, R=3D0) and (V=3D1, X=3D1, W= =3D1, R=3D0), by masking it with PAGE_HYPERVISOR_RW. Now that PAGE_HYPERVISOR_RW also carries A and D, a reserved PTE with A or D set would no longer be caught. Mask with the V, R and W bits explicitly instead, and factor the check out into pte_has_reserved_rwx(). Fixes: e66003e7be19 ("xen/riscv: introduce setup_initial_pages") Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc Reviewed-by: Oleksii Kurochko --- Changes since v3: - rebase patch 2/6 which modified wrong indentation. - change commit message to address review comments. --- Changes since v2: - add fixes commit ref. - add A/D bits to PAGE_HYPERVISOR_RO and derive PAGE_HYPERVISOR_RW/RX from it for consistency with runtime. - introduce pte_is_reserved() to factor out the reserved-encoding assert shared by pte_is_table() and pte_is_mapping(). - reword commit title --- Changes since v1: - change commit title - mention in patch message that arch_pmap_map() is fixed too, via the PAGE_HYPERVISOR_RW change, not just setup_initial_mapping(). - convert check_pgtbl_mode_support()'s temporary root entry to PAGE_HYPERVISOR_RX, as it's harmless. - drop PTE_LEAF_DEFAULT entirely instead of keeping it, now that no site open-codes it anymore. - drop the pte_is_table() comment line that referenced PAGE_HYPERVISOR_RW, now stale. --- xen/arch/riscv/include/asm/page.h | 33 +++++++++++++++++---------------- xen/arch/riscv/mm.c | 8 ++++---- 2 files changed, 21 insertions(+), 20 deletions(-) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index b465a90325..8a3e3e1e66 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -46,12 +46,12 @@ #define PTE_PBMT_NOCACHE BIT(61, UL) #define PTE_PBMT_IO BIT(62, UL) =20 -#define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) #define PTE_TABLE (PTE_VALID) =20 -#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE) -#define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITAB= LE) -#define PAGE_HYPERVISOR_RX (PTE_VALID | PTE_READABLE | PTE_EXECUT= ABLE) +#define PAGE_HYPERVISOR_RO (PTE_VALID | PTE_READABLE | \ + PTE_ACCESSED | PTE_DIRTY) +#define PAGE_HYPERVISOR_RW (PAGE_HYPERVISOR_RO | PTE_WRITABLE) +#define PAGE_HYPERVISOR_RX (PAGE_HYPERVISOR_RO | PTE_EXECUTABLE) =20 #define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW /* @@ -161,31 +161,32 @@ static inline bool pte_is_valid(pte_t p) * X W R Meaning * 0 0 0 Pointer to next level of page table. * 0 0 1 Read-only page. - * 0 1 0 Reserved for future use. + * 0 1 0 Reserved for future use. [1] * 0 1 1 Read-write page. * 1 0 0 Execute-only page. * 1 0 1 Read-execute page. - * 1 1 0 Reserved for future use. + * 1 1 0 Reserved for future use. [2] * 1 1 1 Read-write-execute page. + * + * So if V=3D1 and W=3D1 then R also needs to be 1 as R =3D 0 is reserve= d for + * future use ([1], [2]). */ +static inline bool pte_has_reserved_rwx(pte_t p) +{ + return (p.pte & (PTE_VALID | PTE_READABLE | PTE_WRITABLE)) =3D=3D + (PTE_VALID | PTE_WRITABLE); +} + static inline bool pte_is_table(pte_t p) { - /* - * According to the spec if V=3D1 and W=3D1 then R also needs to be 1 = as - * R =3D 0 is reserved for future use ( look at the Table 4.5 ) so che= ck - * in ASSERT that if (V=3D=3D1 && W=3D=3D1) then R isn't 0. - * - * PAGE_HYPERVISOR_RW contains PTE_VALID too. - */ - ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); + ASSERT(!pte_has_reserved_rwx(p)); =20 return ((p.pte & (PTE_VALID | PTE_ACCESS_MASK)) =3D=3D PTE_VALID); } =20 static inline bool pte_is_mapping(pte_t p) { - /* See pte_is_table() */ - ASSERT(((p.pte & PAGE_HYPERVISOR_RW) !=3D (PTE_VALID | PTE_WRITABLE))); + ASSERT(!pte_has_reserved_rwx(p)); =20 return (p.pte & PTE_VALID) && (p.pte & PTE_ACCESS_MASK); } diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index a9bce48f4a..6f7dcd10b2 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -140,7 +140,7 @@ static void __init setup_initial_mapping(struct mmu_des= c *mmu_desc, case 1: /* Level 0 */ { unsigned long paddr =3D (page_addr - map_start) + pa_start; - unsigned int pte_flags =3D PTE_LEAF_DEFAULT; + unsigned int pte_flags =3D PAGE_HYPERVISOR_RW; unsigned long addr =3D is_identity_mapping ? page_addr : virt_to_maddr(page_addr= ); pte_t pte_to_be_written; @@ -148,10 +148,10 @@ static void __init setup_initial_mapping(struct mmu_d= esc *mmu_desc, index =3D pt_index(0, page_addr); =20 if ( is_kernel_text(addr) || is_kernel_inittext(addr) ) - pte_flags =3D PTE_EXECUTABLE | PTE_READABLE | PTE_VALI= D; + pte_flags =3D PAGE_HYPERVISOR_RX; =20 if ( is_kernel_rodata(addr) ) - pte_flags =3D PTE_READABLE | PTE_VALID; + pte_flags =3D PAGE_HYPERVISOR_RO; =20 pte_to_be_written =3D paddr_to_pte(paddr, pte_flags); =20 @@ -196,7 +196,7 @@ static bool __init check_pgtbl_mode_support(struct mmu_= desc *mmu_desc, =20 index =3D pt_index(page_table_level, aligned_load_start); stage1_pgtbl_root[index] =3D paddr_to_pte(aligned_load_start, - PTE_LEAF_DEFAULT | PTE_EXECUTA= BLE); + PAGE_HYPERVISOR_RX); =20 sfence_vma(); csr_write(CSR_SATP, --=20 2.55.0 From nobody Fri Oct 23 15:34:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; t=1790845673; cv=none; d=zohomail.com; s=zohoarc; b=OczCFYu4wEPAg6tkDxAmtDs8dursYNGn3foF1qcLWqGZ/ut45TZ1ZBHypuVAbWy/9+x0869LjiZD/QOPkczynIycK0b0dmgYErPf5PGuY2OFCYh9U/LAtn8mSmsilQwtQq34ky5A3SyCPVlueCCHzN6IMtRJlGH3TBA/gCWARvo= ARC-Message-Signature: i=1; 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No functional change. Assisted-by: Claude:claude-opus-5 Signed-off-by: Baptiste Le Duc Reviewed-by: Oleksii Kurochko --- Changes since v2: - new patch. --- xen/arch/riscv/include/asm/page.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index 8a3e3e1e66..f9e59e61de 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -188,7 +188,7 @@ static inline bool pte_is_mapping(pte_t p) { ASSERT(!pte_has_reserved_rwx(p)); =20 - return (p.pte & PTE_VALID) && (p.pte & PTE_ACCESS_MASK); + return pte_is_valid(p) && (p.pte & PTE_ACCESS_MASK); } =20 static inline bool pte_is_superpage(pte_t p, unsigned int level) --=20 2.55.0