Currently seabios assumes there is only one pci domain(0), and almost
everything operates on pci domain 0 by default. This patch aims to add
multiple pci domain support for pci_device, while reserve the original
API for compatibility.

The reason to get seabios involved is that the pxb-pcie host bus created
in QEMU is now in a different PCI domain, and its bus number would start
from 0 instead of bus_nr. Actually bus_nr should not be used when in
another non-zero domain. However, QEMU only binds port 0xcf8 and 0xcfc to
bus pcie.0. To avoid bus confliction, we should use other port pairs for
busses under new domains.

Current issues:
* when trying to read config space of pcie_pci_bridge, it actually reads
  out the result of mch. I'm working on this weird behavior.

Changelog:
v2 <- v1:
- Fix bugs in filtering domains when traversing pci devices
- Reformat some hardcoded codes, such as probing the pci device in pci_setup

Zihan Yang (3):
  fw/pciinit: Recognize pxb-pcie-dev device
  pci_device: Add pci domain support
  pci: filter undesired domain when traversing pci

 src/fw/coreboot.c    |   2 +-
 src/fw/csm.c         |   2 +-
 src/fw/mptable.c     |   1 +
 src/fw/paravirt.c    |   3 +-
 src/fw/pciinit.c     | 276 ++++++++++++++++++++++++++++++---------------------
 src/hw/ahci.c        |   1 +
 src/hw/ata.c         |   1 +
 src/hw/esp-scsi.c    |   1 +
 src/hw/lsi-scsi.c    |   1 +
 src/hw/megasas.c     |   1 +
 src/hw/mpt-scsi.c    |   1 +
 src/hw/nvme.c        |   1 +
 src/hw/pci.c         |  69 +++++++------
 src/hw/pci.h         |  42 +++++---
 src/hw/pci_ids.h     |   6 +-
 src/hw/pcidevice.c   |  11 +-
 src/hw/pcidevice.h   |   8 +-
 src/hw/pvscsi.c      |   1 +
 src/hw/sdcard.c      |   1 +
 src/hw/usb-ehci.c    |   1 +
 src/hw/usb-ohci.c    |   1 +
 src/hw/usb-uhci.c    |   1 +
 src/hw/usb-xhci.c    |   1 +
 src/hw/virtio-blk.c  |   1 +
 src/hw/virtio-scsi.c |   1 +
 src/optionroms.c     |   3 +
 26 files changed, 268 insertions(+), 170 deletions(-)

-- 
2.7.4


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Hi,

On 08/09/2018 08:43 AM, Zihan Yang wrote:
> Currently seabios assumes there is only one pci domain(0), and almost
> everything operates on pci domain 0 by default. This patch aims to add
> multiple pci domain support for pci_device, while reserve the original
> API for compatibility.

This is a necessary addition to support your QEMU patches,
Please send a link to the QEMU series on your next re-spin.

> The reason to get seabios involved is that the pxb-pcie host bus created
> in QEMU is now in a different PCI domain, and its bus number would start
> from 0 instead of bus_nr. Actually bus_nr should not be used when in
> another non-zero domain.

That is not necessarily true. As we discussed in QEMU devel
mailing list, it is possible PCI buses of a different domain
to start from a positive bus number.
Both bus_nr and domain_nr support makes sense.

>   However, QEMU only binds port 0xcf8 and 0xcfc to
> bus pcie.0. To avoid bus confliction, we should use other port pairs for
> busses under new domains.

I would skip support for IO based configuration and use only MMCONFIG
for extra root buses.

The question remains: how do we assign MMCONFIG space for
each PCI domain.

Thanks,
Marcel

> Current issues:
> * when trying to read config space of pcie_pci_bridge, it actually reads
>    out the result of mch. I'm working on this weird behavior.
>
> Changelog:
> v2 <- v1:
> - Fix bugs in filtering domains when traversing pci devices
> - Reformat some hardcoded codes, such as probing the pci device in pci_setup
>
> Zihan Yang (3):
>    fw/pciinit: Recognize pxb-pcie-dev device
>    pci_device: Add pci domain support
>    pci: filter undesired domain when traversing pci
>
>   src/fw/coreboot.c    |   2 +-
>   src/fw/csm.c         |   2 +-
>   src/fw/mptable.c     |   1 +
>   src/fw/paravirt.c    |   3 +-
>   src/fw/pciinit.c     | 276 ++++++++++++++++++++++++++++++---------------------
>   src/hw/ahci.c        |   1 +
>   src/hw/ata.c         |   1 +
>   src/hw/esp-scsi.c    |   1 +
>   src/hw/lsi-scsi.c    |   1 +
>   src/hw/megasas.c     |   1 +
>   src/hw/mpt-scsi.c    |   1 +
>   src/hw/nvme.c        |   1 +
>   src/hw/pci.c         |  69 +++++++------
>   src/hw/pci.h         |  42 +++++---
>   src/hw/pci_ids.h     |   6 +-
>   src/hw/pcidevice.c   |  11 +-
>   src/hw/pcidevice.h   |   8 +-
>   src/hw/pvscsi.c      |   1 +
>   src/hw/sdcard.c      |   1 +
>   src/hw/usb-ehci.c    |   1 +
>   src/hw/usb-ohci.c    |   1 +
>   src/hw/usb-uhci.c    |   1 +
>   src/hw/usb-xhci.c    |   1 +
>   src/hw/virtio-blk.c  |   1 +
>   src/hw/virtio-scsi.c |   1 +
>   src/optionroms.c     |   3 +
>   26 files changed, 268 insertions(+), 170 deletions(-)
>


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  Hi,

> >   However, QEMU only binds port 0xcf8 and 0xcfc to
> > bus pcie.0. To avoid bus confliction, we should use other port pairs for
> > busses under new domains.
> 
> I would skip support for IO based configuration and use only MMCONFIG
> for extra root buses.
> 
> The question remains: how do we assign MMCONFIG space for
> each PCI domain.

Allocation-wise it would be easiest to place them above 4G.  Right after
memory, or after etc/reserved-memory-end (if that fw_cfg file is
present), where the 64bit pci bars would have been placed.  Move the pci
bars up in address space to make room.

Only problem is that seabios wouldn't be able to access mmconfig then.

Placing them below 4G would work at least for a few pci domains.  q35
mmconfig bar is placed at 0xb0000000 -> 0xbfffffff, basically for
historical reasons.  Old qemu versions had 2.75G low memory on q35 (up
to 0xafffffff), and I think old machine types still have that for live
migration compatibility reasons.  Modern qemu uses 2G only, to make
gigabyte alignment work.

32bit pci bars are placed above 0xc0000000.  The address space from 2G
to 2.75G (0x8000000 -> 0xafffffff) is unused on new machine types.
Enough room for three additional mmconfig bars (full size), so four
pci domains total if you add the q35 one.

cheers,
  Gerd


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Marcel Apfelbaum <marcel.apfelbaum@gmail.com> 于2018年8月25日周六 下午4:07写道：
>
> Hi,
>
> On 08/09/2018 08:43 AM, Zihan Yang wrote:
> > Currently seabios assumes there is only one pci domain(0), and almost
> > everything operates on pci domain 0 by default. This patch aims to add
> > multiple pci domain support for pci_device, while reserve the original
> > API for compatibility.
>
> This is a necessary addition to support your QEMU patches,
> Please send a link to the QEMU series on your next re-spin.

OK, I will attach the link in later QEMU patches.

> > The reason to get seabios involved is that the pxb-pcie host bus created
> > in QEMU is now in a different PCI domain, and its bus number would start
> > from 0 instead of bus_nr. Actually bus_nr should not be used when in
> > another non-zero domain.
>
> That is not necessarily true. As we discussed in QEMU devel
> mailing list, it is possible PCI buses of a different domain
> to start from a positive bus number.
> Both bus_nr and domain_nr support makes sense.

OK, I think I will still use bus_nr as the start bus when in separate domain.

> >   However, QEMU only binds port 0xcf8 and 0xcfc to
> > bus pcie.0. To avoid bus confliction, we should use other port pairs for
> > busses under new domains.
>
> I would skip support for IO based configuration and use only MMCONFIG
> for extra root buses.
>
> The question remains: how do we assign MMCONFIG space for
> each PCI domain.

Indeed, seabios does not have fixed MMCONFIG space(except for q35 host) yet.

> Thanks,
> Marcel
>
> > Current issues:
> > * when trying to read config space of pcie_pci_bridge, it actually reads
> >    out the result of mch. I'm working on this weird behavior.
> >
> > Changelog:
> > v2 <- v1:
> > - Fix bugs in filtering domains when traversing pci devices
> > - Reformat some hardcoded codes, such as probing the pci device in pci_setup
> >
> > Zihan Yang (3):
> >    fw/pciinit: Recognize pxb-pcie-dev device
> >    pci_device: Add pci domain support
> >    pci: filter undesired domain when traversing pci
> >
> >   src/fw/coreboot.c    |   2 +-
> >   src/fw/csm.c         |   2 +-
> >   src/fw/mptable.c     |   1 +
> >   src/fw/paravirt.c    |   3 +-
> >   src/fw/pciinit.c     | 276 ++++++++++++++++++++++++++++++---------------------
> >   src/hw/ahci.c        |   1 +
> >   src/hw/ata.c         |   1 +
> >   src/hw/esp-scsi.c    |   1 +
> >   src/hw/lsi-scsi.c    |   1 +
> >   src/hw/megasas.c     |   1 +
> >   src/hw/mpt-scsi.c    |   1 +
> >   src/hw/nvme.c        |   1 +
> >   src/hw/pci.c         |  69 +++++++------
> >   src/hw/pci.h         |  42 +++++---
> >   src/hw/pci_ids.h     |   6 +-
> >   src/hw/pcidevice.c   |  11 +-
> >   src/hw/pcidevice.h   |   8 +-
> >   src/hw/pvscsi.c      |   1 +
> >   src/hw/sdcard.c      |   1 +
> >   src/hw/usb-ehci.c    |   1 +
> >   src/hw/usb-ohci.c    |   1 +
> >   src/hw/usb-uhci.c    |   1 +
> >   src/hw/usb-xhci.c    |   1 +
> >   src/hw/virtio-blk.c  |   1 +
> >   src/hw/virtio-scsi.c |   1 +
> >   src/optionroms.c     |   3 +
> >   26 files changed, 268 insertions(+), 170 deletions(-)
> >
>

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