From nobody Sat Apr 20 05:23:09 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1533793480407896.7535918449327; Wed, 8 Aug 2018 22:44:40 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coreboot.org) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1fndlq-0001By-Ry; Thu, 09 Aug 2018 07:46:02 +0200 Received: from mail-pg1-f195.google.com ([209.85.215.195]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1fndlf-0001BO-JF for seabios@seabios.org; Thu, 09 Aug 2018 07:46:00 +0200 Received: by mail-pg1-f195.google.com with SMTP id a14-v6so2191188pgv.10 for ; Wed, 08 Aug 2018 22:44:09 -0700 (PDT) Received: from bloodymary.ipads-lab.se.sjtu.edu.cn (45.78.72.26.16clouds.com. [45.78.72.26]) by smtp.gmail.com with ESMTPSA id j27-v6sm11515584pfj.91.2018.08.08.22.44.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Aug 2018 22:44:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WPxHEHnOpip4IVkRGvwHs+/lwomtZWyAp9yzvgaxhaE=; b=VFJocXTkdSXUxlVNdBkJafXFcDdAj5iJN0IWfZNq6W6bkYOXDdjx5mRuslCBQ6f+i2 KMYffdan3W9Qmd2YMG+yUEFG80MX2Qo0hHvqd4AvGnwCOpRqN44RmjN5WXsP6V/S1+o6 MGPYrhkLr9Rs+AiPaGanRHPvjR8mZ00cXa32QCh0iR2ufuE8XJKFXqcjrr1Ez6YFvWIS zAzm21OWoE0upjtiDwB5hSSrgAXcUNk4xX/1AT9lpheev9i4Xxa1mL6cT356GT6ydove r+I11RHlg1JcfIwpm1bLqXxLhG95G9jMPA5eIITvm7qdLvtvnBi7twNE3+tWl8fpvzhP yYnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WPxHEHnOpip4IVkRGvwHs+/lwomtZWyAp9yzvgaxhaE=; b=bMWSoQMGBCw7AqHNJCmQaLVrQ0WF4GTkPS55v9Yy+qzX0txcVfXR0NbswWvjWjUHBw 1g9r7ufXff2VVePGQmNxZCtgtQB6tDpzMvaaqWXTBmi76XssND0VNnVAcrhqfnZF7cwf FCdexQme1BAtXUuUbdsCJBdYWaEru6G4XkVxAtJFQXFKJchiShqrYQI4WIHRbl/dBdMV L+D6+9p0PGUwpXDlJsXhLXiUmgRgJe4rZWPokQ15NGwEe6wCrZ9KQY1oFJO70Fs2VQ2m 3/6BJZCHtRvntg6s90TUmdrR5+h8ENp3duUYvQe+8xAbLksKhrHB+ne9Xtg2018xoYnu IHEg== X-Gm-Message-State: AOUpUlHv7de842kYBwul0pggaSLf2U8mTWj2QnMQ9pZx09+jn43u4ewR L+hIhivgnLcTmhZgEK+ovL+o4n7uiNs= X-Google-Smtp-Source: AA+uWPwfYKLSS8c5HFsyehpuqPn8W//6X+emRUjehXcmK/2R0HkSj/F8yiRJXyglL5BI9rOYppiT7A== X-Received: by 2002:a62:8913:: with SMTP id v19-v6mr800632pfd.127.1533793447201; Wed, 08 Aug 2018 22:44:07 -0700 (PDT) From: Zihan Yang To: seabios@seabios.org Date: Thu, 9 Aug 2018 13:43:52 +0800 Message-Id: <1533793434-7614-2-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533793434-7614-1-git-send-email-whois.zihan.yang@gmail.com> References: <1533793434-7614-1-git-send-email-whois.zihan.yang@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [RFC v2 1/3] fw/pciinit: Recognize pxb-pcie-dev device X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" QEMU q35 uses pxb-pcie-dev to enable multiple host bridges, this patch recognizes such devices in seabios and add corresponding e820 entry. MCFG base and size are already setup in QEMU, we just need to read it Signed-off-by: Zihan Yang --- src/fw/paravirt.c | 1 - src/fw/pciinit.c | 17 +++++++++++++++++ src/hw/pci_ids.h | 1 + 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 0770c47..6b14542 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -197,7 +197,6 @@ qemu_platform_setup(void) if (!loader_err) warn_internalerror(); } - acpi_setup(); } =20 diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 3a2f747..6e6a434 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -507,11 +507,28 @@ static void mch_mem_addr_setup(struct pci_device *dev= , void *arg) pci_io_low_end =3D acpi_pm_base; } =20 +static void pxb_mem_addr_setup(struct pci_device *dev, void *arg) +{ + union u64_u32_u mcfg_base; + mcfg_base.lo =3D pci_config_readl(dev->bdf, Q35_HOST_BRIDGE_PCIEXBAR); + mcfg_base.hi =3D pci_config_readl(dev->bdf, Q35_HOST_BRIDGE_PCIEXBAR += 4); + + // Fix me! Use another meaningful macro + u32 mcfg_size =3D pci_config_readl(dev->bdf, Q35_HOST_BRIDGE_PCIEXBAR = + 8); + + /* Skip config write here as the qemu-level objects are already setup,= we + * read mcfg_base and mcfg_size from it just now. Instead, we directly= add + * this item to e820 */ + e820_add(mcfg_base.val, mcfg_size, E820_RESERVED); +} + static const struct pci_device_id pci_platform_tbl[] =3D { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, i440fx_mem_addr_setup), PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH, mch_mem_addr_setup), + PCI_DEVICE(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_PXB_HOST, + pxb_mem_addr_setup), PCI_DEVICE_END }; =20 diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 38fa2ca..35096ea 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2265,6 +2265,7 @@ =20 #define PCI_VENDOR_ID_REDHAT 0x1b36 #define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C +#define PCI_DEVICE_ID_REDHAT_PXB_HOST 0x000B =20 #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sat Apr 20 05:23:09 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1533793490226906.1486252294595; Wed, 8 Aug 2018 22:44:50 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coreboot.org) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1fndly-0001Cr-IO; Thu, 09 Aug 2018 07:46:10 +0200 Received: from mail-pl0-f66.google.com ([209.85.160.66]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1fndlj-0001BS-Hz for seabios@seabios.org; Thu, 09 Aug 2018 07:46:08 +0200 Received: by mail-pl0-f66.google.com with SMTP id u11-v6so2067331plq.5 for ; Wed, 08 Aug 2018 22:44:13 -0700 (PDT) Received: from bloodymary.ipads-lab.se.sjtu.edu.cn (45.78.72.26.16clouds.com. [45.78.72.26]) by smtp.gmail.com with ESMTPSA id j27-v6sm11515584pfj.91.2018.08.08.22.44.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Aug 2018 22:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lBMTBRyQPe2S/j3ri/W6Pr8QStmy3p0OZlueboMdLWs=; b=sKEDiizFYD3KPSuf6jum76O+n8SkXMZvUrA4Xs9k87mZByXMW9/rPmG0Y4ItHjPAQH UTSkD1KBldhcyIHWJLL88PEJA3yNvJEDZEO+GE7DF3EtB+Uow7dDesuvDtViG5XMyj3L rXI0oTRc7yRJXW9K3CtiGErGbPTMG01NvKNGIEzJzqwWoKmWHWK/sdAyxc3vVH55jYdo AVYgrHB1v+u/qJyR8cMJcsQjSdksiY6Zzj5e0/9NEnneEjq0Yssz1VphF+MFBr6eF+To H1Ku8waEdooRt/oDraqk8gVFFnJD9a/7kzdChyceD01Jkz+PIC1zV39pphXSe74hJKQo iExA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lBMTBRyQPe2S/j3ri/W6Pr8QStmy3p0OZlueboMdLWs=; b=DdmVbZVT7+XesqzhrnFDe8Lf7tpNAu7iMEEq1UYIoJzNk2+cXv5mKe/NH2pASRYkoM Tdqtihxm9HEOqaT3eN9liQGl4tkhrCd5RkaLPCPDSBX2ZDdEi7bA2jfHCRlNQSAWOa4o 36G9ztzIhOnv6c89Bj4/CvLwoo8xt8j5jeLSnxUSSqt2gyw+1XpT9ItSIpL61HueFHVi N0lI9Op+TY84Q/FV9hoaYcWP7igGoNuGOh4qQ8o+h9NlDkYVbMXB2bsom5OWQcU9XHGG an6JpZNOapCYl35gQItGE9QLfkIiZZdmnhj7smb7eQdWFFEOp8d6Xvozm3JyyVHMf7fa 2XNg== X-Gm-Message-State: AOUpUlF8J4XcXw1aBOyjJ24Tv3kSDn0U+83clGacm7zVjrBR/dLhDwtA GPonH62ridoEVX8JyTAWwi7jZL03pU8= X-Google-Smtp-Source: AA+uWPwQ1XKfxiW7mT+iyQby60JcxBx3nwVzG3t6m39gj2BhmxfdcDqzvFjBZnwhAO/znzIuGHBf/g== X-Received: by 2002:a17:902:a9c8:: with SMTP id b8-v6mr674855plr.343.1533793450678; Wed, 08 Aug 2018 22:44:10 -0700 (PDT) From: Zihan Yang To: seabios@seabios.org Date: Thu, 9 Aug 2018 13:43:53 +0800 Message-Id: <1533793434-7614-3-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533793434-7614-1-git-send-email-whois.zihan.yang@gmail.com> References: <1533793434-7614-1-git-send-email-whois.zihan.yang@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [RFC v2 2/3] pci_device: Add pci domain support X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Most part of seabios assume only PCI domain 0. This patch adds support for multiple domain in pci devices, which involves some API changes. For compatibility, interfaces such as pci_config_read[b|w|l] still exist so that existing domain 0 devices needs no modification, but whenever a device wants to reside in different domain, it should add *_dom suffix to above functions, e.g, pci_config_readl_dom(..., domain_nr) to read from specific host bridge other than q35 host bridge. Also, the user should check the device domain when using foreachpci() macro to fileter undesired devices that reside in a different domain. Signed-off-by: Zihan Yang --- src/fw/coreboot.c | 2 +- src/fw/csm.c | 2 +- src/fw/paravirt.c | 2 +- src/fw/pciinit.c | 261 ++++++++++++++++++++++++++++++-------------------= ---- src/hw/pci.c | 69 +++++++------- src/hw/pci.h | 42 ++++++--- src/hw/pci_ids.h | 7 +- src/hw/pcidevice.c | 8 +- src/hw/pcidevice.h | 4 +- 9 files changed, 227 insertions(+), 170 deletions(-) diff --git a/src/fw/coreboot.c b/src/fw/coreboot.c index 7c0954b..c955dfd 100644 --- a/src/fw/coreboot.c +++ b/src/fw/coreboot.c @@ -254,7 +254,7 @@ coreboot_platform_setup(void) { if (!CONFIG_COREBOOT) return; - pci_probe_devices(); + pci_probe_devices(0); =20 struct cb_memory *cbm =3D CBMemTable; if (!cbm) diff --git a/src/fw/csm.c b/src/fw/csm.c index 03b4bb8..e94f614 100644 --- a/src/fw/csm.c +++ b/src/fw/csm.c @@ -63,7 +63,7 @@ static void csm_maininit(struct bregs *regs) { interface_init(); - pci_probe_devices(); + pci_probe_devices(0); =20 csm_compat_table.PnPInstallationCheckSegment =3D SEG_BIOS; csm_compat_table.PnPInstallationCheckOffset =3D get_pnp_offset(); diff --git a/src/fw/paravirt.c b/src/fw/paravirt.c index 6b14542..ef4d487 100644 --- a/src/fw/paravirt.c +++ b/src/fw/paravirt.c @@ -155,7 +155,7 @@ qemu_platform_setup(void) return; =20 if (runningOnXen()) { - pci_probe_devices(); + pci_probe_devices(0); xen_hypercall_setup(); xen_biostable_setup(); return; diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 6e6a434..fcdcd38 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -51,6 +51,7 @@ u64 pcimem_end =3D BUILD_PCIMEM_END; u64 pcimem64_start =3D BUILD_PCIMEM64_START; u64 pcimem64_end =3D BUILD_PCIMEM64_END; u64 pci_io_low_end =3D 0xa000; +u64 pxb_mcfg_size =3D 0; =20 struct pci_region_entry { struct pci_device *dev; @@ -88,9 +89,9 @@ static void pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int is64) { u32 ofs =3D pci_bar(pci, bar); - pci_config_writel(pci->bdf, ofs, addr); + pci_config_writel_dom(pci->bdf, ofs, addr, pci->domain_nr); if (is64) - pci_config_writel(pci->bdf, ofs + 4, addr >> 32); + pci_config_writel_dom(pci->bdf, ofs + 4, addr >> 32, pci->domain_n= r); } =20 =20 @@ -405,25 +406,29 @@ static void pci_bios_init_device(struct pci_device *p= ci) =20 /* map the interrupt */ u16 bdf =3D pci->bdf; - int pin =3D pci_config_readb(bdf, PCI_INTERRUPT_PIN); + int pin =3D pci_config_readb_dom(bdf, PCI_INTERRUPT_PIN, pci->domain_n= r); if (pin !=3D 0) - pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci, p= in)); + pci_config_writeb_dom(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pc= i, pin), + pci->domain_nr); =20 pci_init_device(pci_device_tbl, pci, NULL); =20 /* enable memory mappings */ - pci_config_maskw(bdf, PCI_COMMAND, 0, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SER= R); + pci_config_maskw_dom(bdf, PCI_COMMAND, 0, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SER= R, + pci->domain_nr); /* enable SERR# for forwarding */ if (pci->header_type & PCI_HEADER_TYPE_BRIDGE) - pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, - PCI_BRIDGE_CTL_SERR); + pci_config_maskw_dom(bdf, PCI_BRIDGE_CONTROL, 0, + PCI_BRIDGE_CTL_SERR, pci->domain_nr); } =20 -static void pci_bios_init_devices(void) +static void pci_bios_init_devices(int domain_nr) { struct pci_device *pci; foreachpci(pci) { + if (pci->domain_nr !=3D domain_nr) + continue; pci_bios_init_device(pci); } } @@ -520,6 +525,10 @@ static void pxb_mem_addr_setup(struct pci_device *dev,= void *arg) * read mcfg_base and mcfg_size from it just now. Instead, we directly= add * this item to e820 */ e820_add(mcfg_base.val, mcfg_size, E820_RESERVED); + + /* Add PXBHosts so that we can can initialize them later */ + ++PXBHosts; + pxb_mcfg_size +=3D mcfg_size; } =20 static const struct pci_device_id pci_platform_tbl[] =3D { @@ -532,27 +541,31 @@ static const struct pci_device_id pci_platform_tbl[] = =3D { PCI_DEVICE_END }; =20 -static void pci_bios_init_platform(void) +static void pci_bios_init_platform(int domain_nr) { struct pci_device *pci; foreachpci(pci) { + if (pci->domain_nr !=3D domain_nr) + continue; pci_init_device(pci_platform_tbl, pci, NULL); } } =20 -static u8 pci_find_resource_reserve_capability(u16 bdf) +static u8 pci_find_resource_reserve_capability(u16 bdf, int domain_nr) { - if (pci_config_readw(bdf, PCI_VENDOR_ID) =3D=3D PCI_VENDOR_ID_REDHAT && - pci_config_readw(bdf, PCI_DEVICE_ID) =3D=3D - PCI_DEVICE_ID_REDHAT_ROOT_PORT) { + if (pci_config_readw_dom(bdf, PCI_VENDOR_ID, domain_nr) =3D=3D PCI_VEN= DOR_ID_REDHAT && + (pci_config_readw_dom(bdf, PCI_DEVICE_ID, domain_nr) =3D=3D + PCI_DEVICE_ID_REDHAT_ROOT_PORT || + pci_config_readw_dom(bdf, PCI_DEVICE_ID, domain_nr) =3D=3D + PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE)) { u8 cap =3D 0; do { - cap =3D pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap); + cap =3D pci_find_capability_dom(bdf, PCI_CAP_ID_VNDR, cap, dom= ain_nr); } while (cap && - pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) != =3D + pci_config_readb_dom(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSE= T, domain_nr) !=3D REDHAT_CAP_RESOURCE_RESERVE); if (cap) { - u8 cap_len =3D pci_config_readb(bdf, cap + PCI_CAP_FLAGS); + u8 cap_len =3D pci_config_readb_dom(bdf, cap + PCI_CAP_FLAGS, = domain_nr); if (cap_len < RES_RESERVE_CAP_SIZE) { dprintf(1, "PCI: QEMU resource reserve cap length %d is in= valid\n", cap_len); @@ -570,7 +583,7 @@ static u8 pci_find_resource_reserve_capability(u16 bdf) ****************************************************************/ =20 static void -pci_bios_init_bus_rec(int bus, u8 *pci_bus) +pci_bios_init_bus_rec(int bus, u8 *pci_bus, int domain_nr) { int bdf; u16 class; @@ -578,54 +591,54 @@ pci_bios_init_bus_rec(int bus, u8 *pci_bus) dprintf(1, "PCI: %s bus =3D 0x%x\n", __func__, bus); =20 /* prevent accidental access to unintended devices */ - foreachbdf(bdf, bus) { - class =3D pci_config_readw(bdf, PCI_CLASS_DEVICE); + foreachbdf_dom(bdf, bus, domain_nr) { + class =3D pci_config_readw_dom(bdf, PCI_CLASS_DEVICE, domain_nr); if (class =3D=3D PCI_CLASS_BRIDGE_PCI) { - pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255); - pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0); + pci_config_writeb_dom(bdf, PCI_SECONDARY_BUS, 255, domain_nr); + pci_config_writeb_dom(bdf, PCI_SUBORDINATE_BUS, 0, domain_nr); } } =20 - foreachbdf(bdf, bus) { - class =3D pci_config_readw(bdf, PCI_CLASS_DEVICE); + foreachbdf_dom(bdf, bus, domain_nr) { + class =3D pci_config_readw_dom(bdf, PCI_CLASS_DEVICE, domain_nr); if (class !=3D PCI_CLASS_BRIDGE_PCI) { continue; } dprintf(1, "PCI: %s bdf =3D 0x%x\n", __func__, bdf); =20 - u8 pribus =3D pci_config_readb(bdf, PCI_PRIMARY_BUS); + u8 pribus =3D pci_config_readb_dom(bdf, PCI_PRIMARY_BUS, domain_nr= ); if (pribus !=3D bus) { dprintf(1, "PCI: primary bus =3D 0x%x -> 0x%x\n", pribus, bus); - pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus); + pci_config_writeb_dom(bdf, PCI_PRIMARY_BUS, bus, domain_nr); } else { dprintf(1, "PCI: primary bus =3D 0x%x\n", pribus); } =20 - u8 secbus =3D pci_config_readb(bdf, PCI_SECONDARY_BUS); + u8 secbus =3D pci_config_readb_dom(bdf, PCI_SECONDARY_BUS, domain_= nr); (*pci_bus)++; if (*pci_bus !=3D secbus) { dprintf(1, "PCI: secondary bus =3D 0x%x -> 0x%x\n", secbus, *pci_bus); secbus =3D *pci_bus; - pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus); + pci_config_writeb_dom(bdf, PCI_SECONDARY_BUS, secbus, domain_n= r); } else { dprintf(1, "PCI: secondary bus =3D 0x%x\n", secbus); } =20 /* set to max for access to all subordinate buses. later set it to accurate value */ - u8 subbus =3D pci_config_readb(bdf, PCI_SUBORDINATE_BUS); - pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255); + u8 subbus =3D pci_config_readb_dom(bdf, PCI_SUBORDINATE_BUS, domai= n_nr); + pci_config_writeb_dom(bdf, PCI_SUBORDINATE_BUS, 255, domain_nr); =20 - pci_bios_init_bus_rec(secbus, pci_bus); + pci_bios_init_bus_rec(secbus, pci_bus, domain_nr); =20 if (subbus !=3D *pci_bus) { u8 res_bus =3D *pci_bus; - u8 cap =3D pci_find_resource_reserve_capability(bdf); + u8 cap =3D pci_find_resource_reserve_capability(bdf, domain_nr= ); =20 if (cap) { - u32 tmp_res_bus =3D pci_config_readl(bdf, - cap + RES_RESERVE_BUS_RES); + u32 tmp_res_bus =3D pci_config_readl_dom(bdf, + cap + RES_RESERVE_BUS_RES, domain_nr); if (tmp_res_bus !=3D (u32)-1) { res_bus =3D tmp_res_bus & 0xFF; if ((u8)(res_bus + secbus) < secbus || @@ -648,44 +661,43 @@ pci_bios_init_bus_rec(int bus, u8 *pci_bus) } else { dprintf(1, "PCI: subordinate bus =3D 0x%x\n", subbus); } - pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus); + pci_config_writeb_dom(bdf, PCI_SUBORDINATE_BUS, subbus, domain_nr); } } =20 static void -pci_bios_init_bus(void) +pci_bios_init_bus(int domain_nr) { - u8 extraroots =3D romfile_loadint("etc/extra-pci-roots", 0); u8 pci_bus =3D 0; =20 - pci_bios_init_bus_rec(0 /* host bus */, &pci_bus); + pci_bios_init_bus_rec(0 /* host bus */, &pci_bus, domain_nr); =20 - if (extraroots) { + if (domain_nr) { while (pci_bus < 0xff) { pci_bus++; - pci_bios_init_bus_rec(pci_bus, &pci_bus); + pci_bios_init_bus_rec(pci_bus, &pci_bus, domain_nr); } } } =20 - /**************************************************************** * Bus sizing ****************************************************************/ =20 static void pci_bios_get_bar(struct pci_device *pci, int bar, - int *ptype, u64 *psize, int *pis64) + int *ptype, u64 *psize, int *pis64, + int domain_nr) { u32 ofs =3D pci_bar(pci, bar); u16 bdf =3D pci->bdf; - u32 old =3D pci_config_readl(bdf, ofs); + u32 old =3D pci_config_readl_dom(bdf, ofs, domain_nr); int is64 =3D 0, type =3D PCI_REGION_TYPE_MEM; u64 mask; =20 if (bar =3D=3D PCI_ROM_SLOT) { mask =3D PCI_ROM_ADDRESS_MASK; - pci_config_writel(bdf, ofs, mask); + pci_config_writel_dom(bdf, ofs, mask, domain_nr); } else { if (old & PCI_BASE_ADDRESS_SPACE_IO) { mask =3D PCI_BASE_ADDRESS_IO_MASK; @@ -697,15 +709,15 @@ pci_bios_get_bar(struct pci_device *pci, int bar, is64 =3D ((old & PCI_BASE_ADDRESS_MEM_TYPE_MASK) =3D=3D PCI_BASE_ADDRESS_MEM_TYPE_64); } - pci_config_writel(bdf, ofs, ~0); + pci_config_writel_dom(bdf, ofs, ~0, domain_nr); } - u64 val =3D pci_config_readl(bdf, ofs); - pci_config_writel(bdf, ofs, old); + u64 val =3D pci_config_readl_dom(bdf, ofs, domain_nr); + pci_config_writel_dom(bdf, ofs, old, domain_nr); if (is64) { - u32 hold =3D pci_config_readl(bdf, ofs + 4); - pci_config_writel(bdf, ofs + 4, ~0); - u32 high =3D pci_config_readl(bdf, ofs + 4); - pci_config_writel(bdf, ofs + 4, hold); + u32 hold =3D pci_config_readl_dom(bdf, ofs + 4, domain_nr); + pci_config_writel_dom(bdf, ofs + 4, ~0, domain_nr); + u32 high =3D pci_config_readl_dom(bdf, ofs + 4, domain_nr); + pci_config_writel_dom(bdf, ofs + 4, hold, domain_nr); val |=3D ((u64)high << 32); mask |=3D ((u64)0xffffffff << 32); *psize =3D (~(val & mask)) + 1; @@ -717,15 +729,20 @@ pci_bios_get_bar(struct pci_device *pci, int bar, } =20 static int pci_bios_bridge_region_is64(struct pci_region *r, - struct pci_device *pci, int type) + struct pci_device *pci, int type, + int domain_nr) { if (type !=3D PCI_REGION_TYPE_PREFMEM) return 0; - u32 pmem =3D pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE); + u32 pmem =3D pci_config_readl_dom(pci->bdf, PCI_PREF_MEMORY_BASE, + domain_nr); if (!pmem) { - pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0xfff0fff0); - pmem =3D pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE); - pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0x0); + pci_config_writel_dom(pci->bdf, PCI_PREF_MEMORY_BASE, 0xfff0fff0, + domain_nr); + pmem =3D pci_config_readl_dom(pci->bdf, PCI_PREF_MEMORY_BASE, + domain_nr); + pci_config_writel_dom(pci->bdf, PCI_PREF_MEMORY_BASE, 0x0, + domain_nr); } if ((pmem & PCI_PREF_RANGE_TYPE_MASK) !=3D PCI_PREF_RANGE_TYPE_64) return 0; @@ -801,13 +818,15 @@ pci_region_create_entry(struct pci_bus *bus, struct p= ci_device *dev, return entry; } =20 -static int pci_bus_hotplug_support(struct pci_bus *bus, u8 pcie_cap) +static int pci_bus_hotplug_support(struct pci_bus *bus, u8 pcie_cap, + int domain_nr) { u8 shpc_cap; =20 if (pcie_cap) { - u16 pcie_flags =3D pci_config_readw(bus->bus_dev->bdf, - pcie_cap + PCI_EXP_FLAGS); + u16 pcie_flags =3D pci_config_readw_dom(bus->bus_dev->bdf, + pcie_cap + PCI_EXP_FLAGS, + domain_nr); u8 port_type =3D ((pcie_flags & PCI_EXP_FLAGS_TYPE) >> (__builtin_ffs(PCI_EXP_FLAGS_TYPE) - 1)); u8 downstream_port =3D (port_type =3D=3D PCI_EXP_TYPE_DOWNSTREAM) = || @@ -826,7 +845,8 @@ static int pci_bus_hotplug_support(struct pci_bus *bus,= u8 pcie_cap) return downstream_port && slot_implemented; } =20 - shpc_cap =3D pci_find_capability(bus->bus_dev->bdf, PCI_CAP_ID_SHPC, 0= ); + shpc_cap =3D pci_find_capability_dom(bus->bus_dev->bdf, PCI_CAP_ID_SHP= C, 0, + domain_nr); return !!shpc_cap; } =20 @@ -835,7 +855,8 @@ static int pci_bus_hotplug_support(struct pci_bus *bus,= u8 pcie_cap) * Note: disables bridge's window registers as a side effect. */ static int pci_bridge_has_region(struct pci_device *pci, - enum pci_region_type region_type) + enum pci_region_type region_type, + int domain_nr) { u8 base; =20 @@ -851,18 +872,20 @@ static int pci_bridge_has_region(struct pci_device *p= ci, return 1; } =20 - pci_config_writeb(pci->bdf, base, 0xFF); + pci_config_writeb_dom(pci->bdf, base, 0xFF, domain_nr); =20 - return pci_config_readb(pci->bdf, base) !=3D 0; + return pci_config_readb_dom(pci->bdf, base, domain_nr) !=3D 0; } =20 -static int pci_bios_check_devices(struct pci_bus *busses) +static int pci_bios_check_devices(struct pci_bus *busses, int domain_nr) { dprintf(1, "PCI: check devices\n"); =20 // Calculate resources needed for regular (non-bus) devices. struct pci_device *pci; foreachpci(pci) { + if (pci->domain_nr !=3D domain_nr) + continue; if (pci->class =3D=3D PCI_CLASS_BRIDGE_PCI) busses[pci->secondary_bus].bus_dev =3D pci; =20 @@ -879,7 +902,7 @@ static int pci_bios_check_devices(struct pci_bus *busse= s) continue; int type, is64; u64 size; - pci_bios_get_bar(pci, i, &type, &size, &is64); + pci_bios_get_bar(pci, i, &type, &size, &is64, domain_nr); if (size =3D=3D 0) continue; =20 @@ -909,14 +932,14 @@ static int pci_bios_check_devices(struct pci_bus *bus= ses) parent =3D &busses[0]; int type; u16 bdf =3D s->bus_dev->bdf; - u8 pcie_cap =3D pci_find_capability(bdf, PCI_CAP_ID_EXP, 0); - u8 qemu_cap =3D pci_find_resource_reserve_capability(bdf); + u8 pcie_cap =3D pci_find_capability_dom(bdf, PCI_CAP_ID_EXP, 0, do= main_nr); + u8 qemu_cap =3D pci_find_resource_reserve_capability(bdf, domain_n= r); =20 - int hotplug_support =3D pci_bus_hotplug_support(s, pcie_cap); + int hotplug_support =3D pci_bus_hotplug_support(s, pcie_cap, domai= n_nr); for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; - if (!pci_bridge_has_region(s->bus_dev, type)) + if (!pci_bridge_has_region(s->bus_dev, type, domain_nr)) continue; u64 size =3D 0; if (qemu_cap) { @@ -924,22 +947,25 @@ static int pci_bios_check_devices(struct pci_bus *bus= ses) u64 tmp_size_64; switch(type) { case PCI_REGION_TYPE_IO: - tmp_size_64 =3D (pci_config_readl(bdf, qemu_cap + RES_= RESERVE_IO) | - (u64)pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_IO + 4) << 32); + tmp_size_64 =3D (pci_config_readl_dom(bdf, qemu_cap + = RES_RESERVE_IO, domain_nr) | + (u64)pci_config_readl_dom(bdf, qemu_cap + RES_= RESERVE_IO + 4, domain_nr) << 32); if (tmp_size_64 !=3D (u64)-1) { size =3D tmp_size_64; } break; case PCI_REGION_TYPE_MEM: - tmp_size =3D pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_MEM); + tmp_size =3D pci_config_readl_dom(bdf, qemu_cap + RES_= RESERVE_MEM, domain_nr); if (tmp_size !=3D (u32)-1) { size =3D tmp_size; } break; case PCI_REGION_TYPE_PREFMEM: - tmp_size =3D pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_PREF_MEM_32); - tmp_size_64 =3D (pci_config_readl(bdf, qemu_cap + RES_= RESERVE_PREF_MEM_64) | - (u64)pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_PREF_MEM_64 + 4) << 32); + tmp_size =3D pci_config_readl_dom(bdf, qemu_cap + RES_= RESERVE_PREF_MEM_32, + domain_nr); + tmp_size_64 =3D (pci_config_readl_dom(bdf, qemu_cap + = RES_RESERVE_PREF_MEM_64, + domain_nr) | + (u64)pci_config_readl_dom(bdf, qemu_cap + RE= S_RESERVE_PREF_MEM_64 + 4, + domain_nr) << 32); if (tmp_size !=3D (u32)-1 && tmp_size_64 =3D=3D (u64)-= 1) { size =3D tmp_size; } else if (tmp_size =3D=3D (u32)-1 && tmp_size_64 !=3D= (u64)-1) { @@ -970,7 +996,7 @@ static int pci_bios_check_devices(struct pci_bus *busse= s) size =3D ALIGN(sum, align); } int is64 =3D pci_bios_bridge_region_is64(&s->r[type], - s->bus_dev, type); + s->bus_dev, type, domain_nr); // entry->bar is -1 if the entry represents a bridge region struct pci_region_entry *entry =3D pci_region_create_entry( parent, s->bus_dev, -1, size, align, type, is64); @@ -1048,7 +1074,7 @@ static int pci_bios_init_root_regions_mem(struct pci_= bus *bus) #define PCI_PREF_MEMORY_SHIFT 16 =20 static void -pci_region_map_one_entry(struct pci_region_entry *entry, u64 addr) +pci_region_map_one_entry(struct pci_region_entry *entry, u64 addr, int dom= ain_nr) { if (entry->bar >=3D 0) { dprintf(1, "PCI: map device bdf=3D%pP" @@ -1063,24 +1089,24 @@ pci_region_map_one_entry(struct pci_region_entry *e= ntry, u64 addr) u16 bdf =3D entry->dev->bdf; u64 limit =3D addr + entry->size - 1; if (entry->type =3D=3D PCI_REGION_TYPE_IO) { - pci_config_writeb(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT); - pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0); - pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT); - pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0); + pci_config_writeb_dom(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT, doma= in_nr); + pci_config_writew_dom(bdf, PCI_IO_BASE_UPPER16, 0, domain_nr); + pci_config_writeb_dom(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT, do= main_nr); + pci_config_writew_dom(bdf, PCI_IO_LIMIT_UPPER16, 0, domain_nr); } if (entry->type =3D=3D PCI_REGION_TYPE_MEM) { - pci_config_writew(bdf, PCI_MEMORY_BASE, addr >> PCI_MEMORY_SHIFT); - pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT= ); + pci_config_writew_dom(bdf, PCI_MEMORY_BASE, addr >> PCI_MEMORY_SHI= FT, domain_nr); + pci_config_writew_dom(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_S= HIFT, domain_nr); } if (entry->type =3D=3D PCI_REGION_TYPE_PREFMEM) { - pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, addr >> PCI_PREF_MEMO= RY_SHIFT); - pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_ME= MORY_SHIFT); - pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, addr >> 32); - pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, limit >> 32); + pci_config_writew_dom(bdf, PCI_PREF_MEMORY_BASE, addr >> PCI_PREF_= MEMORY_SHIFT, domain_nr); + pci_config_writew_dom(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PRE= F_MEMORY_SHIFT, domain_nr); + pci_config_writel_dom(bdf, PCI_PREF_BASE_UPPER32, addr >> 32, doma= in_nr); + pci_config_writel_dom(bdf, PCI_PREF_LIMIT_UPPER32, limit >> 32, do= main_nr); } } =20 -static void pci_region_map_entries(struct pci_bus *busses, struct pci_regi= on *r) +static void pci_region_map_entries(struct pci_bus *busses, struct pci_regi= on *r, int domain_nr) { struct hlist_node *n; struct pci_region_entry *entry; @@ -1090,13 +1116,13 @@ static void pci_region_map_entries(struct pci_bus *= busses, struct pci_region *r) if (entry->bar =3D=3D -1) // Update bus base address if entry is a bridge region busses[entry->dev->secondary_bus].r[entry->type].base =3D addr; - pci_region_map_one_entry(entry, addr); + pci_region_map_one_entry(entry, addr, domain_nr); hlist_del(&entry->node); free(entry); } } =20 -static void pci_bios_map_devices(struct pci_bus *busses) +static void pci_bios_map_devices(struct pci_bus *busses, int domain_nr) { if (pci_bios_init_root_regions_io(busses)) panic("PCI: out of I/O address space\n"); @@ -1127,13 +1153,13 @@ static void pci_bios_map_devices(struct pci_bus *bu= sses) r64_pref.base =3D r64_mem.base + sum_mem; r64_pref.base =3D ALIGN(r64_pref.base, align_pref); r64_pref.base =3D ALIGN(r64_pref.base, (1LL<<30)); // 1G hugepage - pcimem64_start =3D r64_mem.base; - pcimem64_end =3D r64_pref.base + sum_pref; + pcimem64_start =3D r64_mem.base + pxb_mcfg_size; + pcimem64_end =3D r64_pref.base + sum_pref + pxb_mcfg_size; pcimem64_end =3D ALIGN(pcimem64_end, (1LL<<30)); // 1G hugepage dprintf(1, "PCI: 64: %016llx - %016llx\n", pcimem64_start, pcimem6= 4_end); =20 - pci_region_map_entries(busses, &r64_mem); - pci_region_map_entries(busses, &r64_pref); + pci_region_map_entries(busses, &r64_mem, domain_nr); + pci_region_map_entries(busses, &r64_pref, domain_nr); } else { // no bars mapped high -> drop 64bit window (see dsdt) pcimem64_start =3D 0; @@ -1143,7 +1169,7 @@ static void pci_bios_map_devices(struct pci_bus *buss= es) for (bus =3D 0; bus<=3DMaxPCIBus; bus++) { int type; for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) - pci_region_map_entries(busses, &busses[bus].r[type]); + pci_region_map_entries(busses, &busses[bus].r[type], domain_nr= ); } } =20 @@ -1164,30 +1190,35 @@ pci_setup(void) if (pci_probe_host() !=3D 0) { return; } - pci_bios_init_bus(); =20 - dprintf(1, "=3D=3D=3D PCI device probing =3D=3D=3D\n"); - pci_probe_devices(); + u8 extraroots =3D romfile_loadint("etc/extra-pci-roots", 0); + int domain_nr; + /* q35 host is in domain 0, pxb hosts in domain >=3D 1*/ + for (domain_nr =3D 0; domain_nr <=3D extraroots; ++domain_nr) { + pci_bios_init_bus(domain_nr); =20 - pcimem_start =3D RamSize; - pci_bios_init_platform(); + dprintf(1, "=3D=3D=3D PCI device probing =3D=3D=3D\n"); + pci_probe_devices(domain_nr); =20 - dprintf(1, "=3D=3D=3D PCI new allocation pass #1 =3D=3D=3D\n"); - struct pci_bus *busses =3D malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1= )); - if (!busses) { - warn_noalloc(); - return; + pcimem_start =3D RamSize; + pci_bios_init_platform(domain_nr); + + dprintf(1, "=3D=3D=3D [domain %d] PCI new allocation pass #1 =3D= =3D=3D\n", domain_nr); + struct pci_bus *busses =3D malloc_tmp(sizeof(*busses) * (MaxPCIBus= + 1)); + if (!busses) { + warn_noalloc(); + return; + } + memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1)); + if (pci_bios_check_devices(busses, domain_nr)) + return; + + dprintf(1, "=3D=3D=3D [domain %d] PCI new allocation pass #2 =3D= =3D=3D\n", domain_nr); + pci_bios_map_devices(busses, domain_nr); + + pci_bios_init_devices(domain_nr); + free(busses); } - memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1)); - if (pci_bios_check_devices(busses)) - return; - - dprintf(1, "=3D=3D=3D PCI new allocation pass #2 =3D=3D=3D\n"); - pci_bios_map_devices(busses); - - pci_bios_init_devices(); - - free(busses); =20 pci_enable_default_vga(); } diff --git a/src/hw/pci.c b/src/hw/pci.c index 9855bad..cc1b6ec 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -11,72 +11,75 @@ #include "util.h" // udelay #include "x86.h" // outl =20 -#define PORT_PCI_CMD 0x0cf8 -#define PORT_PCI_DATA 0x0cfc - -void pci_config_writel(u16 bdf, u32 addr, u32 val) +void pci_config_writel_dom(u16 bdf, u32 addr, u32 val, int domain_nr) { - outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); - outl(val, PORT_PCI_DATA); + outl(0x80000000 | (bdf << 8) | (addr & 0xfc), + domain_nr ? PORT_PXB_CMD_BASE + ((domain_nr - 1) << 3) : PORT_PCI= _CMD); + outl(val, (domain_nr ? PORT_PXB_DATA_BASE + ((domain_nr - 1) << 3) : P= ORT_PCI_DATA)); } =20 -void pci_config_writew(u16 bdf, u32 addr, u16 val) +void pci_config_writew_dom(u16 bdf, u32 addr, u16 val, int domain_nr) { - outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); - outw(val, PORT_PCI_DATA + (addr & 2)); + outl(0x80000000 | (bdf << 8) | (addr & 0xfc), + domain_nr =3D=3D 0 ? PORT_PCI_CMD : PORT_PXB_CMD_BASE + (domain_n= r << 3)); + outw(val, (domain_nr ? PORT_PXB_DATA_BASE + ((domain_nr - 1) << 3) : P= ORT_PCI_DATA) + (addr & 2)); } =20 -void pci_config_writeb(u16 bdf, u32 addr, u8 val) +void pci_config_writeb_dom(u16 bdf, u32 addr, u8 val, int domain_nr) { - outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); - outb(val, PORT_PCI_DATA + (addr & 3)); + outl(0x80000000 | (bdf << 8) | (addr & 0xfc), + domain_nr ? PORT_PXB_CMD_BASE + ((domain_nr - 1) << 3) : PORT_PCI= _CMD); + outb(val, (domain_nr ? PORT_PXB_DATA_BASE + ((domain_nr - 1) << 3) : P= ORT_PCI_DATA) + (addr & 3)); } =20 -u32 pci_config_readl(u16 bdf, u32 addr) +u32 pci_config_readl_dom(u16 bdf, u32 addr, int domain_nr) { - outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); - return inl(PORT_PCI_DATA); + outl(0x80000000 | (bdf << 8) | (addr & 0xfc), + domain_nr ? PORT_PXB_CMD_BASE + ((domain_nr - 1) << 3) : PORT_PCI= _CMD); + return inl((domain_nr ? PORT_PXB_DATA_BASE + ((domain_nr - 1) << 3) : = PORT_PCI_DATA)); } =20 -u16 pci_config_readw(u16 bdf, u32 addr) +u16 pci_config_readw_dom(u16 bdf, u32 addr, int domain_nr) { - outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); - return inw(PORT_PCI_DATA + (addr & 2)); + outl(0x80000000 | (bdf << 8) | (addr & 0xfc), + domain_nr ? PORT_PXB_CMD_BASE + ((domain_nr - 1) << 3) : PORT_PCI= _CMD); + return inw((domain_nr ? PORT_PXB_DATA_BASE + ((domain_nr - 1) << 3) : = PORT_PCI_DATA) + (addr & 2)); } =20 -u8 pci_config_readb(u16 bdf, u32 addr) +u8 pci_config_readb_dom(u16 bdf, u32 addr, int domain_nr) { - outl(0x80000000 | (bdf << 8) | (addr & 0xfc), PORT_PCI_CMD); - return inb(PORT_PCI_DATA + (addr & 3)); + outl(0x80000000 | (bdf << 8) | (addr & 0xfc), + domain_nr ? PORT_PXB_CMD_BASE + ((domain_nr - 1) << 3) : PORT_PCI= _CMD); + return inb((domain_nr ? PORT_PXB_DATA_BASE + ((domain_nr - 1) << 3) : = PORT_PCI_DATA) + (addr & 3)); } =20 void -pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on) +pci_config_maskw_dom(u16 bdf, u32 addr, u16 off, u16 on, int domain_nr) { - u16 val =3D pci_config_readw(bdf, addr); + u16 val =3D pci_config_readw_dom(bdf, addr, domain_nr); val =3D (val & ~off) | on; - pci_config_writew(bdf, addr, val); + pci_config_writew_dom(bdf, addr, val, domain_nr); } =20 -u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap) +u8 pci_find_capability_dom(u16 bdf, u8 cap_id, u8 cap, int domain_nr) { int i; - u16 status =3D pci_config_readw(bdf, PCI_STATUS); + u16 status =3D pci_config_readw_dom(bdf, PCI_STATUS, domain_nr); =20 if (!(status & PCI_STATUS_CAP_LIST)) return 0; =20 if (cap =3D=3D 0) { /* find first */ - cap =3D pci_config_readb(bdf, PCI_CAPABILITY_LIST); + cap =3D pci_config_readb_dom(bdf, PCI_CAPABILITY_LIST, domain_nr); } else { /* find next */ - cap =3D pci_config_readb(bdf, cap + PCI_CAP_LIST_NEXT); + cap =3D pci_config_readb_dom(bdf, cap + PCI_CAP_LIST_NEXT, domain_= nr); } for (i =3D 0; cap && i <=3D 0xff; i++) { - if (pci_config_readb(bdf, cap + PCI_CAP_LIST_ID) =3D=3D cap_id) + if (pci_config_readb_dom(bdf, cap + PCI_CAP_LIST_ID, domain_nr) = =3D=3D cap_id) return cap; - cap =3D pci_config_readb(bdf, cap + PCI_CAP_LIST_NEXT); + cap =3D pci_config_readb_dom(bdf, cap + PCI_CAP_LIST_NEXT, domain_= nr); } =20 return 0; @@ -84,10 +87,10 @@ u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap) =20 // Helper function for foreachbdf() macro - return next device int -pci_next(int bdf, int bus) +pci_next_dom(int bdf, int bus, int domain_nr) { if (pci_bdf_to_fn(bdf) =3D=3D 0 - && (pci_config_readb(bdf, PCI_HEADER_TYPE) & 0x80) =3D=3D 0) + && (pci_config_readb_dom(bdf, PCI_HEADER_TYPE, domain_nr) & 0x80) = =3D=3D 0) // Last found device wasn't a multi-function device - skip to // the next device. bdf +=3D 8; @@ -98,7 +101,7 @@ pci_next(int bdf, int bus) if (pci_bdf_to_bus(bdf) !=3D bus) return -1; =20 - u16 v =3D pci_config_readw(bdf, PCI_VENDOR_ID); + u16 v =3D pci_config_readw_dom(bdf, PCI_VENDOR_ID, domain_nr); if (v !=3D 0x0000 && v !=3D 0xffff) // Device is present. return bdf; diff --git a/src/hw/pci.h b/src/hw/pci.h index 2e30e28..4381563 100644 --- a/src/hw/pci.h +++ b/src/hw/pci.h @@ -3,7 +3,11 @@ =20 #include "types.h" // u32 =20 +#define PORT_PCI_CMD 0x0cf8 #define PORT_PCI_REBOOT 0x0cf9 +#define PORT_PCI_DATA 0x0cfc +#define PORT_PXB_CMD_BASE 0x1000 +#define PORT_PXB_DATA_BASE 0x1004 =20 static inline u8 pci_bdf_to_bus(u16 bdf) { return bdf >> 8; @@ -27,20 +31,34 @@ static inline u16 pci_bus_devfn_to_bdf(int bus, u16 dev= fn) { return (bus << 8) | devfn; } =20 -#define foreachbdf(BDF, BUS) \ - for (BDF=3Dpci_next(pci_bus_devfn_to_bdf((BUS), 0)-1, (BUS)) \ +/* for compatibility */ +#define foreachbdf(BDF, BUS) foreachbdf_dom(BDF, BUS, 0) + +#define foreachbdf_dom(BDF, BUS, DOMAIN) = \ + for (BDF=3Dpci_next_dom(pci_bus_devfn_to_bdf((BUS), 0)-1, (BUS), (DOMA= IN)) \ ; BDF >=3D 0 \ - ; BDF=3Dpci_next(BDF, (BUS))) + ; BDF=3Dpci_next_dom(BDF, (BUS), (DOMAIN))) =20 -void pci_config_writel(u16 bdf, u32 addr, u32 val); -void pci_config_writew(u16 bdf, u32 addr, u16 val); -void pci_config_writeb(u16 bdf, u32 addr, u8 val); -u32 pci_config_readl(u16 bdf, u32 addr); -u16 pci_config_readw(u16 bdf, u32 addr); -u8 pci_config_readb(u16 bdf, u32 addr); -void pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on); -u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap); -int pci_next(int bdf, int bus); +#define pci_config_maskw(BDF, ADDR, OFF, ON) pci_config_maskw_dom((BDF), (= ADDR), (OFF), (ON), 0) +#define pci_find_capability(BDF, CAP_ID, CAP) pci_find_capability_dom((BDF= ), (CAP_ID), (CAP), 0) +#define pci_next(BDF, BUS) pci_next_dom((BDF), (BUS), 0) + +#define pci_config_writel(BDF, ADDR, VAL) pci_config_writel_dom((BDF), (AD= DR), (VAL), 0) +#define pci_config_writew(BDF, ADDR, VAL) pci_config_writew_dom((BDF), (AD= DR), (VAL), 0) +#define pci_config_writeb(BDF, ADDR, VAL) pci_config_writeb_dom((BDF), (AD= DR), (VAL), 0) +#define pci_config_readl(BDF, ADDR) pci_config_readl_dom((BDF), (ADDR), 0) +#define pci_config_readw(BDF, ADDR) pci_config_readw_dom((BDF), (ADDR), 0) +#define pci_config_readb(BDF, ADDR) pci_config_readb_dom((BDF), (ADDR), 0) + +void pci_config_writel_dom(u16 bdf, u32 addr, u32 val, int domain_nr); +void pci_config_writew_dom(u16 bdf, u32 addr, u16 val, int domain_nr); +void pci_config_writeb_dom(u16 bdf, u32 addr, u8 val, int domain_nr); +u32 pci_config_readl_dom(u16 bdf, u32 addr, int domain_nr); +u16 pci_config_readw_dom(u16 bdf, u32 addr, int domain_nr); +u8 pci_config_readb_dom(u16 bdf, u32 addr, int domain_nr); +void pci_config_maskw_dom(u16 bdf, u32 addr, u16 off, u16 on, int domain_n= r); +u8 pci_find_capability_dom(u16 bdf, u8 cap_id, u8 cap, int domain_nr); +int pci_next_dom(int bdf, int bus, int domain_nr); int pci_probe_host(void); void pci_reboot(void); =20 diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 35096ea..1d4ddf6 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2263,9 +2263,10 @@ #define PCI_DEVICE_ID_KORENIX_JETCARDF0 0x1600 #define PCI_DEVICE_ID_KORENIX_JETCARDF1 0x16ff =20 -#define PCI_VENDOR_ID_REDHAT 0x1b36 -#define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C -#define PCI_DEVICE_ID_REDHAT_PXB_HOST 0x000B +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_DEVICE_ID_REDHAT_PXB_HOST 0x000B +#define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C +#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000E =20 #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 diff --git a/src/hw/pcidevice.c b/src/hw/pcidevice.c index 8853cf7..ec21ec1 100644 --- a/src/hw/pcidevice.c +++ b/src/hw/pcidevice.c @@ -15,10 +15,11 @@ =20 struct hlist_head PCIDevices VARVERIFY32INIT; int MaxPCIBus VARFSEG; +int PXBHosts VARFSEG; =20 // Find all PCI devices and populate PCIDevices linked list. void -pci_probe_devices(void) +pci_probe_devices(int domain_nr) { dprintf(3, "PCI probe\n"); struct pci_device *busdevs[256]; @@ -29,7 +30,7 @@ pci_probe_devices(void) while (bus < 0xff && (bus < MaxPCIBus || rootbuses < extraroots)) { bus++; int bdf; - foreachbdf(bdf, bus) { + foreachbdf_dom(bdf, bus, domain_nr) { // Create new pci_device struct and add to list. struct pci_device *dev =3D malloc_tmp(sizeof(*dev)); if (!dev) { @@ -56,6 +57,7 @@ pci_probe_devices(void) } =20 // Populate pci_device info. + dev->domain_nr =3D domain_nr; dev->bdf =3D bdf; dev->parent =3D parent; dev->rootbus =3D rootbus; @@ -69,7 +71,7 @@ pci_probe_devices(void) dev->header_type =3D pci_config_readb(bdf, PCI_HEADER_TYPE); u8 v =3D dev->header_type & 0x7f; if (v =3D=3D PCI_HEADER_TYPE_BRIDGE || v =3D=3D PCI_HEADER_TYP= E_CARDBUS) { - u8 secbus =3D pci_config_readb(bdf, PCI_SECONDARY_BUS); + u8 secbus =3D pci_config_readb_dom(bdf, PCI_SECONDARY_BUS,= domain_nr); dev->secondary_bus =3D secbus; if (secbus > bus && !busdevs[secbus]) busdevs[secbus] =3D dev; diff --git a/src/hw/pcidevice.h b/src/hw/pcidevice.h index 225d545..951e005 100644 --- a/src/hw/pcidevice.h +++ b/src/hw/pcidevice.h @@ -5,6 +5,7 @@ #include "list.h" // hlist_node =20 struct pci_device { + u32 domain_nr; u16 bdf; u8 rootbus; struct hlist_node node; @@ -22,6 +23,7 @@ struct pci_device { }; extern struct hlist_head PCIDevices; extern int MaxPCIBus; +extern int PXBHosts; =20 static inline u32 pci_classprog(struct pci_device *pci) { return (pci->class << 8) | pci->prog_if; @@ -62,7 +64,7 @@ struct pci_device_id { .vendid =3D 0, \ } =20 -void pci_probe_devices(void); +void pci_probe_devices(int domain_nr); struct pci_device *pci_find_device(u16 vendid, u16 devid); struct pci_device *pci_find_class(u16 classid); int pci_init_device(const struct pci_device_id *ids --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sat Apr 20 05:23:09 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; 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[45.78.72.26]) by smtp.gmail.com with ESMTPSA id j27-v6sm11515584pfj.91.2018.08.08.22.44.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Aug 2018 22:44:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Pyy++2mASS+nnWVRXlRl24QUcKF8R93spibLB8eUdlg=; b=pr77p7Xet0EjzhSoS99DC0cPZzydxRWJ65JQYZOb6SC/4ex+hcdPWJ2s9HUs+O8j6n MOjPl9MBD5AzMUCBobzqUIw6pGp+xY17w8gPZT7dwzSdnhcn1WGfptgKPrrqp4tTqqyK tsShPeAqZqdCWvDCaJkTu4ZHJzSQpkgMU9yuxbrj6DVP3VD8z5/hY9dsn5y7W2B6ACiV QKAcm6TCVcAcL+HpoHgBFmTZS2f/f1KtGHEzA21IJlSFat9JOKPdSr0eEqQGy/tOFs79 o32NTyARWVacBGQf10q5TjxMo6xWV5MuOqTyka19J9si8WhNc3N6LWoBj8EoJU7FApe2 0nDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Pyy++2mASS+nnWVRXlRl24QUcKF8R93spibLB8eUdlg=; b=OuFlnKn0wMd4fYDbGdn3wSGqmOEun9U5PeZ3bVZD4NZJND+zyx1vRjHFoB1cJN58kw 1Yt+quRA5suQE5EJs94v6ihZM8Uo52QqQxt488FD4RH8BJPRNlarB8C6o8cpUkqR2SJD RbTOiAGWtCzRzSrDfqakAY5avTg4EtHU8zh+DBUPqT5hlwxSvF7aaKMarcHnlfKrPPEO TfSyQIh+zRgtgK/43zU8VWVC2MRYQxm7ugU43pPbUjiKqp4BuR5lkyI+UKtURs/tdXej payHSZBhfiSayUlCtkeJ55hcOxJpa9TV9vYrveHQUQHDPNT/1Sye/8xVw2qRabB+9AoV y+Iw== X-Gm-Message-State: AOUpUlHret9UF1hti5wtZEYfDcEpn5XMiNk6DqB7K6mC3n1EJ9dtMs7Y 3PXeVIQ4Jm/pHQy4TcCkg/zZO+XszkE= X-Google-Smtp-Source: AA+uWPy/pqRegc/hvIKpWMnYfAJGsmAAjk54WuDAFj+rtyP6uJ1qrXm86agwVgW3Bb/iREV/brjEkA== X-Received: by 2002:a17:902:143:: with SMTP id 61-v6mr689102plb.171.1533793453592; Wed, 08 Aug 2018 22:44:13 -0700 (PDT) From: Zihan Yang To: seabios@seabios.org Date: Thu, 9 Aug 2018 13:43:54 +0800 Message-Id: <1533793434-7614-4-git-send-email-whois.zihan.yang@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533793434-7614-1-git-send-email-whois.zihan.yang@gmail.com> References: <1533793434-7614-1-git-send-email-whois.zihan.yang@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [RFC v2 3/3] pci: filter undesired domain when traversing pci X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zihan Yang MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Since pci devices could reside in different domains now, we should judge the domain of pci devices when traversing them. Original devices still use domain 0 for compatibility Signed-off-by: Zihan Yang --- src/fw/mptable.c | 1 + src/fw/pciinit.c | 10 ++++------ src/hw/ahci.c | 1 + src/hw/ata.c | 1 + src/hw/esp-scsi.c | 1 + src/hw/lsi-scsi.c | 1 + src/hw/megasas.c | 1 + src/hw/mpt-scsi.c | 1 + src/hw/nvme.c | 1 + src/hw/pcidevice.c | 3 +++ src/hw/pcidevice.h | 4 ++++ src/hw/pvscsi.c | 1 + src/hw/sdcard.c | 1 + src/hw/usb-ehci.c | 1 + src/hw/usb-ohci.c | 1 + src/hw/usb-uhci.c | 1 + src/hw/usb-xhci.c | 1 + src/hw/virtio-blk.c | 1 + src/hw/virtio-scsi.c | 1 + src/optionroms.c | 3 +++ 20 files changed, 30 insertions(+), 6 deletions(-) diff --git a/src/fw/mptable.c b/src/fw/mptable.c index 47385cc..3989cb6 100644 --- a/src/fw/mptable.c +++ b/src/fw/mptable.c @@ -110,6 +110,7 @@ mptable_setup(void) =20 struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); u16 bdf =3D pci->bdf; if (pci_bdf_to_bus(bdf) !=3D 0) break; diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index fcdcd38..834540f 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -427,8 +427,7 @@ static void pci_bios_init_devices(int domain_nr) { struct pci_device *pci; foreachpci(pci) { - if (pci->domain_nr !=3D domain_nr) - continue; + filter_domain(pci, domain_nr); pci_bios_init_device(pci); } } @@ -438,6 +437,7 @@ static void pci_enable_default_vga(void) struct pci_device *pci; =20 foreachpci(pci) { + filter_domain(pci, 0); if (is_pci_vga(pci)) { dprintf(1, "PCI: Using %pP for primary VGA\n", pci); return; @@ -545,8 +545,7 @@ static void pci_bios_init_platform(int domain_nr) { struct pci_device *pci; foreachpci(pci) { - if (pci->domain_nr !=3D domain_nr) - continue; + filter_domain(pci, domain_nr); pci_init_device(pci_platform_tbl, pci, NULL); } } @@ -884,8 +883,7 @@ static int pci_bios_check_devices(struct pci_bus *busse= s, int domain_nr) // Calculate resources needed for regular (non-bus) devices. struct pci_device *pci; foreachpci(pci) { - if (pci->domain_nr !=3D domain_nr) - continue; + filter_domain(pci, domain_nr); if (pci->class =3D=3D PCI_CLASS_BRIDGE_PCI) busses[pci->secondary_bus].bus_dev =3D pci; =20 diff --git a/src/hw/ahci.c b/src/hw/ahci.c index 1746e7a..f825992 100644 --- a/src/hw/ahci.c +++ b/src/hw/ahci.c @@ -677,6 +677,7 @@ ahci_scan(void) // Scan PCI bus for ATA adapters struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->class !=3D PCI_CLASS_STORAGE_SATA) continue; if (pci->prog_if !=3D 1 /* AHCI rev 1 */) diff --git a/src/hw/ata.c b/src/hw/ata.c index b6e073c..2273326 100644 --- a/src/hw/ata.c +++ b/src/hw/ata.c @@ -1024,6 +1024,7 @@ ata_scan(void) // Scan PCI bus for ATA adapters struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); pci_init_device(pci_ata_tbl, pci, NULL); } } diff --git a/src/hw/esp-scsi.c b/src/hw/esp-scsi.c index ffd86d0..17436d5 100644 --- a/src/hw/esp-scsi.c +++ b/src/hw/esp-scsi.c @@ -233,6 +233,7 @@ esp_scsi_setup(void) =20 struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->vendor !=3D PCI_VENDOR_ID_AMD || pci->device !=3D PCI_DEVICE_ID_AMD_SCSI) continue; diff --git a/src/hw/lsi-scsi.c b/src/hw/lsi-scsi.c index d5fc3e4..5748d1f 100644 --- a/src/hw/lsi-scsi.c +++ b/src/hw/lsi-scsi.c @@ -213,6 +213,7 @@ lsi_scsi_setup(void) =20 struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->vendor !=3D PCI_VENDOR_ID_LSI_LOGIC || pci->device !=3D PCI_DEVICE_ID_LSI_53C895A) continue; diff --git a/src/hw/megasas.c b/src/hw/megasas.c index d267580..1d84771 100644 --- a/src/hw/megasas.c +++ b/src/hw/megasas.c @@ -386,6 +386,7 @@ megasas_setup(void) =20 struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->vendor !=3D PCI_VENDOR_ID_LSI_LOGIC && pci->vendor !=3D PCI_VENDOR_ID_DELL) continue; diff --git a/src/hw/mpt-scsi.c b/src/hw/mpt-scsi.c index 1faede6..e89316b 100644 --- a/src/hw/mpt-scsi.c +++ b/src/hw/mpt-scsi.c @@ -310,6 +310,7 @@ mpt_scsi_setup(void) =20 struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->vendor =3D=3D PCI_VENDOR_ID_LSI_LOGIC && (pci->device =3D=3D PCI_DEVICE_ID_LSI_53C1030 || pci->device =3D=3D PCI_DEVICE_ID_LSI_SAS1068 diff --git a/src/hw/nvme.c b/src/hw/nvme.c index e6d739d..d7b5183 100644 --- a/src/hw/nvme.c +++ b/src/hw/nvme.c @@ -633,6 +633,7 @@ nvme_scan(void) struct pci_device *pci; =20 foreachpci(pci) { + filter_domain(pci, 0); if (pci->class !=3D PCI_CLASS_STORAGE_NVME) continue; if (pci->prog_if !=3D 2 /* as of NVM 1.0e */) { diff --git a/src/hw/pcidevice.c b/src/hw/pcidevice.c index ec21ec1..44dc05a 100644 --- a/src/hw/pcidevice.c +++ b/src/hw/pcidevice.c @@ -91,6 +91,7 @@ pci_find_device(u16 vendid, u16 devid) { struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->vendor =3D=3D vendid && pci->device =3D=3D devid) return pci; } @@ -103,6 +104,7 @@ pci_find_class(u16 classid) { struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->class =3D=3D classid) return pci; } @@ -130,6 +132,7 @@ pci_find_init_device(const struct pci_device_id *ids, v= oid *arg) { struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci_init_device(ids, pci, arg) =3D=3D 0) return pci; } diff --git a/src/hw/pcidevice.h b/src/hw/pcidevice.h index 951e005..4518e77 100644 --- a/src/hw/pcidevice.h +++ b/src/hw/pcidevice.h @@ -32,6 +32,10 @@ static inline u32 pci_classprog(struct pci_device *pci) { #define foreachpci(PCI) \ hlist_for_each_entry(PCI, &PCIDevices, node) =20 +#define filter_domain(PCI, DOMAIN) \ + if ((PCI)->domain_nr !=3D (DOMAIN)) \ + continue; + #define PCI_ANY_ID (~0) struct pci_device_id { u32 vendid; diff --git a/src/hw/pvscsi.c b/src/hw/pvscsi.c index d62d0a0..d0f6dac 100644 --- a/src/hw/pvscsi.c +++ b/src/hw/pvscsi.c @@ -325,6 +325,7 @@ pvscsi_setup(void) =20 struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->vendor !=3D PCI_VENDOR_ID_VMWARE || pci->device !=3D PCI_DEVICE_ID_VMWARE_PVSCSI) continue; diff --git a/src/hw/sdcard.c b/src/hw/sdcard.c index 6410340..f3782f2 100644 --- a/src/hw/sdcard.c +++ b/src/hw/sdcard.c @@ -564,6 +564,7 @@ sdcard_setup(void) =20 struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->class !=3D PCI_CLASS_SYSTEM_SDHCI || pci->prog_if >=3D 2) // Not an SDHCI controller following SDHCI spec continue; diff --git a/src/hw/usb-ehci.c b/src/hw/usb-ehci.c index 7eca55b..60b73b2 100644 --- a/src/hw/usb-ehci.c +++ b/src/hw/usb-ehci.c @@ -331,6 +331,7 @@ ehci_setup(void) return; struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci_classprog(pci) =3D=3D PCI_CLASS_SERIAL_USB_EHCI) ehci_controller_setup(pci); } diff --git a/src/hw/usb-ohci.c b/src/hw/usb-ohci.c index 90f60e6..c25745f 100644 --- a/src/hw/usb-ohci.c +++ b/src/hw/usb-ohci.c @@ -302,6 +302,7 @@ ohci_setup(void) return; struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci_classprog(pci) =3D=3D PCI_CLASS_SERIAL_USB_OHCI) ohci_controller_setup(pci); } diff --git a/src/hw/usb-uhci.c b/src/hw/usb-uhci.c index 075ed02..f92b417 100644 --- a/src/hw/usb-uhci.c +++ b/src/hw/usb-uhci.c @@ -275,6 +275,7 @@ uhci_setup(void) return; struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci_classprog(pci) =3D=3D PCI_CLASS_SERIAL_USB_UHCI) uhci_controller_setup(pci); } diff --git a/src/hw/usb-xhci.c b/src/hw/usb-xhci.c index 08d1e32..9293720 100644 --- a/src/hw/usb-xhci.c +++ b/src/hw/usb-xhci.c @@ -631,6 +631,7 @@ xhci_setup(void) return; struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci_classprog(pci) =3D=3D PCI_CLASS_SERIAL_USB_XHCI) xhci_controller_setup(pci); } diff --git a/src/hw/virtio-blk.c b/src/hw/virtio-blk.c index 88d7e54..2a98303 100644 --- a/src/hw/virtio-blk.c +++ b/src/hw/virtio-blk.c @@ -202,6 +202,7 @@ virtio_blk_setup(void) =20 struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->vendor !=3D PCI_VENDOR_ID_REDHAT_QUMRANET || (pci->device !=3D PCI_DEVICE_ID_VIRTIO_BLK_09 && pci->device !=3D PCI_DEVICE_ID_VIRTIO_BLK_10)) diff --git a/src/hw/virtio-scsi.c b/src/hw/virtio-scsi.c index a87cad8..b77680e 100644 --- a/src/hw/virtio-scsi.c +++ b/src/hw/virtio-scsi.c @@ -211,6 +211,7 @@ virtio_scsi_setup(void) =20 struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->vendor !=3D PCI_VENDOR_ID_REDHAT_QUMRANET || (pci->device !=3D PCI_DEVICE_ID_VIRTIO_SCSI_09 && pci->device !=3D PCI_DEVICE_ID_VIRTIO_SCSI_10)) diff --git a/src/optionroms.c b/src/optionroms.c index fc992f6..527b7cb 100644 --- a/src/optionroms.c +++ b/src/optionroms.c @@ -350,6 +350,7 @@ optionrom_setup(void) // Find and deploy PCI roms. struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (pci->class =3D=3D PCI_CLASS_DISPLAY_VGA || pci->class =3D=3D PCI_CLASS_DISPLAY_OTHER || pci->have_driver) @@ -409,6 +410,7 @@ static void try_setup_display_other(void) dprintf(1, "No VGA found, scan for other display\n"); =20 foreachpci(pci) { + filter_domain(pci, 0); if (pci->class !=3D PCI_CLASS_DISPLAY_OTHER) continue; struct rom_header *rom =3D map_pcirom(pci); @@ -445,6 +447,7 @@ vgarom_setup(void) // Find and deploy PCI VGA rom. struct pci_device *pci; foreachpci(pci) { + filter_domain(pci, 0); if (!is_pci_vga(pci)) continue; vgahook_setup(pci); --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios