Re: [PATCH v1] hw/pci-host/xilinx-pcie: Set explicit bus name for Root Port
Hi,
 Gentle ping for this patch.
 The motivation for this change is to make the secondary bus behind the
 Xilinx PCIe root bridge addressable from the QEMU command line.
 Without an explicit bus name, it is difficult to attach another PCIe
 device or bridge below the XDMA root bridge using the -device bus=
 property. With this patch, the root bridge creates its secondary bus
 with a stable name, so command lines such as the following become
 possible:
 -device xio3130-downstream,id=switch1,bus=xdma-pcie
 This is useful when building PCIe topologies behind the Xilinx XDMA PCIe
 host bridge, for example when testing PCIe switch/downstream-port setups
 or IOMMU requester-id behavior.
 Could someone take a look when convenient?
 Thanks,
 Chengbo
------------------------------------------------------------------
title：[PATCH v1] hw/pci-host/xilinx-pcie: Set explicit bus name for Root Port
Assign the name "xdma-pcie" to the PCI bridge bus in xilinx_pcie_root_realize().
This makes it easier to identify the Xilinx PCIe host bridge in QEMU monitor
commands (e.g., 'info qtree', 'info mtree') and debugging logs, distinguishing
it from generic pci-bridge instances.
Signed-off-by: Chengbo Gao <gaochengbo@bosc.ac.cn>
---
 hw/pci-host/xilinx-pcie.c | 2 ++
 1 file changed, 2 insertions(+)
diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c
index 40f625b61d..2949c5385e 100644
--- a/hw/pci-host/xilinx-pcie.c
+++ b/hw/pci-host/xilinx-pcie.c
@@ -271,7 +271,9 @@ static void xilinx_pcie_root_realize(PCIDevice *pci_dev, Error **errp)
 {
 BusState *bus = qdev_get_parent_bus(DEVICE(pci_dev));
 XilinxPCIEHost *s = XILINX_PCIE_HOST(bus->parent);
+ PCIBridge *br = PCI_BRIDGE(pci_dev);
+ br->bus_name = "xdma-pcie";
 pci_set_word(pci_dev->config + PCI_COMMAND,
 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 pci_set_word(pci_dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16);
-- 
2.43.0

On Fri, 15 May 2026 at 09:52, 高承博 <gaochengbo@bosc.ac.cn> wrote:
>
> Re: [PATCH v1] hw/pci-host/xilinx-pcie: Set explicit bus name for Root Port
> Hi,
>
>   Gentle ping for this patch.
>
>   The motivation for this change is to make the secondary bus behind the
>   Xilinx PCIe root bridge addressable from the QEMU command line.
>
>   Without an explicit bus name, it is difficult to attach another PCIe
>   device or bridge below the XDMA root bridge using the -device bus=
>   property.  With this patch, the root bridge creates its secondary bus
>   with a stable name, so command lines such as the following become
>   possible:
>
>     -device xio3130-downstream,id=switch1,bus=xdma-pcie
>
>   This is useful when building PCIe topologies behind the Xilinx XDMA PCIe
>   host bridge, for example when testing PCIe switch/downstream-port setups
>   or IOMMU requester-id behavior.
>
>   Could someone take a look when convenient?
>
>   Thanks,
>   Chengbo

I'm not a PCI expert, but nowhere else in QEMU seems to reach in
to the PCIBridge private data bus_name field and set it like this,
which makes me think this isn't the right way to do this.

There is a pci_bridge_map_irq() function which lets you set
the bus_name, but we use that in only two devices, so I'm not
sure about that either.

thanks
-- PMM