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boundary="----=ALIBOUNDARY_2845_7f7a3c006700_6a06dea9_5b9e8" Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=115.124.28.51; envelope-from=gaochengbo@bosc.ac.cn; helo=out28-51.mail.aliyun.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: =?UTF-8?B?6auY5om/5Y2a?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @bosc.ac.cn) X-ZM-MESSAGEID: 1778835157160158500 ------=ALIBOUNDARY_2845_7f7a3c006700_6a06dea9_5b9e8 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Re: [PATCH v1] hw/pci-host/xilinx-pcie: Set explicit bus name for Root Port Hi, Gentle ping for this patch. The motivation for this change is to make the secondary bus behind the Xilinx PCIe root bridge addressable from the QEMU command line. Without an explicit bus name, it is difficult to attach another PCIe device or bridge below the XDMA root bridge using the -device bus=3D property. With this patch, the root bridge creates its secondary bus with a stable name, so command lines such as the following become possible: -device xio3130-downstream,id=3Dswitch1,bus=3Dxdma-pcie This is useful when building PCIe topologies behind the Xilinx XDMA PCIe host bridge, for example when testing PCIe switch/downstream-port setups or IOMMU requester-id behavior. Could someone take a look when convenient? Thanks, Chengbo ------------------------------------------------------------------ title=EF=BC=9A[PATCH v1] hw/pci-host/xilinx-pcie: Set explicit bus name for= Root Port Assign the name "xdma-pcie" to the PCI bridge bus in xilinx_pcie_root_reali= ze(). This makes it easier to identify the Xilinx PCIe host bridge in QEMU monitor commands (e.g., 'info qtree', 'info mtree') and debugging logs, distinguish= ing it from generic pci-bridge instances. Signed-off-by: Chengbo Gao --- hw/pci-host/xilinx-pcie.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c index 40f625b61d..2949c5385e 100644 --- a/hw/pci-host/xilinx-pcie.c +++ b/hw/pci-host/xilinx-pcie.c @@ -271,7 +271,9 @@ static void xilinx_pcie_root_realize(PCIDevice *pci_dev= , Error **errp) { BusState *bus =3D qdev_get_parent_bus(DEVICE(pci_dev)); XilinxPCIEHost *s =3D XILINX_PCIE_HOST(bus->parent); + PCIBridge *br =3D PCI_BRIDGE(pci_dev); + br->bus_name =3D "xdma-pcie"; pci_set_word(pci_dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); pci_set_word(pci_dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16); --=20 2.43.0 ------=ALIBOUNDARY_2845_7f7a3c006700_6a06dea9_5b9e8 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: base64 PGRpdiBjbGFzcz0iX19hbGl5dW5fZW1haWxfYm9keV9ibG9jayI+PGRpdiAgc3R5bGU9ImZvbnQt ZmFtaWx5OiBUYWhvbWEsIEFyaWFsLCBTVEhlaXRpU0MtTGlnaHQsIFNpbVN1biI+PGRpdiAgc3R5 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