Fix transfer size register decrement

[PATCH v2 0/1] Fix transfer size register decrement

Tao Ding posted 1 patch 1 week, 5 days ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1774282897.git.dingtao0430@163.com

Maintainers: Peter Maydell <peter.maydell@linaro.org>

hw/dma/pl080.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)

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[PATCH v2 0/1] Fix transfer size register decrement

Posted by Tao Ding 1 week, 5 days ago

When source and destination widths are different, the transfer size
register was not being decremented correctly, causing data corruption.

Compared to the previous version(PATCH v1 2/3), simplified the code and
the judgment of constraint relationships between size, swidth, and dwidth has been added.

Tao Ding (1):
  Fix transfer size register decrement in pl080

 hw/dma/pl080.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)


base-commit: 8e711856d7639cbffa51405f2cc2366e3d9e3a23
-- 
2.43.0