Accept action=debug-mode in itrigger tdata1 when Sdext is enabled
and reject unsupported action encodings explicitly.

This extends the instruction-count trigger path to the same
debug-entry mode used by other trigger types and keeps invalid
encodings from being silently accepted.

Signed-off-by: Chao Liu <chao.liu.zevorn@gmail.com>
---
 target/riscv/debug.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index f3d6eaeb1e..4dbcf289f2 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -916,15 +916,27 @@ static target_ulong itrigger_validate(CPURISCVState *env,
                                       target_ulong ctrl)
 {
     target_ulong val;
+    uint32_t action;
 
     /* validate the generic part first */
     val = tdata1_validate(env, ctrl, TRIGGER_TYPE_INST_CNT);
 
-    /* validate unimplemented (always zero) bits */
-    warn_always_zero_bit(ctrl, ITRIGGER_ACTION, "action");
     warn_always_zero_bit(ctrl, ITRIGGER_HIT, "hit");
     warn_always_zero_bit(ctrl, ITRIGGER_PENDING, "pending");
 
+    action = ctrl & ITRIGGER_ACTION;
+    if (action == DBG_ACTION_DBG_MODE) {
+        if (env_archcpu(env)->cfg.ext_sdext) {
+            val |= action;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "trigger action=debug mode requires Sdext\n");
+        }
+    } else if (action != DBG_ACTION_BP) {
+        qemu_log_mask(LOG_UNIMP, "trigger action: %u is not supported\n",
+                      action);
+    }
+
     /* keep the mode and attribute bits */
     val |= ctrl & (ITRIGGER_VU | ITRIGGER_VS | ITRIGGER_U | ITRIGGER_S |
                    ITRIGGER_M | ITRIGGER_COUNT);
-- 
2.53.0