[v1] riscv: add initial sdext support

[RFC PATCH v1 0/8] riscv: add initial sdext support

Chao Liu posted 8 patches 2 weeks, 6 days ago

Diff against v2 v3 v4 v5
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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1768622881.git.chao.liu.zevorn@gmail.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

include/exec/translation-block.h              |   3 +-
target/riscv/cpu.c                            |  23 ++-
target/riscv/cpu.h                            |  10 ++
target/riscv/cpu_bits.h                       |  33 ++++
target/riscv/cpu_cfg_fields.h.inc             |   2 +
target/riscv/cpu_helper.c                     |  93 ++++++++++++
target/riscv/csr.c                            | 142 +++++++++++++++++-
target/riscv/debug.c                          |  58 ++++++-
target/riscv/helper.h                         |   3 +
target/riscv/insn32.decode                    |   1 +
.../riscv/insn_trans/trans_privileged.c.inc   |  24 ++-
target/riscv/machine.c                        |  12 +-
target/riscv/op_helper.c                      |  72 +++++++++
target/riscv/tcg/tcg-cpu.c                    |  34 +++--
target/riscv/translate.c                      |  16 +-
tests/data/acpi/riscv64/virt/RHCT             | Bin 416 -> 422 bytes
16 files changed, 492 insertions(+), 34 deletions(-)

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[RFC PATCH v1 0/8] riscv: add initial sdext support

Posted by Chao Liu 2 weeks, 6 days ago

Hi Daniel,

This RFC series adds a minimal CPU-side model for Sdext and Sdtrig in
RISC-V QEMU. It is based on RISC-V Debug Specification 1.0:
https://github.com/riscv/riscv-debug-spec/releases/tag/1.0

It introduces the sdext/sdtrig config bits, DCSR/DPC/DSCRATCH state,
Debug Mode enter/leave helpers, DRET, EBREAK entry, single-step, and
trigger action=debug mode.

To reduce review load, this series focuses on the Sdext features first.
The Debug Module (DM) and related flows will follow in a later series.

Current status:
- Debug Mode entry/exit updates DCSR/DPC and restores execution via DRET.
- EBREAK honors DCSR ebreak bits and enters Debug Mode when enabled.
- Single-step uses DCSR.STEP with a TB flag and a helper at TB exit.
  It references Max Chou's patch "target/riscv: Use the tb->cs_bqse as
  the extend tb flags.":
  https://lore.kernel.org/qemu-devel/20260108132631.9429-6-max.chou@sifive.com/
- Sdtrig supports action=debug mode for mcontrol/mcontrol6 and reports
  inst-count triggers in tinfo.

Differences vs Debug Spec (known gaps):
- No Debug Module (no DMI, dmcontrol/dmstatus, haltreq/resumereq).
- No debug ROM, program buffer, abstract commands, or SBA.
- Resume is modeled by leaving Debug Mode at cpu_exec_enter.
- Step/exception ordering is simplified: if the stepped instruction
  traps, the normal exception is taken and Debug Mode is not forced.
- Several DCSR fields are not fully modeled (stopcount/stoptime, etc).

Roadmap (next stage, DM focus):
1) Add a DM core with DMI access and hart state tracking.
2) Implement halt/resume handshake and move Debug Mode transitions
   under DM control.
3) Add debug ROM, program buffer, and abstract commands for GPR/CSR
   and memory access.
4) Add SBA if required by tooling.
5) Tighten ordering rules for step/exception/trigger priorities.

Thanks,
Chao


Chao Liu (8):
  riscv: split sdext and sdtrig config bits
  riscv: add sdext debug CSRs state
  riscv: add sdext Debug Mode helpers
  riscv: add dret instruction
  riscv: add sdext enter Debug Mode on ebreak
  riscv: add sdext single-step support
  riscv: add sdtrig trigger action=debug mode
  tests: update riscv64 virt RHCT

 include/exec/translation-block.h              |   3 +-
 target/riscv/cpu.c                            |  23 ++-
 target/riscv/cpu.h                            |  10 ++
 target/riscv/cpu_bits.h                       |  33 ++++
 target/riscv/cpu_cfg_fields.h.inc             |   2 +
 target/riscv/cpu_helper.c                     |  93 ++++++++++++
 target/riscv/csr.c                            | 142 +++++++++++++++++-
 target/riscv/debug.c                          |  58 ++++++-
 target/riscv/helper.h                         |   3 +
 target/riscv/insn32.decode                    |   1 +
 .../riscv/insn_trans/trans_privileged.c.inc   |  24 ++-
 target/riscv/machine.c                        |  12 +-
 target/riscv/op_helper.c                      |  72 +++++++++
 target/riscv/tcg/tcg-cpu.c                    |  34 +++--
 target/riscv/translate.c                      |  16 +-
 tests/data/acpi/riscv64/virt/RHCT             | Bin 416 -> 422 bytes
 16 files changed, 492 insertions(+), 34 deletions(-)

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2.52.0