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Fri, 16 Jan 2026 20:27:40 -0800 (PST) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wangjingwei@iscas.ac.cn, Chao Liu Subject: [RFC PATCH v1 1/8] riscv: split sdext and sdtrig config bits Date: Sat, 17 Jan 2026 12:27:22 +0800 Message-ID: <78122e119ee8c961716e2bec72c9895148b04ef9.1768622882.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pg1-x542.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768624577171158500 Content-Type: text/plain; charset="utf-8" Add cfg.ext_sdext and cfg.ext_sdtrig and expose them as ISA extensions. Keep the legacy 'debug' CPU property as a global kill switch and force-disable both when it is off. Trigger CSRs (tselect/tdata*/tinfo/mcontext) and trigger setup now depend on ext_sdtrig instead of cfg.debug. Signed-off-by: Chao Liu --- target/riscv/cpu.c | 18 +++++++++++++++--- target/riscv/cpu_cfg_fields.h.inc | 2 ++ target/riscv/csr.c | 16 ++++++++-------- target/riscv/machine.c | 4 ++-- target/riscv/tcg/tcg-cpu.c | 11 +---------- 5 files changed, 28 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 73d4280d7c..bc0b385cc1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -189,7 +189,8 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), - ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug), + ISA_EXT_DATA_ENTRY(sdext, PRIV_VERSION_1_12_0, ext_sdext), + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha), ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -783,7 +784,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType= type) env->vill =3D true; =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } =20 @@ -922,6 +923,15 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error = **errp) return; } } + + /* + * Keep the legacy 'debug' CPU property as a global kill switch. + * If it is off, force-disable Sdext/Sdtrig regardless of ISA strings. + */ + if (!cpu->cfg.debug) { + cpu->cfg.ext_sdext =3D false; + cpu->cfg.ext_sdtrig =3D false; + } } =20 static void riscv_cpu_realize(DeviceState *dev, Error **errp) @@ -946,7 +956,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) riscv_cpu_register_gdb_regs_for_features(cs); =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.ext_sdtrig) { riscv_trigger_realize(&cpu->env); } #endif @@ -1112,6 +1122,8 @@ static void riscv_cpu_init(Object *obj) */ RISCV_CPU(obj)->cfg.ext_zicntr =3D !mcc->def->bare; RISCV_CPU(obj)->cfg.ext_zihpm =3D !mcc->def->bare; + RISCV_CPU(obj)->cfg.ext_sdext =3D true; + RISCV_CPU(obj)->cfg.ext_sdtrig =3D true; =20 /* Default values for non-bool cpu properties */ cpu->cfg.pmu_mask =3D MAKE_64BIT_MASK(3, 16); diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index a154ecdc79..9701319195 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -44,6 +44,8 @@ BOOL_FIELD(ext_zihpm) BOOL_FIELD(ext_zimop) BOOL_FIELD(ext_zcmop) BOOL_FIELD(ext_ztso) +BOOL_FIELD(ext_sdext) +BOOL_FIELD(ext_sdtrig) BOOL_FIELD(ext_smstateen) BOOL_FIELD(ext_sstc) BOOL_FIELD(ext_smcdeleg) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c91658c3d..4f071b1db2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -775,9 +775,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, = int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 -static RISCVException debug(CPURISCVState *env, int csrno) +static RISCVException sdtrig(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->debug) { + if (riscv_cpu_cfg(env)->ext_sdtrig) { return RISCV_EXCP_NONE; } =20 @@ -6308,12 +6308,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 /* Debug CSRs */ - [CSR_TSELECT] =3D { "tselect", debug, read_tselect, write_tselect= }, - [CSR_TDATA1] =3D { "tdata1", debug, read_tdata, write_tdata = }, - [CSR_TDATA2] =3D { "tdata2", debug, read_tdata, write_tdata = }, - [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata = }, - [CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore = }, - [CSR_MCONTEXT] =3D { "mcontext", debug, read_mcontext, write_mcontex= t }, + [CSR_TSELECT] =3D { "tselect", sdtrig, read_tselect, write_tselec= t }, + [CSR_TDATA1] =3D { "tdata1", sdtrig, read_tdata, write_tdata = }, + [CSR_TDATA2] =3D { "tdata2", sdtrig, read_tdata, write_tdata = }, + [CSR_TDATA3] =3D { "tdata3", sdtrig, read_tdata, write_tdata = }, + [CSR_TINFO] =3D { "tinfo", sdtrig, read_tinfo, write_ignore= }, + [CSR_MCONTEXT] =3D { "mcontext", sdtrig, read_mcontext, write_mconte= xt }, =20 [CSR_MCTRCTL] =3D { "mctrctl", ctr_mmode, NULL, NULL, rmw_xctrc= tl }, [CSR_SCTRCTL] =3D { "sctrctl", ctr_smode, NULL, NULL, rmw_xctrc= tl }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 18d790af0d..d6a0b8e357 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -222,7 +222,7 @@ static bool debug_needed(void *opaque) { RISCVCPU *cpu =3D opaque; =20 - return cpu->cfg.debug; + return cpu->cfg.ext_sdext || cpu->cfg.ext_sdtrig; } =20 static int debug_post_load(void *opaque, int version_id) @@ -230,7 +230,7 @@ static int debug_post_load(void *opaque, int version_id) RISCVCPU *cpu =3D opaque; CPURISCVState *env =3D &cpu->env; =20 - if (icount_enabled()) { + if (cpu->cfg.ext_sdtrig && icount_enabled()) { env->itrigger_enabled =3D riscv_itrigger_enabled(env); } =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index d3968251fa..b5a26cf662 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -177,7 +177,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; } =20 - if (cpu->cfg.debug && !icount_enabled()) { + if (cpu->cfg.ext_sdtrig && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); } #endif @@ -469,15 +469,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV= CPU *cpu) continue; } =20 - /* - * cpu.debug =3D true is marked as 'sdtrig', priv spec 1.12. - * Skip this warning since existing CPUs with older priv - * spec and debug =3D true will be impacted. - */ - if (!strcmp(edata->name, "sdtrig")) { - continue; - } - isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); =20 /* --=20 2.52.0 From nobody Sun Feb 8 04:34:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1768624564; 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Fri, 16 Jan 2026 20:27:43 -0800 (PST) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wangjingwei@iscas.ac.cn, Chao Liu Subject: [RFC PATCH v1 2/8] riscv: add sdext debug CSRs state Date: Sat, 17 Jan 2026 12:27:23 +0800 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pg1-x541.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768624567262158500 Content-Type: text/plain; charset="utf-8" RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Add architectural state for Sdext Debug Mode: debug_mode, dcsr, dpc and dscratch0/1. Wire up CSR access for dcsr/dpc/dscratch and gate them to Debug Mode (or host debugger access). Also migrate the new state in vmstate_debug. Signed-off-by: Chao Liu --- target/riscv/cpu.c | 5 ++ target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 33 ++++++++++ target/riscv/csr.c | 133 ++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 8 ++- 5 files changed, 181 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bc0b385cc1..d7c0f255a8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -782,6 +782,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTyp= e type) /* Default NaN value: sign bit clear, frac msb set */ set_float_default_nan_pattern(0b01000000, &env->fp_status); env->vill =3D true; + env->debug_mode =3D false; + env->dcsr =3D DCSR_DEBUGVER(4); + env->dpc =3D 0; + env->dscratch[0] =3D 0; + env->dscratch[1] =3D 0; =20 #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sdtrig) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 36e7f10037..18ebac830a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -482,6 +482,10 @@ struct CPUArchState { =20 /* True if in debugger mode. */ bool debugger; + bool debug_mode; + target_ulong dcsr; + target_ulong dpc; + target_ulong dscratch[2]; =20 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; uint64_t hstateen[SMSTATEEN_MAX_COUNT]; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b62dd82fe7..bb59f7ff56 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -467,6 +467,39 @@ #define CSR_DCSR 0x7b0 #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 +#define CSR_DSCRATCH1 0x7b3 + +/* DCSR fields */ +#define DCSR_XDEBUGVER_SHIFT 28 +#define DCSR_XDEBUGVER_MASK (0xfu << DCSR_XDEBUGVER_SHIFT) +#define DCSR_DEBUGVER(val) ((target_ulong)(val) << DCSR_XDEBUGVER_SHI= FT) +#define DCSR_EXTCAUSE_SHIFT 24 +#define DCSR_EXTCAUSE_MASK (0x7u << DCSR_EXTCAUSE_SHIFT) +#define DCSR_CETRIG BIT(19) +#define DCSR_PELP BIT(18) +#define DCSR_EBREAKVS BIT(17) +#define DCSR_EBREAKVU BIT(16) +#define DCSR_EBREAKM BIT(15) +#define DCSR_EBREAKS BIT(13) +#define DCSR_EBREAKU BIT(12) +#define DCSR_STEPIE BIT(11) +#define DCSR_STOPCOUNT BIT(10) +#define DCSR_STOPTIME BIT(9) +#define DCSR_CAUSE_SHIFT 6 +#define DCSR_CAUSE_MASK (0x7u << DCSR_CAUSE_SHIFT) +#define DCSR_V BIT(5) +#define DCSR_MPRVEN BIT(4) +#define DCSR_NMIP BIT(3) +#define DCSR_STEP BIT(2) +#define DCSR_PRV_MASK 0x3u + +#define DCSR_CAUSE_EBREAK 1 +#define DCSR_CAUSE_TRIGGER 2 +#define DCSR_CAUSE_HALTREQ 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_RESET 5 +#define DCSR_CAUSE_GROUP 6 +#define DCSR_CAUSE_OTHER 7 =20 /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4f071b1db2..4a732b9364 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3171,6 +3171,131 @@ static RISCVException write_mtval(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +#ifndef CONFIG_USER_ONLY +static bool riscv_sdext_available(CPURISCVState *env) +{ + return riscv_cpu_cfg(env)->ext_sdext; +} + +static RISCVException dcsr_predicate(CPURISCVState *env, int csrno) +{ + if (!riscv_sdext_available(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (!env->debug_mode && !env->debugger) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + +static target_ulong dcsr_visible_mask(CPURISCVState *env) +{ + target_ulong mask =3D (target_ulong)-1; + RISCVCPU *cpu =3D env_archcpu(env); + + if (!riscv_has_ext(env, RVH)) { + mask &=3D ~(DCSR_EBREAKVS | DCSR_EBREAKVU | DCSR_V); + } + if (!riscv_has_ext(env, RVS)) { + mask &=3D ~DCSR_EBREAKS; + } + if (!riscv_has_ext(env, RVU)) { + mask &=3D ~DCSR_EBREAKU; + } + if (!cpu->cfg.ext_zicfilp) { + mask &=3D ~DCSR_PELP; + } + if (!cpu->cfg.ext_smdbltrp) { + mask &=3D ~DCSR_CETRIG; + } + + return mask; +} + +static RISCVException read_dcsr(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->dcsr & dcsr_visible_mask(env); + return RISCV_EXCP_NONE; +} + +static target_ulong dcsr_writable_mask(CPURISCVState *env) +{ + target_ulong mask =3D DCSR_EBREAKM | DCSR_EBREAKS | DCSR_EBREAKU | + DCSR_STEPIE | DCSR_STOPCOUNT | DCSR_STOPTIME | + DCSR_STEP | DCSR_PRV_MASK; + RISCVCPU *cpu =3D env_archcpu(env); + + mask |=3D DCSR_MPRVEN; + + if (riscv_has_ext(env, RVH)) { + mask |=3D DCSR_EBREAKVS | DCSR_EBREAKVU | DCSR_V; + } + if (riscv_has_ext(env, RVS)) { + mask |=3D DCSR_EBREAKS; + } + if (riscv_has_ext(env, RVU)) { + mask |=3D DCSR_EBREAKU; + } + if (cpu->cfg.ext_zicfilp) { + mask |=3D DCSR_PELP; + } + if (cpu->cfg.ext_smdbltrp) { + mask |=3D DCSR_CETRIG; + } + + return mask; +} + +static RISCVException write_dcsr(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + target_ulong mask =3D dcsr_writable_mask(env); + target_ulong new_val =3D env->dcsr; + + new_val &=3D ~mask; + new_val |=3D val & mask; + new_val &=3D ~DCSR_XDEBUGVER_MASK; + new_val |=3D DCSR_DEBUGVER(4); + env->dcsr =3D new_val; + return RISCV_EXCP_NONE; +} + +static RISCVException read_dpc(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->dpc & get_xepc_mask(env); + return RISCV_EXCP_NONE; +} + +static RISCVException write_dpc(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + env->dpc =3D val & get_xepc_mask(env); + return RISCV_EXCP_NONE; +} + +static RISCVException read_dscratch(CPURISCVState *env, int csrno, + target_ulong *val) +{ + int index =3D (csrno =3D=3D CSR_DSCRATCH1) ? 1 : 0; + + *val =3D env->dscratch[index]; + return RISCV_EXCP_NONE; +} + +static RISCVException write_dscratch(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + int index =3D (csrno =3D=3D CSR_DSCRATCH1) ? 1 : 0; + + env->dscratch[index] =3D val; + return RISCV_EXCP_NONE; +} +#endif /* !CONFIG_USER_ONLY */ + /* Execution environment configuration setup */ static RISCVException read_menvcfg(CPURISCVState *env, int csrno, target_ulong *val) @@ -6314,6 +6439,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_TDATA3] =3D { "tdata3", sdtrig, read_tdata, write_tdata = }, [CSR_TINFO] =3D { "tinfo", sdtrig, read_tinfo, write_ignore= }, [CSR_MCONTEXT] =3D { "mcontext", sdtrig, read_mcontext, write_mconte= xt }, +#if !defined(CONFIG_USER_ONLY) + [CSR_DCSR] =3D { "dcsr", dcsr_predicate, read_dcsr, write_dcsr }, + [CSR_DPC] =3D { "dpc", dcsr_predicate, read_dpc, write_dpc }, + [CSR_DSCRATCH] =3D { "dscratch0", dcsr_predicate, + read_dscratch, write_dscratch }, + [CSR_DSCRATCH1] =3D { "dscratch1", dcsr_predicate, + read_dscratch, write_dscratch }, +#endif =20 [CSR_MCTRCTL] =3D { "mctrctl", ctr_mmode, NULL, NULL, rmw_xctrc= tl }, [CSR_SCTRCTL] =3D { "sctrctl", ctr_smode, NULL, NULL, rmw_xctrc= tl }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index d6a0b8e357..c6fe2d8541 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -239,8 +239,8 @@ static int debug_post_load(void *opaque, int version_id) =20 static const VMStateDescription vmstate_debug =3D { .name =3D "cpu/debug", - .version_id =3D 2, - .minimum_version_id =3D 2, + .version_id =3D 3, + .minimum_version_id =3D 3, .needed =3D debug_needed, .post_load =3D debug_post_load, .fields =3D (const VMStateField[]) { @@ -248,6 +248,10 @@ static const VMStateDescription vmstate_debug =3D { VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_BOOL_V(env.debug_mode, RISCVCPU, 3), + VMSTATE_UINTTL_V(env.dcsr, RISCVCPU, 3), + VMSTATE_UINTTL_V(env.dpc, RISCVCPU, 3), + VMSTATE_UINTTL_ARRAY_V(env.dscratch, RISCVCPU, 2, 3), VMSTATE_END_OF_LIST() } }; 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Fri, 16 Jan 2026 20:27:45 -0800 (PST) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wangjingwei@iscas.ac.cn, Chao Liu Subject: [RFC PATCH v1 3/8] riscv: add sdext Debug Mode helpers Date: Sat, 17 Jan 2026 12:27:24 +0800 Message-ID: <8230a1b0633140c228d063602e93120f0963c3e6.1768622882.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pf1-x444.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768624577040158500 Content-Type: text/plain; charset="utf-8" RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Add helpers to enter/leave Debug Mode and to update dpc/dcsr. Model resume without a Debug Module by leaving Debug Mode at cpu_exec_enter and continuing from dpc. Signed-off-by: Chao Liu --- target/riscv/cpu.h | 3 ++ target/riscv/cpu_helper.c | 87 ++++++++++++++++++++++++++++++++++++++ target/riscv/debug.c | 5 +++ target/riscv/tcg/tcg-cpu.c | 14 ++++++ 4 files changed, 109 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 18ebac830a..ca861aa5f8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -630,6 +630,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, char *riscv_isa_string(RISCVCPU *cpu); int riscv_cpu_max_xlen(RISCVCPUClass *mcc); bool riscv_cpu_option_set(const char *optname); +void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc, + uint32_t cause); +void riscv_cpu_leave_debug_mode(CPURISCVState *env); =20 #ifndef CONFIG_USER_ONLY void riscv_cpu_do_interrupt(CPUState *cpu); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c4fb68b5de..83d2aa1b75 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -136,6 +136,93 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env= , bool virt) #endif } =20 +#ifndef CONFIG_USER_ONLY +static bool riscv_sdext_enabled(CPURISCVState *env) +{ + return riscv_cpu_cfg(env)->ext_sdext; +} +#endif + +void riscv_cpu_enter_debug_mode(CPURISCVState *env, target_ulong pc, + uint32_t cause) +{ +#ifndef CONFIG_USER_ONLY + if (!riscv_sdext_enabled(env)) { + return; + } +#endif + env->debug_mode =3D true; + env->dpc =3D pc & get_xepc_mask(env); + env->dcsr &=3D ~(DCSR_CAUSE_MASK | DCSR_PRV_MASK | DCSR_V); + env->dcsr |=3D ((target_ulong)(cause & 0x7)) << DCSR_CAUSE_SHIFT; + env->dcsr |=3D env->priv & DCSR_PRV_MASK; + if (env->virt_enabled && riscv_has_ext(env, RVH)) { + env->dcsr |=3D DCSR_V; + } +#ifndef CONFIG_USER_ONLY + if (env_archcpu(env)->cfg.ext_zicfilp) { + if (env->elp) { + env->dcsr |=3D DCSR_PELP; + } else { + env->dcsr &=3D ~DCSR_PELP; + } + env->elp =3D false; + } +#endif +} + +void riscv_cpu_leave_debug_mode(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + if (!riscv_sdext_enabled(env)) { + return; + } +#endif + target_ulong new_priv =3D env->dcsr & DCSR_PRV_MASK; + bool new_virt =3D riscv_has_ext(env, RVH) && (env->dcsr & DCSR_V); + + if (new_priv > PRV_M) { + new_priv =3D PRV_M; + } + if (new_priv =3D=3D PRV_M) { + new_virt =3D false; + } +#ifndef CONFIG_USER_ONLY + if (new_priv =3D=3D PRV_S && !riscv_has_ext(env, RVS)) { + new_priv =3D PRV_M; + new_virt =3D false; + } else if (new_priv =3D=3D PRV_U && !riscv_has_ext(env, RVU)) { + new_priv =3D riscv_has_ext(env, RVS) ? PRV_S : PRV_M; + new_virt =3D false; + } +#endif + + env->debug_mode =3D false; + riscv_cpu_set_mode(env, new_priv, new_virt); + +#ifndef CONFIG_USER_ONLY + if (env_archcpu(env)->cfg.ext_zicfilp) { + env->elp =3D cpu_get_fcfien(env) && (env->dcsr & DCSR_PELP); + env->dcsr &=3D ~DCSR_PELP; + } +#endif + + if (new_priv !=3D PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MPRV, 0); + } +#ifndef CONFIG_USER_ONLY + if (env_archcpu(env)->cfg.ext_smdbltrp && new_priv !=3D PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 0); + } + if (env_archcpu(env)->cfg.ext_ssdbltrp && (new_priv =3D=3D PRV_U || ne= w_virt)) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_SDT, 0); + if (new_virt && new_priv =3D=3D PRV_U) { + env->vsstatus =3D set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } +#endif +} + RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 5664466749..5877a60c50 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -927,6 +927,11 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; =20 + /* Triggers must not match or fire while in Debug Mode. */ + if (env->debug_mode) { + return; + } + if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { do_trigger_action(env, DBG_ACTION_BP); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b5a26cf662..2b543ced07 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -261,6 +261,19 @@ static vaddr riscv_pointer_wrap(CPUState *cs, int mmu_= idx, } return extract64(result, 0, 64 - pm_len); } + +static void riscv_cpu_exec_enter(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + if (!cpu->cfg.ext_sdext || !env->debug_mode) { + return; + } + target_ulong pc =3D env->dpc; + riscv_cpu_leave_debug_mode(env); + env->pc =3D pc; +} #endif =20 const TCGCPUOps riscv_tcg_ops =3D { @@ -277,6 +290,7 @@ const TCGCPUOps riscv_tcg_ops =3D { #ifndef CONFIG_USER_ONLY .tlb_fill =3D riscv_cpu_tlb_fill, .pointer_wrap =3D riscv_pointer_wrap, + .cpu_exec_enter =3D riscv_cpu_exec_enter, .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, .cpu_exec_halt =3D riscv_cpu_has_work, .cpu_exec_reset =3D cpu_reset, --=20 2.52.0 From nobody Sun Feb 8 04:34:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 16 Jan 2026 20:27:48 -0800 (PST) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wangjingwei@iscas.ac.cn, Chao Liu Subject: [RFC PATCH v1 4/8] riscv: add dret instruction Date: Sat, 17 Jan 2026 12:27:25 +0800 Message-ID: <4e95ab6c30b7ca58140533eda21801c1bf6b9243.1768622882.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pg1-x543.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768624521380158500 Content-Type: text/plain; charset="utf-8" RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Add DRET decode/translate and a helper to leave Debug Mode and return to dpc. Executing DRET outside Debug Mode raises illegal instruction. Signed-off-by: Chao Liu --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_privileged.c.inc | 18 ++++++++++++++++++ target/riscv/op_helper.c | 16 ++++++++++++++++ 4 files changed, 36 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b785456ee0..6140b6340d 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) +DEF_HELPER_1(dret, tl, env) DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(ctr_clear, void, env) DEF_HELPER_1(wfi, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index cd23b1f3a9..318d330c57 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -118,6 +118,7 @@ sctrclr 000100000100 00000 000 00000 1110011 uret 0000000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 +dret 0111101 10010 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma =20 diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 8a62b4cfcd..f8641b1977 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -125,6 +125,24 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #endif } =20 +static bool trans_dret(DisasContext *ctx, arg_dret *a) +{ +#ifndef CONFIG_USER_ONLY + if (!ctx->cfg_ptr->ext_sdext) { + return false; + } + decode_save_opc(ctx, 0); + translator_io_start(&ctx->base); + gen_update_pc(ctx, 0); + gen_helper_dret(cpu_pc, tcg_env); + exit_tb(ctx); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +#else + return false; +#endif +} + static bool trans_mnret(DisasContext *ctx, arg_mnret *a) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 6ccc127c30..99736bbebb 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -454,6 +454,22 @@ target_ulong helper_mret(CPURISCVState *env) return retpc; } =20 +target_ulong helper_dret(CPURISCVState *env) +{ + uintptr_t ra =3D GETPC(); +#ifdef CONFIG_USER_ONLY + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); + return 0; +#else + if (!riscv_cpu_cfg(env)->ext_sdext || !env->debug_mode) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); + } + target_ulong retpc =3D env->dpc & get_xepc_mask(env); + riscv_cpu_leave_debug_mode(env); + return retpc; +#endif +} + target_ulong helper_mnret(CPURISCVState *env) { target_ulong retpc =3D env->mnepc; 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Fri, 16 Jan 2026 20:27:51 -0800 (PST) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wangjingwei@iscas.ac.cn, Chao Liu Subject: [RFC PATCH v1 5/8] riscv: add sdext enter Debug Mode on ebreak Date: Sat, 17 Jan 2026 12:27:26 +0800 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pf1-x444.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768624588705158500 Content-Type: text/plain; charset="utf-8" RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Route EBREAK via helper_sdext_ebreak. If Sdext is enabled and the matching dcsr.ebreak* bit is set, enter Debug Mode with cause=3Debreak and stop with EXCP_DEBUG. Otherwise keep the normal breakpoint trap. Signed-off-by: Chao Liu --- target/riscv/helper.h | 1 + .../riscv/insn_trans/trans_privileged.c.inc | 6 ++-- target/riscv/op_helper.c | 36 +++++++++++++++++++ 3 files changed, 40 insertions(+), 3 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6140b6340d..acff73051b 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -141,6 +141,7 @@ DEF_HELPER_1(tlb_flush_all, void, env) DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) +DEF_HELPER_2(sdext_ebreak, void, env, tl) #endif =20 /* Hypervisor functions */ diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index f8641b1977..377f551bb3 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -68,9 +68,9 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) if (pre =3D=3D 0x01f01013 && ebreak =3D=3D 0x00100073 && post =3D=3D 0= x40705013) { generate_exception(ctx, RISCV_EXCP_SEMIHOST); } else { - tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env, - offsetof(CPURISCVState, badaddr)); - generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + gen_update_pc(ctx, 0); + gen_helper_sdext_ebreak(tcg_env, tcg_constant_tl(ebreak_addr)); + ctx->base.is_jmp =3D DISAS_NORETURN; } return true; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 99736bbebb..dfe5388ab7 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -470,6 +470,42 @@ target_ulong helper_dret(CPURISCVState *env) #endif } =20 +void helper_sdext_ebreak(CPURISCVState *env, target_ulong pc) +{ +#ifndef CONFIG_USER_ONLY + CPUState *cs =3D env_cpu(env); + bool enter_debug =3D false; + + if (riscv_cpu_cfg(env)->ext_sdext && !env->debug_mode) { + if (env->virt_enabled) { + if (env->priv =3D=3D PRV_S) { + enter_debug =3D env->dcsr & DCSR_EBREAKVS; + } else if (env->priv =3D=3D PRV_U) { + enter_debug =3D env->dcsr & DCSR_EBREAKVU; + } + } else { + if (env->priv =3D=3D PRV_M) { + enter_debug =3D env->dcsr & DCSR_EBREAKM; + } else if (env->priv =3D=3D PRV_S) { + enter_debug =3D env->dcsr & DCSR_EBREAKS; + } else if (env->priv =3D=3D PRV_U) { + enter_debug =3D env->dcsr & DCSR_EBREAKU; + } + } + } + + env->badaddr =3D pc; + + if (enter_debug) { + riscv_cpu_enter_debug_mode(env, pc, DCSR_CAUSE_EBREAK); + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit_restore(cs, GETPC()); + } + + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, GETPC()); +#endif +} + target_ulong helper_mnret(CPURISCVState *env) { target_ulong retpc =3D env->mnepc; --=20 2.52.0 From nobody Sun Feb 8 04:34:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1768624583; cv=none; d=zohomail.com; s=zohoarc; b=MxC+x7ujUwO6d8Tzxn/idfLeeSPa7huNRN5t3FThaLOKwJ+fcI5rDpJ5DRWAz4rYWHXBqdf3ZvO1ZnXq5b12qnDwBN/qvMj061l42RWeonFJhuuh6x9PUr0WYGprV5FccNwMk9/y+BjuXolOrz4LydIOL4R7AJ9sye+GIcB1C50= ARC-Message-Signature: i=1; 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Fri, 16 Jan 2026 20:27:54 -0800 (PST) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wangjingwei@iscas.ac.cn, Chao Liu Subject: [RFC PATCH v1 6/8] riscv: add sdext single-step support Date: Sat, 17 Jan 2026 12:27:27 +0800 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pf1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768624584756158500 Content-Type: text/plain; charset="utf-8" RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Use a TB flag when dcsr.step is set (and we are not in Debug Mode). When the flag is on, build 1-insn TBs and do not chain to the next TB. Add a TB-exit helper that enters Debug Mode with cause=3Dstep and sets dpc to the next pc, then stops with EXCP_DEBUG. If dcsr.stepie is 0, do not take interrupts while stepping. Treat WFI as a nop so the hart does not sleep during a step. PS: This patch references Max Chou's handling of ext_tb_flags. https://lore.kernel.org/qemu-devel/20260108132631.9429-6-max.chou@sifive.co= m/ Signed-off-by: Chao Liu --- include/exec/translation-block.h | 3 ++- target/riscv/cpu.h | 3 +++ target/riscv/cpu_helper.c | 6 ++++++ target/riscv/csr.c | 21 +++++++-------------- target/riscv/helper.h | 1 + target/riscv/op_helper.c | 20 ++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 9 ++++++++- target/riscv/translate.c | 16 ++++++++++++++-- 8 files changed, 61 insertions(+), 18 deletions(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index cdce399eba..75188f56c8 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -62,7 +62,8 @@ struct TranslationBlock { * x86: the original user, the Code Segment virtual base, * arm: an extension of tb->flags, * s390x: instruction data for EXECUTE, - * sparc: the next pc of the instruction queue (for delay slots). + * sparc: the next pc of the instruction queue (for delay slots), + * riscv: an extension of tb->flags. */ uint64_t cs_base; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ca861aa5f8..fe37ae8458 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -712,6 +712,9 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) FIELD(TB_FLAGS, PM_PMM, 29, 2) FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) =20 +/* sdext single-step needs a TB flag to build 1-insn TBs */ +FIELD(EXT_TB_FLAGS, SDEXT_STEP, 33, 1) + #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 83d2aa1b75..d8905a5a1e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -638,6 +638,12 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) if (interrupt_request & mask) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + + if (cpu->cfg.ext_sdext && !env->debug_mode && + (env->dcsr & DCSR_STEP) && !(env->dcsr & DCSR_STEPIE)) { + return false; + } + int interruptno =3D riscv_cpu_local_irq_pending(env); if (interruptno >=3D 0) { cs->exception_index =3D RISCV_EXCP_INT_FLAG | interruptno; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4a732b9364..8dff9615c4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3171,15 +3171,10 @@ static RISCVException write_mtval(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 -#ifndef CONFIG_USER_ONLY -static bool riscv_sdext_available(CPURISCVState *env) -{ - return riscv_cpu_cfg(env)->ext_sdext; -} - -static RISCVException dcsr_predicate(CPURISCVState *env, int csrno) +#if !defined(CONFIG_USER_ONLY) +static RISCVException sdext(CPURISCVState *env, int csrno) { - if (!riscv_sdext_available(env)) { + if (!riscv_cpu_cfg(env)->ext_sdext) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -6440,12 +6435,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_TINFO] =3D { "tinfo", sdtrig, read_tinfo, write_ignore= }, [CSR_MCONTEXT] =3D { "mcontext", sdtrig, read_mcontext, write_mconte= xt }, #if !defined(CONFIG_USER_ONLY) - [CSR_DCSR] =3D { "dcsr", dcsr_predicate, read_dcsr, write_dcsr }, - [CSR_DPC] =3D { "dpc", dcsr_predicate, read_dpc, write_dpc }, - [CSR_DSCRATCH] =3D { "dscratch0", dcsr_predicate, - read_dscratch, write_dscratch }, - [CSR_DSCRATCH1] =3D { "dscratch1", dcsr_predicate, - read_dscratch, write_dscratch }, + [CSR_DCSR] =3D { "dcsr", sdext, read_dcsr, write_dcsr }, + [CSR_DPC] =3D { "dpc", sdext, read_dpc, write_dpc }, + [CSR_DSCRATCH] =3D { "dscratch0", sdext, read_dscratch, write_dscrat= ch }, + [CSR_DSCRATCH1] =3D { "dscratch1", sdext, read_dscratch, write_dscrat= ch }, #endif =20 [CSR_MCTRCTL] =3D { "mctrctl", ctr_mmode, NULL, NULL, rmw_xctrc= tl }, diff --git a/target/riscv/helper.h b/target/riscv/helper.h index acff73051b..0b709c2b99 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -141,6 +141,7 @@ DEF_HELPER_1(tlb_flush_all, void, env) DEF_HELPER_4(ctr_add_entry, void, env, tl, tl, tl) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) +DEF_HELPER_1(sdext_step, void, env) DEF_HELPER_2(sdext_ebreak, void, env, tl) #endif =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index dfe5388ab7..6fe29ce905 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -470,6 +470,22 @@ target_ulong helper_dret(CPURISCVState *env) #endif } =20 +void helper_sdext_step(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + CPUState *cs =3D env_cpu(env); + + if (!riscv_cpu_cfg(env)->ext_sdext || env->debug_mode || + !(env->dcsr & DCSR_STEP)) { + return; + } + + riscv_cpu_enter_debug_mode(env, env->pc, DCSR_CAUSE_STEP); + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit_restore(cs, GETPC()); +#endif +} + void helper_sdext_ebreak(CPURISCVState *env, target_ulong pc) { #ifndef CONFIG_USER_ONLY @@ -604,6 +620,10 @@ void helper_wfi(CPURISCVState *env) (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW))))= { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { + if (riscv_cpu_cfg(env)->ext_sdext && !env->debug_mode && + (env->dcsr & DCSR_STEP)) { + return; + } cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; cpu_loop_exit(cs); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 2b543ced07..0426855145 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -104,6 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; + uint64_t ext_flags =3D 0; bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); =20 if (cpu->cfg.ext_zve32x) { @@ -189,10 +190,16 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState = *cs) flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.ext_sdext && !env->debug_mode && (env->dcsr & DCSR_STEP))= { + ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, SDEXT_STEP, 1); + } +#endif + return (TCGTBCPUState){ .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, .flags =3D flags, - .cs_base =3D env->misa_ext, + .cs_base =3D ext_flags, }; } =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e1f4dc5ffd..4660387164 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -110,6 +110,8 @@ typedef struct DisasContext { bool ztso; /* Use icount trigger for native debug */ bool itrigger; + /* Enter Debug Mode after next instruction (sdext single-step). */ + bool sdext_step; /* FRM is known to contain a valid value. */ bool frm_valid; bool insn_start_updated; @@ -284,6 +286,9 @@ static void lookup_and_goto_ptr(DisasContext *ctx) if (ctx->itrigger) { gen_helper_itrigger_match(tcg_env); } + if (ctx->sdext_step) { + gen_helper_sdext_step(tcg_env); + } #endif tcg_gen_lookup_and_goto_ptr(); } @@ -294,6 +299,9 @@ static void exit_tb(DisasContext *ctx) if (ctx->itrigger) { gen_helper_itrigger_match(tcg_env); } + if (ctx->sdext_step) { + gen_helper_sdext_step(tcg_env); + } #endif tcg_gen_exit_tb(NULL, 0); } @@ -307,7 +315,8 @@ static void gen_goto_tb(DisasContext *ctx, unsigned tb_= slot_idx, * Under itrigger, instruction executes one by one like singlestep, * direct block chain benefits will be small. */ - if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { + if (translator_use_goto_tb(&ctx->base, dest) && + !ctx->itrigger && !ctx->sdext_step) { /* * For pcrel, the pc must always be up-to-date on entry to * the linked TB, so that it can use simple additions for all @@ -1297,6 +1306,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); uint32_t tb_flags =3D ctx->base.tb->flags; + uint64_t ext_tb_flags =3D ctx->base.tb->cs_base; =20 ctx->pc_save =3D ctx->base.pc_first; ctx->priv =3D FIELD_EX32(tb_flags, TB_FLAGS, PRIV); @@ -1333,6 +1343,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->bcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); ctx->fcfi_lp_expected =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPEC= TED); ctx->fcfi_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED); + ctx->sdext_step =3D FIELD_EX64(ext_tb_flags, EXT_TB_FLAGS, SDEXT_STEP); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; ctx->decoders =3D cpu->decoders; @@ -1383,7 +1394,8 @@ static void riscv_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) =20 /* Only the first insn within a TB is allowed to cross a page boundary= . */ if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { - if (ctx->itrigger || !translator_is_same_page(&ctx->base, ctx->bas= e.pc_next)) { + if (ctx->itrigger || ctx->sdext_step || + !translator_is_same_page(&ctx->base, ctx->base.pc_next)) { ctx->base.is_jmp =3D DISAS_TOO_MANY; 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Fri, 16 Jan 2026 20:27:57 -0800 (PST) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wangjingwei@iscas.ac.cn, Chao Liu Subject: [RFC PATCH v1 7/8] riscv: add sdtrig trigger action=debug mode Date: Sat, 17 Jan 2026 12:27:28 +0800 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pg1-x541.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768624588774158500 Content-Type: text/plain; charset="utf-8" RISC-V Debug Specification: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0 Allow mcontrol/mcontrol6 action=3D1 when Sdext is enabled. When such a trigger hits, enter Debug Mode with cause=3Dtrigger and stop with EXCP_DEBUG. Also report inst-count triggers in tinfo and read their action field. Signed-off-by: Chao Liu --- target/riscv/debug.c | 53 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 5877a60c50..4e30d42905 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -110,6 +110,8 @@ static trigger_action_t get_trigger_action(CPURISCVStat= e *env, action =3D (tdata1 & TYPE6_ACTION) >> 12; break; case TRIGGER_TYPE_INST_CNT: + action =3D tdata1 & ITRIGGER_ACTION; + break; case TRIGGER_TYPE_INT: case TRIGGER_TYPE_EXCP: case TRIGGER_TYPE_EXT_SRC: @@ -280,6 +282,7 @@ static target_ulong textra_validate(CPURISCVState *env,= target_ulong tdata3) =20 static void do_trigger_action(CPURISCVState *env, target_ulong trigger_ind= ex) { + CPUState *cs =3D env_cpu(env); trigger_action_t action =3D get_trigger_action(env, trigger_index); =20 switch (action) { @@ -289,6 +292,21 @@ static void do_trigger_action(CPURISCVState *env, targ= et_ulong trigger_index) riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); break; case DBG_ACTION_DBG_MODE: + if (!env_archcpu(env)->cfg.ext_sdext) { + qemu_log_mask(LOG_UNIMP, + "trigger action=3Ddebug mode requires Sdext\n"); + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + riscv_cpu_enter_debug_mode(env, env->pc, DCSR_CAUSE_TRIGGER); + /* + * If this came from the Trigger Module's CPU breakpoint/watchpoin= t, + * we're already returning via EXCP_DEBUG. Otherwise, stop now. + */ + if (cs->exception_index !=3D EXCP_DEBUG) { + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit_restore(cs, GETPC()); + } + break; case DBG_ACTION_TRACE0: case DBG_ACTION_TRACE1: case DBG_ACTION_TRACE2: @@ -441,6 +459,7 @@ static target_ulong type2_mcontrol_validate(CPURISCVSta= te *env, { target_ulong val; uint32_t size; + uint32_t action; =20 /* validate the generic part first */ val =3D tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH); @@ -448,11 +467,25 @@ static target_ulong type2_mcontrol_validate(CPURISCVS= tate *env, /* validate unimplemented (always zero) bits */ warn_always_zero_bit(ctrl, TYPE2_MATCH, "match"); warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain"); - warn_always_zero_bit(ctrl, TYPE2_ACTION, "action"); warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing"); warn_always_zero_bit(ctrl, TYPE2_SELECT, "select"); warn_always_zero_bit(ctrl, TYPE2_HIT, "hit"); =20 + action =3D (ctrl & TYPE2_ACTION) >> 12; + if (action =3D=3D DBG_ACTION_BP) { + val |=3D ctrl & TYPE2_ACTION; + } else if (action =3D=3D DBG_ACTION_DBG_MODE) { + if (env_archcpu(env)->cfg.ext_sdext) { + val |=3D ctrl & TYPE2_ACTION; + } else { + qemu_log_mask(LOG_UNIMP, + "trigger action=3Ddebug mode requires Sdext\n"); + } + } else { + qemu_log_mask(LOG_UNIMP, "trigger action: %u is not supported\n", + action); + } + /* validate size encoding */ size =3D type2_breakpoint_size(env, ctrl); if (access_size[size] =3D=3D -1) { @@ -569,6 +602,7 @@ static target_ulong type6_mcontrol6_validate(CPURISCVSt= ate *env, { target_ulong val; uint32_t size; + uint32_t action; =20 /* validate the generic part first */ val =3D tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6); @@ -576,11 +610,25 @@ static target_ulong type6_mcontrol6_validate(CPURISCV= State *env, /* validate unimplemented (always zero) bits */ warn_always_zero_bit(ctrl, TYPE6_MATCH, "match"); warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain"); - warn_always_zero_bit(ctrl, TYPE6_ACTION, "action"); warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing"); warn_always_zero_bit(ctrl, TYPE6_SELECT, "select"); warn_always_zero_bit(ctrl, TYPE6_HIT, "hit"); =20 + action =3D (ctrl & TYPE6_ACTION) >> 12; + if (action =3D=3D DBG_ACTION_BP) { + val |=3D ctrl & TYPE6_ACTION; + } else if (action =3D=3D DBG_ACTION_DBG_MODE) { + if (env_archcpu(env)->cfg.ext_sdext) { + val |=3D ctrl & TYPE6_ACTION; + } else { + qemu_log_mask(LOG_UNIMP, + "trigger action=3Ddebug mode requires Sdext\n"); + } + } else { + qemu_log_mask(LOG_UNIMP, "trigger action: %u is not supported\n", + action); + } + /* validate size encoding */ size =3D extract32(ctrl, 16, 4); if (access_size[size] =3D=3D -1) { @@ -919,6 +967,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env) { /* assume all triggers support the same types of triggers */ return BIT(TRIGGER_TYPE_AD_MATCH) | + BIT(TRIGGER_TYPE_INST_CNT) | BIT(TRIGGER_TYPE_AD_MATCH6); } =20 --=20 2.52.0 From nobody Sun Feb 8 04:34:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 16 Jan 2026 20:28:00 -0800 (PST) From: Chao Liu To: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wangjingwei@iscas.ac.cn, Chao Liu Subject: [RFC PATCH v1 8/8] tests: update riscv64 virt RHCT Date: Sat, 17 Jan 2026 12:27:29 +0800 Message-ID: X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-pf1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1768624531023158500 Content-Type: text/plain; charset="utf-8" Update the golden RHCT table for riscv64 virt after the Sdext/Sdtrig changes. Rebuilt with tests/data/acpi/ rebuild-expected-aml.sh. Signed-off-by: Chao Liu --- tests/data/acpi/riscv64/virt/RHCT | Bin 416 -> 422 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/vi= rt/RHCT index 52a4cc4b6380eee3299b965271a39e9e01f5a698..b9a288b299ef98491d33d3c5cda= 59c50ab434fc9 100644 GIT binary patch delta 42 ycmZ3$yo{ME$iq2g86yJ&quE3*16CJCMh5GN_G_3@D<(eQ$Wg<{z|h9XzyJW>g$hRi delta 39 vcmZ3+ynvZ2$iq2g0V4wg