Hi!
On 11/14/24 23:36, Babu Moger wrote:
>
> This series addresses the following issues with EPYC CPU models.
>
> 1. Update the L1, L2, L3 cache properties to match the actual hardware (PPR).
> This needs to be updated on all the EPYC models.
> 2. RAS feature bits (SUCCOR, McaOverflowRecov).
> 3. Add SVM feature bits which are required in nested guests.
> 4. Add perfmon-v2 on Genoa.
> 5. Add missing feature bit fs-gs-base-ns(WRMSR to {FS,GS,KERNEL_G}S_BASE
> is non-serializing).
>
Seems good for me. I've tested cache changes.
If needed, Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
> Dropped EPYC-Turin model for now. Some of the feature bits
> (srso-user-kernel-no, eraps, rapsize) are still work in progress in
> the kernel. Will post them later.
>
> Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip
> ---
> v4: Some of the patches in v3 are already merged. Posting the rest of the patches.
> Dropped EPYC-Turin model for now. Will post them later.
> Added SVM feature bit as discussed in
> https://lore.kernel.org/kvm/b4b7abae-669a-4a86-81d3-d1f677a82929@redhat.com/
> Fixed the cache property details as discussed in
> https://lore.kernel.org/kvm/20230504205313.225073-8-babu.moger@amd.com/
> Thanks to Maksim and Paolo for their feedback.
>
> v3: Added SBPB, IBPB_BRTYPE, SRSO_USER_KERNEL_NO, ERAPS and RAPSIZE bits
> to EPYC-Turin.
>
> v2: Fixed couple of typos.
> Added Reviewed-by tag from Zhao.
> Rebased on top of 6d00c6f98256 ("Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging")
>
> v3: https://lore.kernel.org/kvm/cover.1729807947.git.babu.moger@amd.com/
> v2: https://lore.kernel.org/kvm/cover.1723068946.git.babu.moger@amd.com/
> v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.moger@amd.com/
>
>
> Babu Moger (5):
> target/i386: Update EPYC CPU model for Cache property, RAS, SVM
> feature bits
> target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM
> feature bits
> target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM
> feature bits
> target/i386: Add feature that indicates WRMSR to BASE reg is
> non-serializing
> target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and
> SVM feature bits
>
> target/i386/cpu.c | 299 +++++++++++++++++++++++++++++++++++++++++++++-
> target/i386/cpu.h | 2 +
> 2 files changed, 300 insertions(+), 1 deletion(-)
>
--
Best regards,
Maksim Davydov