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charset="utf-8" Found that some of the cache properties are not set correctly for EPYC mode= ls. l1d_cache.no_invd_sharing should not be true. l1i_cache.no_invd_sharing should not be true. L2.self_init should be true. L2.inclusive should be true. L3.inclusive should not be true. L3.no_invd_sharing should be true. Fix the cache properties. Also add the missing RAS and SVM features bits on AMD EPYC CPU models. The SVM feature bits are used in nested guests. succor : Software uncorrectable error containment and recovery capability. overflow-recov : MCA overflow recovery support. lbrv : LBR virtualization tsc-scale : MSR based TSC rate control vmcb-clean : VMCB clean bits flushbyasid : Flush by ASID pause-filter : Pause intercept filter pfthreshold : PAUSE filter threshold v-vmsave-vmload : Virtualized VMLOAD and VMSAVE vgif : Virtualized GIF Signed-off-by: Babu Moger --- target/i386/cpu.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 58c96eafea..a632c8030c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2181,6 +2181,60 @@ static CPUCaches epyc_v4_cache_info =3D { }, }; =20 +static CPUCaches epyc_v5_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 64 * KiB, + .line_size =3D 64, + .associativity =3D 4, + .partitions =3D 1, + .sets =3D 256, + .lines_per_tag =3D 1, + .self_init =3D 1, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 512 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 1024, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 8 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .partitions =3D 1, + .sets =3D 8192, + .lines_per_tag =3D 1, + .self_init =3D true, + .no_invd_sharing =3D true, + .complex_indexing =3D false, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; + static const CPUCaches epyc_rome_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { .type =3D DATA_CACHE, @@ -5053,6 +5107,25 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, .cache_info =3D &epyc_v4_cache_info }, + { + .version =3D 5, + .props =3D (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "lbrv", "on" }, + { "tsc-scale", "on" }, + { "vmcb-clean", "on" }, + { "flushbyasid", "on" }, + { "pause-filter", "on" }, + { "pfthreshold", "on" }, + { "v-vmsave-vmload", "on" }, + { "vgif", "on" }, + { "model-id", + "AMD EPYC-v5 Processor" }, + { /* end of list */ } + }, + .cache_info =3D &epyc_v5_cache_info + }, { /* end of list */ } } }, --=20 2.34.1 From nobody Sat Nov 23 17:00:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); 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charset="utf-8" Found that some of the cache properties are not set correctly for EPYC mode= ls. l1d_cache.no_invd_sharing should not be true. l1i_cache.no_invd_sharing should not be true. L2.self_init should be true. L2.inclusive should be true. L3.inclusive should not be true. L3.no_invd_sharing should be true. Fix these cache properties. Also add the missing RAS and SVM features bits on AMD EPYC-Rome. The SVM feature bits are used in nested guests. succor : Software uncorrectable error containment and recovery capability. overflow-recov : MCA overflow recovery support. lbrv : LBR virtualization tsc-scale : MSR based TSC rate control vmcb-clean : VMCB clean bits flushbyasid : Flush by ASID pause-filter : Pause intercept filter pfthreshold : PAUSE filter threshold v-vmsave-vmload : Virtualized VMLOAD and VMSAVE vgif : Virtualized GIF Signed-off-by: Babu Moger --- target/i386/cpu.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a632c8030c..c21b232e75 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2343,6 +2343,60 @@ static const CPUCaches epyc_rome_v3_cache_info =3D { }, }; =20 +static const CPUCaches epyc_rome_v5_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 512 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 1024, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 16 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .partitions =3D 1, + .sets =3D 16384, + .lines_per_tag =3D 1, + .self_init =3D true, + .no_invd_sharing =3D true, + .complex_indexing =3D false, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; + static const CPUCaches epyc_milan_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { .type =3D DATA_CACHE, @@ -5264,6 +5318,25 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ } }, }, + { + .version =3D 5, + .props =3D (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "lbrv", "on" }, + { "tsc-scale", "on" }, + { "vmcb-clean", "on" }, + { "flushbyasid", "on" }, + { "pause-filter", "on" }, + { "pfthreshold", "on" }, + { "v-vmsave-vmload", "on" }, + { "vgif", "on" }, + { "model-id", + "AMD EPYC-Rome-v5 Processor" }, + { /* end of list */ } + }, + .cache_info =3D &epyc_rome_v5_cache_info + }, { /* end of list */ } } }, --=20 2.34.1 From nobody Sat Nov 23 17:00:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); 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charset="utf-8" Found that some of the cache properties are not set correctly for EPYC mode= ls. l1d_cache.no_invd_sharing should not be true. l1i_cache.no_invd_sharing should not be true. L2.self_init should be true. L2.inclusive should be true. L3.inclusive should not be true. L3.no_invd_sharing should be true. Fix these cache properties. Also add the missing RAS and SVM features bits on AMD EPYC-Milan model. The SVM feature bits are used in nested guests. succor : Software uncorrectable error containment and recovery cap= ability. overflow-recov : MCA overflow recovery support. lbrv : LBR virtualization tsc-scale : MSR based TSC rate control vmcb-clean : VMCB clean bits flushbyasid : Flush by ASID pause-filter : Pause intercept filter pfthreshold : PAUSE filter threshold v-vmsave-vmload : Virtualized VMLOAD and VMSAVE vgif : Virtualized GIF Signed-off-by: Babu Moger --- target/i386/cpu.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c21b232e75..4a4e9b81d8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2505,6 +2505,60 @@ static const CPUCaches epyc_milan_v2_cache_info =3D { }, }; =20 +static const CPUCaches epyc_milan_v3_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 512 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 1024, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 32 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .partitions =3D 1, + .sets =3D 32768, + .lines_per_tag =3D 1, + .self_init =3D true, + .no_invd_sharing =3D true, + .complex_indexing =3D false, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; + static const CPUCaches epyc_genoa_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { .type =3D DATA_CACHE, @@ -5412,6 +5466,25 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, .cache_info =3D &epyc_milan_v2_cache_info }, + { + .version =3D 3, + .props =3D (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "lbrv", "on" }, + { "tsc-scale", "on" }, + { "vmcb-clean", "on" }, + { "flushbyasid", "on" }, + { "pause-filter", "on" }, + { "pfthreshold", "on" }, + { "v-vmsave-vmload", "on" }, + { "vgif", "on" }, + { "model-id", + "AMD EPYC-Milan-v3 Processor" }, + { /* end of list */ } + }, + .cache_info =3D &epyc_milan_v3_cache_info + }, { /* end of list */ } } }, --=20 2.34.1 From nobody Sat Nov 23 17:00:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); 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charset="utf-8" Add the CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or MSR_KERNEL_GS_BASE is non-serializing. CPUID_Fn80000021_EAX Bit Feature description 1 FsGsKernelGsBaseNonSerializing. WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing. Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/= programmer-references/57238.zip Signed-off-by: Babu Moger --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4a4e9b81d8..107ecd2bde 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1235,7 +1235,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { [FEAT_8000_0021_EAX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { - "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, + "no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializi= ng", NULL, NULL, NULL, "null-sel-clr-base", NULL, "auto-ibrs", NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b65eedb617..12dafc9b32 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1032,6 +1032,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); =20 /* Processor ignores nested data breakpoints */ #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0) +/* WRMSR to FS_BASE, GS_BASE, or KERNEL_GS_BASE is non-serializing */ +#define CPUID_8000_0021_EAX_FS_GS_BASE_NS (1U << 1) /* LFENCE is always serializing */ #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) /* Null Selector Clears Base */ --=20 2.34.1 From nobody Sat Nov 23 17:00:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Found that some of the cache properties are not set correctly for EPYC mode= ls. l1d_cache.no_invd_sharing should not be true. l1i_cache.no_invd_sharing should not be true. L2.self_init should be true. L2.inclusive should be true. L3.inclusive should not be true. L3.no_invd_sharing should be true. Fix these cache properties. Also add the missing RAS and SVM features bits on AMD EPYC-Genoa model. The SVM feature bits are used in nested guests. perfmon-v2 : Allow guests to make use of the PerfMonV2 features. succor : Software uncorrectable error containment and recovery capa= bility. overflow-recov : MCA overflow recovery support. lbrv : LBR virtualization tsc-scale : MSR based TSC rate control vmcb-clean : VMCB clean bits flushbyasid : Flush by ASID pause-filter : Pause intercept filter pfthreshold : PAUSE filter threshold v-vmsave-vmload: Virtualized VMLOAD and VMSAVE vgif : Virtualized GIF fs-gs-base-ns : WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing The feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- target/i386/cpu.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 107ecd2bde..1d241fcd13 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2613,6 +2613,59 @@ static const CPUCaches epyc_genoa_cache_info =3D { }, }; =20 +static const CPUCaches epyc_genoa_v2_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 32 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 64, + .lines_per_tag =3D 1, + .self_init =3D 1, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 1 * MiB, + .line_size =3D 64, + .associativity =3D 8, + .partitions =3D 1, + .sets =3D 2048, + .lines_per_tag =3D 1, + .self_init =3D true, + .inclusive =3D true, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 32 * MiB, + .line_size =3D 64, + .associativity =3D 16, + .partitions =3D 1, + .sets =3D 32768, + .lines_per_tag =3D 1, + .self_init =3D true, + .no_invd_sharing =3D true, + .complex_indexing =3D false, + .share_level =3D CPU_TOPOLOGY_LEVEL_DIE, + }, +}; /* The following VMX features are not supported by KVM and are left out in= the * CPU definitions: * @@ -5559,6 +5612,31 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { .xlevel =3D 0x80000022, .model_id =3D "AMD EPYC-Genoa Processor", .cache_info =3D &epyc_genoa_cache_info, + .versions =3D (X86CPUVersionDefinition[]) { + { .version =3D 1 }, + { + .version =3D 2, + .props =3D (PropValue[]) { + { "overflow-recov", "on" }, + { "succor", "on" }, + { "lbrv", "on" }, + { "tsc-scale", "on" }, + { "vmcb-clean", "on" }, + { "flushbyasid", "on" }, + { "pause-filter", "on" }, + { "pfthreshold", "on" }, + { "v-vmsave-vmload", "on" }, + { "vgif", "on" }, + { "fs-gs-base-ns", "on" }, + { "perfmon-v2", "on" }, + { "model-id", + "AMD EPYC-Genoa-v2 Processor" }, + { /* end of list */ } + }, + .cache_info =3D &epyc_genoa_v2_cache_info + }, + { /* end of list */ } + } }, }; =20 --=20 2.34.1