[v1] RISC-V: Populate mtval and stval

[PATCH v1 0/2] RISC-V: Populate mtval and stval

Alistair Francis posted 2 patches 2 years, 7 months ago

Diff against v1 v1 v2 v4
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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1630624983.git.alistair.francis@wdc.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Bin Meng <bin.meng@windriver.com>, Alistair Francis <alistair.francis@wdc.com>

There is a newer version of this series

target/riscv/cpu.h        |  6 +++++-
target/riscv/cpu.c        |  6 +++++-
target/riscv/cpu_helper.c |  9 +++++++++
target/riscv/translate.c  | 33 +++++++++++++++++++--------------
4 files changed, 38 insertions(+), 16 deletions(-)

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[PATCH v1 0/2] RISC-V: Populate mtval and stval

Posted by Alistair Francis 2 years, 7 months ago

From: Alistair Francis <alistair.francis@wdc.com>


Populate mtval and stval when taking an illegal instruction exception if
the features are set for the CPU.



Alistair Francis (2):
  target/riscv: Implement the stval/mtval illegal instruction
  target/riscv: Set mtval and stval support

 target/riscv/cpu.h        |  6 +++++-
 target/riscv/cpu.c        |  6 +++++-
 target/riscv/cpu_helper.c |  9 +++++++++
 target/riscv/translate.c  | 33 +++++++++++++++++++--------------
 4 files changed, 38 insertions(+), 16 deletions(-)

-- 
2.31.1