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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630625026; x=1633217027; bh=DWTb7faK5lXbqRqwl4 F0MWI3aMOeLqgKbwb65Kqcza8=; b=PLoroVOeGOKty1eKu6bOCyIwzsKD+GFxte PlTzuWIE56HeM3weUrLWpVUE7PQkW/iortalccZmMLFBQDhRa4xDKtl42H1UAuSc YHgvxuPFYlZaWtVTfyHCt7Yhjjg6wFpIJnRjdFxyYGiKiP6z5ILWElXBBzAoobtG /5er7i8SfEF5M0OqjKr3cFTwZUSMXfrmWgmIZ6i2NVXu3M01Ne0U94aYzELAh7fD NisTA7dw/8EZmiC+bMm7OBTm3BukapcnqBC8xxCJjZsHabEgFuw+2juubVTieV8L sQX1NUOy/h4HyfR8JR8dQRHblIRlwJphfHxmOFTY6X37D4M2P89Q== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction Date: Fri, 3 Sep 2021 09:23:35 +1000 Message-Id: <289f8d59cf883fec5764cb0cea8da4430b6fd6da.1630624983.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=8724dbd3c=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630625277862100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers based on the CPU feature. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 ++++- target/riscv/cpu_helper.c | 9 +++++++++ target/riscv/translate.c | 33 +++++++++++++++++++-------------- 3 files changed, 32 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..6d41a16ae3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -77,7 +77,8 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_MISA + RISCV_FEATURE_MISA, + RISCV_FEATURE_MTVAL_INST, }; =20 #define PRIV_VERSION_1_10_0 0x00011000 @@ -130,6 +131,8 @@ struct CPURISCVState { target_ulong frm; =20 target_ulong badaddr; + target_ulong bins; + target_ulong guest_phys_fault_addr; =20 target_ulong priv_ver; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 968cb8046f..42edd71c1e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -967,6 +967,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) write_tval =3D true; tval =3D env->badaddr; break; + case RISCV_EXCP_ILLEGAL_INST: + if (riscv_feature(env, RISCV_FEATURE_MTVAL_INST)) { + /* The stval/mtval register can optionally also be used to + * return the faulting instruction bits on an illegal + * instruction exception. + */ + tval =3D env->bins; + } + break; default: break; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e356fc6c46..4221d8e2d5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -173,8 +173,27 @@ static void lookup_and_goto_ptr(DisasContext *ctx) } } =20 +/* + * Wrappers for getting reg values. + * + * The $zero register does not have cpu_gpr[0] allocated -- we supply the + * constant zero as a source, and an uninitialized sink as destination. + * + * Further, we may provide an extension for word operations. + */ +static TCGv temp_new(DisasContext *ctx) +{ + assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); + return ctx->temp[ctx->ntemp++] =3D tcg_temp_new(); +} + static void gen_exception_illegal(DisasContext *ctx) { + TCGv tmp =3D temp_new(ctx); + + tcg_gen_movi_tl(tmp, ctx->opcode); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, bins)); + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); } =20 @@ -195,20 +214,6 @@ static void gen_goto_tb(DisasContext *ctx, int n, targ= et_ulong dest) } } =20 -/* - * Wrappers for getting reg values. - * - * The $zero register does not have cpu_gpr[0] allocated -- we supply the - * constant zero as a source, and an uninitialized sink as destination. - * - * Further, we may provide an extension for word operations. - */ -static TCGv temp_new(DisasContext *ctx) -{ - assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); - return ctx->temp[ctx->ntemp++] =3D tcg_temp_new(); -} - static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) { TCGv t; --=20 2.31.1 From nobody Sun May 5 01:29:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1630625038; x=1633217039; bh=fX+D9NkC99giVZdE2Z 7T5c65nGBj+I1+KnYy8YTXeO0=; b=k+2/NpwBSHeEPRttmzSUXqID0HfWo6S+uR qfuCc3OHUvKHtkWBtA8y3KB/Jen9k26a1lVrIHXOm20ZSfd64Bzm2WeUgmr5V6gQ jaQmd6Wg0aQlBmizCYC9PoKRlMHGPni8NRqQPjmS3HGvYYruCM0w99OTWCuruasO MdrvWEG/DPrOzEz6d6AxUajp/zEdqlNwUHPOXmsd/IyzIEvvS6gMhIlHbrkzv9HX paC2s5OX+wiUQlbEZ9HC00Si5NvoVdJY2VFsZMU84LuBVIW41WVNGrmpdKDjaQvk Nb640oFgomvhgaHo4R2nrDMnaOoUueAf4599ehpM/Kl0xDU69Klg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH v1 2/2] target/riscv: Set mtval and stval support Date: Fri, 3 Sep 2021 09:23:48 +1000 Message-Id: <968ed1af9002f5f9f42f9efe8a5db5a1ed830a09.1630624983.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=8724dbd3c=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1630625167269100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6d41a16ae3..64ebb593fb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -309,6 +309,7 @@ struct RISCVCPU { bool mmu; bool pmp; bool epmp; + bool mtval_inst; uint64_t resetvec; } cfg; }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a2b03d579..8b77526c79 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -437,6 +437,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 + if (cpu->cfg.mtval_inst) { + set_feature(env, RISCV_FEATURE_MTVAL_INST); + } + set_resetvec(env, cpu->cfg.resetvec); =20 /* If only XLEN is set for misa, then set misa from properties */ @@ -600,7 +604,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), - + DEFINE_PROP_BOOL("mtval_inst", RISCVCPU, cfg.mtval_inst, true), DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), }; --=20 2.31.1