OpenTitan is an open source silicon Root of Trust (RoT) project. This
series adds initial support for the OpenTitan machine to QEMU.

This series add the Ibex CPU to the QEMU RISC-V target. It then adds the
OpenTitan machine, the Ibex UART and the Ibex PLIC.

The UART has been tested sending and receiving data.

With this series QEMU can boot the OpenTitan ROM, Tock OS and a Tock
userspace app.

The Ibex PLIC is similar to the RISC-V PLIC (and is based on the QEMU
implementation) with some differences. The hope is that the Ibex PLIC
will converge to follow the RISC-V spec. As that happens I want to
update the QEMU Ibex PLIC and hopefully eventually replace the current
PLIC as the implementation is a little overlay complex.

For more details on OpenTitan, see here: https://docs.opentitan.org/

v2:
 - Rebase on master
 - Get uart receive working

Alistair Francis (9):
  riscv/boot: Add a missing header include
  target/riscv: Don't overwrite the reset vector
  target/riscv: Add the lowRISC Ibex CPU
  riscv: Initial commit of OpenTitan machine
  hw/char: Initial commit of Ibex UART
  hw/intc: Initial commit of lowRISC Ibex PLIC
  riscv/opentitan: Connect the PLIC device
  riscv/opentitan: Connect the UART device
  target/riscv: Use a smaller guess size for no-MMU PMP

 MAINTAINERS                         |  14 +
 default-configs/riscv32-softmmu.mak |   1 +
 default-configs/riscv64-softmmu.mak |  11 +-
 hw/char/Makefile.objs               |   1 +
 hw/char/ibex_uart.c                 | 490 ++++++++++++++++++++++++++++
 hw/intc/Makefile.objs               |   1 +
 hw/intc/ibex_plic.c                 | 261 +++++++++++++++
 hw/riscv/Kconfig                    |   9 +
 hw/riscv/Makefile.objs              |   1 +
 hw/riscv/opentitan.c                | 204 ++++++++++++
 include/hw/char/ibex_uart.h         | 110 +++++++
 include/hw/intc/ibex_plic.h         |  63 ++++
 include/hw/riscv/boot.h             |   1 +
 include/hw/riscv/opentitan.h        |  79 +++++
 target/riscv/cpu.c                  |  30 +-
 target/riscv/cpu.h                  |   1 +
 target/riscv/pmp.c                  |  19 +-
 17 files changed, 1281 insertions(+), 15 deletions(-)
 create mode 100644 hw/char/ibex_uart.c
 create mode 100644 hw/intc/ibex_plic.c
 create mode 100644 hw/riscv/opentitan.c
 create mode 100644 include/hw/char/ibex_uart.h
 create mode 100644 include/hw/intc/ibex_plic.h
 create mode 100644 include/hw/riscv/opentitan.h

-- 
2.26.2

On Thu, May 7, 2020 at 12:21 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> OpenTitan is an open source silicon Root of Trust (RoT) project. This
> series adds initial support for the OpenTitan machine to QEMU.
>
> This series add the Ibex CPU to the QEMU RISC-V target. It then adds the
> OpenTitan machine, the Ibex UART and the Ibex PLIC.
>
> The UART has been tested sending and receiving data.
>
> With this series QEMU can boot the OpenTitan ROM, Tock OS and a Tock
> userspace app.
>
> The Ibex PLIC is similar to the RISC-V PLIC (and is based on the QEMU
> implementation) with some differences. The hope is that the Ibex PLIC
> will converge to follow the RISC-V spec. As that happens I want to
> update the QEMU Ibex PLIC and hopefully eventually replace the current
> PLIC as the implementation is a little overlay complex.
>
> For more details on OpenTitan, see here: https://docs.opentitan.org/

Ping!

+ Some people who might be able to review this series (or at least ack).

I'll give it another week and if I don't hear anything I'll merge it.

Alistair

>
> v2:
>  - Rebase on master
>  - Get uart receive working
>
> Alistair Francis (9):
>   riscv/boot: Add a missing header include
>   target/riscv: Don't overwrite the reset vector
>   target/riscv: Add the lowRISC Ibex CPU
>   riscv: Initial commit of OpenTitan machine
>   hw/char: Initial commit of Ibex UART
>   hw/intc: Initial commit of lowRISC Ibex PLIC
>   riscv/opentitan: Connect the PLIC device
>   riscv/opentitan: Connect the UART device
>   target/riscv: Use a smaller guess size for no-MMU PMP
>
>  MAINTAINERS                         |  14 +
>  default-configs/riscv32-softmmu.mak |   1 +
>  default-configs/riscv64-softmmu.mak |  11 +-
>  hw/char/Makefile.objs               |   1 +
>  hw/char/ibex_uart.c                 | 490 ++++++++++++++++++++++++++++
>  hw/intc/Makefile.objs               |   1 +
>  hw/intc/ibex_plic.c                 | 261 +++++++++++++++
>  hw/riscv/Kconfig                    |   9 +
>  hw/riscv/Makefile.objs              |   1 +
>  hw/riscv/opentitan.c                | 204 ++++++++++++
>  include/hw/char/ibex_uart.h         | 110 +++++++
>  include/hw/intc/ibex_plic.h         |  63 ++++
>  include/hw/riscv/boot.h             |   1 +
>  include/hw/riscv/opentitan.h        |  79 +++++
>  target/riscv/cpu.c                  |  30 +-
>  target/riscv/cpu.h                  |   1 +
>  target/riscv/pmp.c                  |  19 +-
>  17 files changed, 1281 insertions(+), 15 deletions(-)
>  create mode 100644 hw/char/ibex_uart.c
>  create mode 100644 hw/intc/ibex_plic.c
>  create mode 100644 hw/riscv/opentitan.c
>  create mode 100644 include/hw/char/ibex_uart.h
>  create mode 100644 include/hw/intc/ibex_plic.h
>  create mode 100644 include/hw/riscv/opentitan.h
>
> --
> 2.26.2
>