[PATCH v6 0/6] RISC-V Add the OpenTitan Machine

Alistair Francis posted 6 patches 3 years, 10 months ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1591827110.git.alistair.francis@wdc.com
Maintainers: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, Alistair Francis <Alistair.Francis@wdc.com>
include/hw/char/ibex_uart.h  | 110 ++++++++
include/hw/intc/ibex_plic.h  |  63 +++++
include/hw/riscv/opentitan.h |  16 ++
hw/char/ibex_uart.c          | 492 +++++++++++++++++++++++++++++++++++
hw/intc/ibex_plic.c          | 261 +++++++++++++++++++
hw/riscv/opentitan.c         |  45 +++-
target/riscv/pmp.c           |  14 +-
MAINTAINERS                  |   4 +
hw/char/Makefile.objs        |   1 +
hw/intc/Makefile.objs        |   1 +
hw/riscv/Kconfig             |   4 +
11 files changed, 1001 insertions(+), 10 deletions(-)
create mode 100644 include/hw/char/ibex_uart.h
create mode 100644 include/hw/intc/ibex_plic.h
create mode 100644 hw/char/ibex_uart.c
create mode 100644 hw/intc/ibex_plic.c
[PATCH v6 0/6] RISC-V Add the OpenTitan Machine
Posted by Alistair Francis 3 years, 10 months ago
OpenTitan is an open source silicon Root of Trust (RoT) project. This
series adds initial support for the OpenTitan machine to QEMU.

This series add the Ibex CPU to the QEMU RISC-V target. It then adds the
OpenTitan machine, the Ibex UART and the Ibex PLIC.

The UART has been tested sending and receiving data.

With this series QEMU can boot the OpenTitan ROM, Tock OS and a Tock
userspace app.

The Ibex PLIC is similar to the RISC-V PLIC (and is based on the QEMU
implementation) with some differences. The hope is that the Ibex PLIC
will converge to follow the RISC-V spec. As that happens I want to
update the QEMU Ibex PLIC and hopefully eventually replace the current
PLIC as the implementation is a little overlay complex.

For more details on OpenTitan, see here: https://docs.opentitan.org/

v6:
 - Rebase on master (some patches applied)
 - Fix the ROM address
v5:
 - Add some of the missing unimplemented devices
 - Don't set PMP feature in init() function
v4:
 - Don't set the reset vector in realise
 - Fix a bug where the MMU is always enabled
 - Fixup the PMP/MMU size logic
v3:
 - Small fixes pointed out in review
v2:
 - Rebase on master
 - Get uart receive working



Alistair Francis (6):
  riscv/opentitan: Fix the ROM size
  hw/char: Initial commit of Ibex UART
  hw/intc: Initial commit of lowRISC Ibex PLIC
  riscv/opentitan: Connect the PLIC device
  riscv/opentitan: Connect the UART device
  target/riscv: Use a smaller guess size for no-MMU PMP

 include/hw/char/ibex_uart.h  | 110 ++++++++
 include/hw/intc/ibex_plic.h  |  63 +++++
 include/hw/riscv/opentitan.h |  16 ++
 hw/char/ibex_uart.c          | 492 +++++++++++++++++++++++++++++++++++
 hw/intc/ibex_plic.c          | 261 +++++++++++++++++++
 hw/riscv/opentitan.c         |  45 +++-
 target/riscv/pmp.c           |  14 +-
 MAINTAINERS                  |   4 +
 hw/char/Makefile.objs        |   1 +
 hw/intc/Makefile.objs        |   1 +
 hw/riscv/Kconfig             |   4 +
 11 files changed, 1001 insertions(+), 10 deletions(-)
 create mode 100644 include/hw/char/ibex_uart.h
 create mode 100644 include/hw/intc/ibex_plic.h
 create mode 100644 hw/char/ibex_uart.c
 create mode 100644 hw/intc/ibex_plic.c

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2.26.2