From: "Zhang, Qi" <qi1.zhang@intel.com>

spilt the reserved fields arrays and remove TM field from reserved 
 bits

Changelog V1:
 add descriptons
Changelog V2:
 refine

Zhang, Qi (2):
  intel_iommu: split the resevred fields arrays into two ones
  intel_iommu: TM field should not be in reserved bits

 hw/i386/intel_iommu.c          | 35 ++++++++++++++++++++--------------
 hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
 2 files changed, 34 insertions(+), 18 deletions(-)

-- 
2.20.1

On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zhang@intel.com wrote:
> From: "Zhang, Qi" <qi1.zhang@intel.com>
> 
> spilt the reserved fields arrays and remove TM field from reserved 
>  bits

Looks good to me.
Also Cc Peter Xu.
Also I wonder - do we need to version this change
with the machine type? Peter what's your take?
Also, Peter, how about we create a MAINTAINERS entry for IOMMUs
and add everyone involved, this way people will
remember to CC you?

> Changelog V1:
>  add descriptons
> Changelog V2:
>  refine
> 
> Zhang, Qi (2):
>   intel_iommu: split the resevred fields arrays into two ones
>   intel_iommu: TM field should not be in reserved bits
> 
>  hw/i386/intel_iommu.c          | 35 ++++++++++++++++++++--------------
>  hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
>  2 files changed, 34 insertions(+), 18 deletions(-)
> 
> -- 
> 2.20.1

On Tue, Nov 19, 2019 at 06:05:11AM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zhang@intel.com wrote:
> > From: "Zhang, Qi" <qi1.zhang@intel.com>
> > 
> > spilt the reserved fields arrays and remove TM field from reserved 
> >  bits
> 
> Looks good to me.
> Also Cc Peter Xu.
> Also I wonder - do we need to version this change
> with the machine type? Peter what's your take?

It should be a bugfix to me.  With the patchset we check even less
reserved bits, then imho it shouldn't break any existing good users.
So we can probably skip versioning this change.

> Also, Peter, how about we create a MAINTAINERS entry for IOMMUs
> and add everyone involved, this way people will
> remember to CC you?

Sure, I'll be fine with either way.

Thanks,

-- 
Peter Xu

On Tue, Nov 19, 2019 at 11:21:10AM -0500, Peter Xu wrote:
> On Tue, Nov 19, 2019 at 06:05:11AM -0500, Michael S. Tsirkin wrote:
> > On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zhang@intel.com wrote:
> > > From: "Zhang, Qi" <qi1.zhang@intel.com>
> > > 
> > > spilt the reserved fields arrays and remove TM field from reserved 
> > >  bits
> > 
> > Looks good to me.
> > Also Cc Peter Xu.
> > Also I wonder - do we need to version this change
> > with the machine type? Peter what's your take?
> 
> It should be a bugfix to me.  With the patchset we check even less
> reserved bits, then imho it shouldn't break any existing good users.
> So we can probably skip versioning this change.


Can you ack this patch then?

> > Also, Peter, how about we create a MAINTAINERS entry for IOMMUs
> > and add everyone involved, this way people will
> > remember to CC you?
> 
> Sure, I'll be fine with either way.
> 
> Thanks,
> 
> -- 
> Peter Xu

On Tue, Nov 19, 2019 at 11:39:04AM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 19, 2019 at 11:21:10AM -0500, Peter Xu wrote:
> > On Tue, Nov 19, 2019 at 06:05:11AM -0500, Michael S. Tsirkin wrote:
> > > On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zhang@intel.com wrote:
> > > > From: "Zhang, Qi" <qi1.zhang@intel.com>
> > > > 
> > > > spilt the reserved fields arrays and remove TM field from reserved 
> > > >  bits
> > > 
> > > Looks good to me.
> > > Also Cc Peter Xu.
> > > Also I wonder - do we need to version this change
> > > with the machine type? Peter what's your take?
> > 
> > It should be a bugfix to me.  With the patchset we check even less
> > reserved bits, then imho it shouldn't break any existing good users.
> > So we can probably skip versioning this change.
> 
> 
> Can you ack this patch then?

I've commented.  I'll wait for a reply from Qi or a new version before
I ack it.  Thanks,

-- 
Peter Xu