From nobody Sat May 4 21:02:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1574137704; cv=none; d=zoho.com; s=zohoarc; b=R84xYahngBgg48q/0NAcHETG5aY8fIFgGVZHQBF8cGweQeEqjnrdcf4qFwRwX+wFswkVwVApCEYOcCtNibfhjiygx3HlPpHT1qmxP8dFToi7Va6Wa1PEpKNZTCQn9StcLMuENDGZzU5Ao+VK4Kwij5elMbdmbTyq60FdmVyhA4Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1574137704; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MEqebdnUURZi8OjiWLC0WjWYJusnpH4ZO+sWzV+Oxx0=; b=WYcDhfc9ZXvH01vMbgoAf1Ho9PMeWLz1j6N7yXomVuPvaSiihYjIQLVq72dJGRwfLfGFw0LR46VUUs7W4v6pZZtrOq8/MwLuLQlkexzWe7ofXD+RE6NL4F3ISVzo6ULqx1/aC4/KocC3L6B5ACKihnvIcor3pwK/L+UVybv8VUU= ARC-Authentication-Results: i=1; mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574137704101145.12395064926113; Mon, 18 Nov 2019 20:28:24 -0800 (PST) Received: from localhost ([::1]:41716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iWv7e-00074W-RA for importer@patchew.org; Mon, 18 Nov 2019 23:28:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49236) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iWv6i-0006B4-PX for qemu-devel@nongnu.org; Mon, 18 Nov 2019 23:27:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iWv6h-0002fQ-6u for qemu-devel@nongnu.org; Mon, 18 Nov 2019 23:27:16 -0500 Received: from mga05.intel.com ([192.55.52.43]:34956) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iWv6g-0002bU-Vv for qemu-devel@nongnu.org; Mon, 18 Nov 2019 23:27:15 -0500 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Nov 2019 20:27:08 -0800 Received: from a23004-02.sh.intel.com ([10.239.9.129]) by orsmga003.jf.intel.com with ESMTP; 18 Nov 2019 20:27:06 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,322,1569308400"; d="scan'208";a="209068488" From: qi1.zhang@intel.com To: qemu-devel@nongnu.org Subject: [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones Date: Tue, 19 Nov 2019 20:27:01 +0800 Message-Id: X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qi1.zhang@intel.com, ehabkost@redhat.com, mst@redhat.com, pbonzini@redhat.com, yadong.qi@intel.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: "Zhang, Qi" Signed-off-by: Zhang, Qi --- hw/i386/intel_iommu.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f1de8fdb75..a118efaeaf 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -910,18 +910,19 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, =20 /* * Rsvd field masks for spte: - * Index [1] to [4] 4k pages - * Index [5] to [8] large pages + * vtd_spte_rsvd 4k pages + * vtd_spte_rsvd_large large pages */ -static uint64_t vtd_paging_entry_rsvd_field[9]; +static uint64_t vtd_spte_rsvd[5]; +static uint64_t vtd_spte_rsvd_large[5]; =20 static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level) { if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) { /* Maybe large page */ - return slpte & vtd_paging_entry_rsvd_field[level + 4]; + return slpte & vtd_spte_rsvd_large[level]; } else { - return slpte & vtd_paging_entry_rsvd_field[level]; + return slpte & vtd_spte_rsvd[level]; } } =20 @@ -3547,15 +3548,17 @@ static void vtd_init(IntelIOMMUState *s) /* * Rsvd field masks for spte */ - vtd_paging_entry_rsvd_field[0] =3D ~0ULL; - vtd_paging_entry_rsvd_field[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bi= ts); - vtd_paging_entry_rsvd_field[5] =3D VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_b= its); - vtd_paging_entry_rsvd_field[6] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_b= its); - vtd_paging_entry_rsvd_field[7] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_b= its); - vtd_paging_entry_rsvd_field[8] =3D VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_b= its); + vtd_spte_rsvd[0] =3D ~0ULL; + vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); + + vtd_spte_rsvd_large[0] =3D ~0ULL; + vtd_spte_rsvd_large[1] =3D VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[4] =3D VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits); =20 if (x86_iommu_ir_supported(x86_iommu)) { s->ecap |=3D VTD_ECAP_IR | VTD_ECAP_MHMV; --=20 2.20.1 From nobody Sat May 4 21:02:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1574137785898159.26537575476107; Mon, 18 Nov 2019 20:29:45 -0800 (PST) Received: from localhost ([::1]:41734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iWv96-0000ZQ-Mx for importer@patchew.org; Mon, 18 Nov 2019 23:29:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49320) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iWv7k-0007fL-RQ for qemu-devel@nongnu.org; Mon, 18 Nov 2019 23:28:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iWv7j-00035R-Kt for qemu-devel@nongnu.org; Mon, 18 Nov 2019 23:28:20 -0500 Received: from mga06.intel.com ([134.134.136.31]:38422) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iWv7j-00034I-Dd for qemu-devel@nongnu.org; Mon, 18 Nov 2019 23:28:19 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Nov 2019 20:28:19 -0800 Received: from a23004-02.sh.intel.com ([10.239.9.129]) by fmsmga001.fm.intel.com with ESMTP; 18 Nov 2019 20:28:17 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,322,1569308400"; d="scan'208";a="215444130" From: qi1.zhang@intel.com To: qemu-devel@nongnu.org Subject: [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits Date: Tue, 19 Nov 2019 20:28:14 +0800 Message-Id: <758ae02ef3a36b2790a7e61018bb55379ceeb450.1570503331.git.qi1.zhang@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 134.134.136.31 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qi1.zhang@intel.com, ehabkost@redhat.com, mst@redhat.com, pbonzini@redhat.com, yadong.qi@intel.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: "Zhang, Qi" When dt is supported, TM field should not be Reserved(0). Refer to VT-d Spec 9.8 Signed-off-by: Zhang, Qi Signed-off-by: Qi, Yadong --- hw/i386/intel_iommu.c | 12 ++++++++---- hw/i386/intel_iommu_internal.h | 17 +++++++++++++---- 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a118efaeaf..d62604ece3 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s) * Rsvd field masks for spte */ vtd_spte_rsvd[0] =3D ~0ULL; - vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd[1] =3D VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, + x86_iommu->dt_supported); vtd_spte_rsvd[2] =3D VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); vtd_spte_rsvd[3] =3D VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); vtd_spte_rsvd[4] =3D VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); =20 vtd_spte_rsvd_large[0] =3D ~0ULL; - vtd_spte_rsvd_large[1] =3D VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits); - vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits); + vtd_spte_rsvd_large[1] =3D VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits, + x86_iommu->dt_sup= ported); + vtd_spte_rsvd_large[2] =3D VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, + x86_iommu->dt_sup= ported); + vtd_spte_rsvd_large[3] =3D VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, + x86_iommu->dt_sup= ported); vtd_spte_rsvd_large[4] =3D VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits); =20 if (x86_iommu_ir_supported(x86_iommu)) { diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index c1235a7063..3a839a8925 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 =20 /* Rsvd field masks for spte */ -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \ +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \ + dt_supported ? \ + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) @@ -395,11 +397,17 @@ typedef union VTDInvDesc VTDInvDesc; (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) -#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \ +#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \ + dt_supported ? \ + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \ +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \ + dt_supported ? \ + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) := \ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \ +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \ + dt_supported ? \ + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM))= : \ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) #define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \ (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) @@ -506,5 +514,6 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SL_W (1ULL << 1) #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(= aw)) #define VTD_SL_IGN_COM 0xbff0000000000000ULL +#define VTD_SL_TM (1ULL << 62) =20 #endif --=20 2.20.1