[Qemu-devel] [PATCH v2 0/6] Connect a PCIe host and graphics support to RISC-V

Alistair Francis posted 6 patches 11 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/cover.1531182400.git.alistair.francis@wdc.com
Test checkpatch passed
Test docker-mingw@fedora passed
Test docker-quick@centos7 passed
default-configs/riscv32-softmmu.mak |  7 ++++
default-configs/riscv64-softmmu.mak |  9 ++++
hw/riscv/sifive_u.c                 | 64 ++++++++++++++++++++++++++++
hw/riscv/virt.c                     | 65 ++++++++++++++++++++++++++++-
include/hw/riscv/sifive_u.h         |  4 +-
include/hw/riscv/virt.h             |  6 ++-
6 files changed, 151 insertions(+), 4 deletions(-)

[Qemu-devel] [PATCH v2 0/6] Connect a PCIe host and graphics support to RISC-V

Posted by Alistair Francis 11 weeks ago
V2:
 - Use the gpex PCIe host for virt
 - Add support for SiFive U PCIe


Alistair Francis (6):
  hw/riscv/virtio: Set the soc device tree node as a simple-bus
  hw/riscv/virt: Increase the number of interrupts
  hw/riscv/virt: Connect the gpex PCIe
  hw/riscv/virt: Connect a VGA PCIe device
  hw/riscv/sifive_u: Connect the Xilinx PCIe
  riscv64-softmmu.mak: Build Virtio Block support

 default-configs/riscv32-softmmu.mak |  7 ++++
 default-configs/riscv64-softmmu.mak |  9 ++++
 hw/riscv/sifive_u.c                 | 64 ++++++++++++++++++++++++++++
 hw/riscv/virt.c                     | 65 ++++++++++++++++++++++++++++-
 include/hw/riscv/sifive_u.h         |  4 +-
 include/hw/riscv/virt.h             |  6 ++-
 6 files changed, 151 insertions(+), 4 deletions(-)

-- 
2.17.1