hw/riscv/riscv-iommu.c: always send MRIF notice MSI

[PATCH] hw/riscv/riscv-iommu.c: always send MRIF notice MSI

Posted by Flavien Solt 1 week, 4 days ago

The AIA specification requires an IOMMU to send the configured notice MSI after storing an MSI to an MRIF even when the corresponding interrupt-enable bit is clear. The problem is that riscv_iommu_msi_write() currently reads the MRIF interrupt-enable doubleword and suppresses the notice MSI when the bit is zero.

This patch removes the enable-word read and always sends the notice MSI after updating the MRIF pending bit.

Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
Cc: qemu-stable@nongnu.org
Signed-off-by: Flavien Solt <flavien@nus.edu.sg>
---
Tested with a deterministic qtest using qemu-system-riscv64.

After this patch we get:
  enable=0: pending=0x20 notice=0x12d
  enable=1: pending=0x20 notice=0x12d

 hw/riscv/riscv-iommu.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index f6865d1..9627cab 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -788,20 +788,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState *s,
         goto err;
     }

-    /* Get MRIF enable bits */
-    addr = addr + sizeof(intn);
-    res = dma_memory_read(s->target_as, addr, &intn, sizeof(intn), attrs);
-    if (res != MEMTX_OK) {
-        cause = RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT;
-        goto err;
-    }
-
-    if (!(intn & data)) {
-        /* notification disabled, MRIF update completed. */
-        return MEMTX_OK;
-    }
-
-    /* Send notification message */
     addr = PPN_PHYS(get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NPPN));
     n190 = get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID) |
           (get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID_MSB) << 10);

base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
--
2.54.0


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Re: [PATCH] hw/riscv/riscv-iommu.c: always send MRIF notice MSI

Posted by Andrew Jones 1 day, 10 hours ago

On Tue, Jul 14, 2026 at 06:01:12AM +0000, Flavien Solt wrote:
> The AIA specification requires an IOMMU to send the configured notice MSI after storing an MSI to an MRIF even when the corresponding interrupt-enable bit is clear. The problem is that riscv_iommu_msi_write() currently reads the MRIF interrupt-enable doubleword and suppresses the notice MSI when the bit is zero.
> 
> This patch removes the enable-word read and always sends the notice MSI after updating the MRIF pending bit.

I'm not sure how these long lines will ultimately look when committed. I
suggest manually wrapping commit message lines.

> 
> Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Flavien Solt <flavien@nus.edu.sg>
> ---
> Tested with a deterministic qtest using qemu-system-riscv64.

Are these tests available somewhere?

> 
> After this patch we get:
>   enable=0: pending=0x20 notice=0x12d
>   enable=1: pending=0x20 notice=0x12d
> 
>  hw/riscv/riscv-iommu.c | 15 +--------------
>  1 file changed, 1 insertion(+), 14 deletions(-)
> 
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index f6865d1..9627cab 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -788,20 +788,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState *s,
>          goto err;
>      }
> 
> -    /* Get MRIF enable bits */
> -    addr = addr + sizeof(intn);
> -    res = dma_memory_read(s->target_as, addr, &intn, sizeof(intn), attrs);
> -    if (res != MEMTX_OK) {
> -        cause = RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT;
> -        goto err;
> -    }
> -
> -    if (!(intn & data)) {
> -        /* notification disabled, MRIF update completed. */
> -        return MEMTX_OK;
> -    }
> -
> -    /* Send notification message */

We should keep this comment.

>      addr = PPN_PHYS(get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NPPN));
>      n190 = get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID) |
>            (get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID_MSB) << 10);
> 
> base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
> --
> 2.54.0
>

Besides the line wrapping and the unnecessary removal of a comment,
this looks good.

Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com>

Thanks,
drew

Re: [PATCH] hw/riscv/riscv-iommu.c: always send MRIF notice MSI

Posted by Daniel Henrique Barboza 2 days, 1 hour ago


On 7/14/2026 3:01 AM, Flavien Solt wrote:
> The AIA specification requires an IOMMU to send the configured notice MSI after storing an MSI to an MRIF even when the corresponding interrupt-enable bit is clear. The problem is that riscv_iommu_msi_write() currently reads the MRIF interrupt-enable doubleword and suppresses the notice MSI when the bit is zero.
> 
> This patch removes the enable-word read and always sends the notice MSI after updating the MRIF pending bit.
> 
> Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Flavien Solt <flavien@nus.edu.sg>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

> Tested with a deterministic qtest using qemu-system-riscv64.
> 
> After this patch we get:
>    enable=0: pending=0x20 notice=0x12d
>    enable=1: pending=0x20 notice=0x12d
> 
>   hw/riscv/riscv-iommu.c | 15 +--------------
>   1 file changed, 1 insertion(+), 14 deletions(-)
> 
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index f6865d1..9627cab 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -788,20 +788,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState *s,
>           goto err;
>       }
> 
> -    /* Get MRIF enable bits */
> -    addr = addr + sizeof(intn);
> -    res = dma_memory_read(s->target_as, addr, &intn, sizeof(intn), attrs);
> -    if (res != MEMTX_OK) {
> -        cause = RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT;
> -        goto err;
> -    }
> -
> -    if (!(intn & data)) {
> -        /* notification disabled, MRIF update completed. */
> -        return MEMTX_OK;
> -    }
> -
> -    /* Send notification message */
>       addr = PPN_PHYS(get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NPPN));
>       n190 = get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID) |
>             (get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID_MSB) << 10);
> 
> base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
> --
> 2.54.0
> 
> 
> ________________________________
> 
> Important: This email is confidential and may be privileged. If you are not the intended recipient, please delete it and notify us immediately; you should not copy or use it for any purpose, nor disclose its contents to any other person. Thank you.
>