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charset="utf-8" The AIA specification requires an IOMMU to send the configured notice MSI a= fter storing an MSI to an MRIF even when the corresponding interrupt-enable= bit is clear. The problem is that riscv_iommu_msi_write() currently reads = the MRIF interrupt-enable doubleword and suppresses the notice MSI when the= bit is zero. This patch removes the enable-word read and always sends the notice MSI aft= er updating the MRIF pending bit. Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation") Cc: qemu-stable@nongnu.org Signed-off-by: Flavien Solt Reviewed-by: Andrew Jones Reviewed-by: Daniel Henrique Barboza --- Tested with a deterministic qtest using qemu-system-riscv64. After this patch we get: enable=3D0: pending=3D0x20 notice=3D0x12d enable=3D1: pending=3D0x20 notice=3D0x12d hw/riscv/riscv-iommu.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index f6865d1..9627cab 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -788,20 +788,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUSta= te *s, goto err; } - /* Get MRIF enable bits */ - addr =3D addr + sizeof(intn); - res =3D dma_memory_read(s->target_as, addr, &intn, sizeof(intn), attrs= ); - if (res !=3D MEMTX_OK) { - cause =3D RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT; - goto err; - } - - if (!(intn & data)) { - /* notification disabled, MRIF update completed. */ - return MEMTX_OK; - } - - /* Send notification message */ addr =3D PPN_PHYS(get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NPPN)); n190 =3D get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID) | (get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID_MSB) << 10); base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05 -- 2.54.0 ________________________________ Important: This email is confidential and may be privileged. If you are not= the intended recipient, please delete it and notify us immediately; you sh= ould not copy or use it for any purpose, nor disclose its contents to any o= ther person. Thank you. --_000_KL1PR0601MB4874F12178F49F9BB8BEA7DF8DF92KL1PR0601MB4874_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
The AIA specification requires an IOMMU to send the configured notice MSI a= fter storing an MSI to an MRIF even when the corresponding interrupt-enable= bit is clear. The problem is that riscv_iommu_msi_write() currently reads = the MRIF interrupt-enable doubleword and suppresses the notice MSI when the bit is zero.

This patch removes the enable-word read and always sends the notice MSI aft= er updating the MRIF pending bit.

Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")=
Cc: qemu-stable@nongnu.org
Signed-off-by: Flavien Solt <flavien@nus.edu.sg>
---
Tested with a deterministic qtest using qemu-system-riscv64.

After this patch we get:
  enable=3D0: pending=3D0x20 notice=3D0x12d
  enable=3D1: pending=3D0x20 notice=3D0x12d

 hw/riscv/riscv-iommu.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index f6865d1..9627cab 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -788,20 +788,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUSta= te *s,
         goto err;
     }
 
-    /* Get MRIF enable bits */
-    addr =3D addr + sizeof(intn);
-    res =3D dma_memory_read(s->target_as, addr, &intn, si= zeof(intn), attrs);
-    if (res !=3D MEMTX_OK) {
-        cause =3D RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT;=
-        goto err;
-    }
-
-    if (!(intn & data)) {
-        /* notification disabled, MRIF update complete= d. */
-        return MEMTX_OK;
-    }
-
-    /* Send notification message */
     addr =3D PPN_PHYS(get_field(pte[1], RISCV_IOMMU_MSI_MRI= F_NPPN));
     n190 =3D get_field(pte[1], RISCV_IOMMU_MSI_MRIF_NID) |<= /div>
           (get_field(pte[1], RISCV_IOMMU_MSI= _MRIF_NID_MSB) << 10);

base-commit: 499039798cdad7d86b787fec0eaf1da4151c0f05
-- 
2.54.0



Important: This email is confidential and may be privileged. If you are not= the intended recipient, please delete it and notify us immediately; you sh= ould not copy or use it for any purpose, nor disclose its contents to any o= ther person. Thank you.
 --_000_KL1PR0601MB4874F12178F49F9BB8BEA7DF8DF92KL1PR0601MB4874_--