This series implements SPARC crypto instructions for QEMU. Most other
arches already support crypto instructions, but SPARC is lagging behind.
The following instructions are added:
- AES rounds and key expansions
- CRC32C
- SHA1/256/512
- RDCFR (Compatibility Feature Register)
Camellia is intentionally left out as it's possibly being removed from
the kernel code, and does not seem to be needed. DES/MD5/MPMUL also left
out, as Linux doesn't use them.
Motivated by the need for QEMU-testable SPARC crypto code without access
to real hardware. An issue was raised by kernel maintainer Eric Biggers
in: https://github.com/sparclinux/issues/issues/77
A new +crypto CPU feature enables the instructions and the CFR. This is
off by default, and does not change default behaviour.
The most difficult part to get right, and the biggest patch, was the
SHA instructions. On SPARC, a single instruction hashes one whole block.
sha1, sha256 and sha512 each do a complete FIPS 180-4 compression.
Testing:
- Every instruction tested against SPARC T4-1 and SPARC T7-1
- Tested QEMU on big-endian host (sparc64 T7-1)
- Linux 7.3-rc5 crypto and CRC KUnit suites (208 passed, 0 failed)
The Linux test used an unsent kernel patch plus -prom-env nvramrc.
AI tool disclosure:
- An early incomplete prototype was made using LLM tools
- Used to research the OSA 2011 and FIPS 180-4 document. Implementation
strategies and review of the _existing_ QEMU code.
- Local test tooling. Scripts for comparing the output vs real SPARC
hardware.
- Review of patches, fixes made by me
- No code, comments or commit messages directly from AI tools
References:
OSA (Oracle SPARC Architecture) 2011:
https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/140521-ua2011-d096-p-ext-2306580.pdf
qemu-devel RFC:
https://lists.gnu.org/archive/html/qemu-devel/2026-09/msg09494.html
Changes in v3:
- 2/8: Return CFR; R-b Philippe
- 3/8: AES rounds; message line on the next commit setting CFR.aes
(Philippe); R-b Philippe (T-b kept).
- 4/8: AES key expansion; deposit64() in aes_kexpand() (Philippe);
R-b Philippe
- 7/8: (NEW) target/sparc: Allow block-init stores when the CPU has the
crypto feature. Multiarch glibc got SIGILL in memcpy/memset with
+crypto. Placed before the linux-user patch. Reported on v2 7/7.
- 8/8: v2 patch 7, unchanged
v2: https://lore.kernel.org/qemu-devel/20261021064640.3591682-1-stian@itx.no/
Changes in v2:
- 1/7: use suggested commit message (Philippe); R-b Philippe
- 2/7: start with an empty CFR. Bits set in each instruction patch
- 3/7: byte-order comment, rk half zeroed explicitly; T-b Philippe
- 4/7: sets CFR.aes; "3-operand"/"4-operand" wording.
- 5/7: sets CFR.crc32c; "3-operand" wording; explicit 64-bit return;
R-b + T-b Philippe
- 6/7: sets the SHA bits; comment on the narrowing; R-b + T-b Philippe
- 7/7: -cpu TI-UltraSparc-II,+crypto mentioned; R-b Philippe
- Tests: Follow-up, as agreed (Philippe)
v1: https://lore.kernel.org/qemu-devel/20261020145530.3385376-1-stian@itx.no/
Stian Halseth (8):
target/sparc: Add crypto feature
target/sparc: Return CFR when crypto feature is enabled
target/sparc: Add the eight AES round instructions
target/sparc: Add the AES key expansion instructions
target/sparc: Add the CRC32C instruction
target/sparc: Add the SHA instructions
target/sparc: Allow block-init stores when the CPU has the crypto
feature
linux-user/sparc: Report HWCAP_SPARC_CRYPTO for crypto CPU feature
linux-user/sparc/elfload.c | 1 +
target/sparc/cpu-feature.h.inc | 1 +
target/sparc/cpu.c | 3 +
target/sparc/crypto_helper.c | 442 +++++++++++++++++++++++++++++++++
target/sparc/helper.h | 16 ++
target/sparc/insns.decode | 26 +-
target/sparc/meson.build | 2 +-
target/sparc/translate.c | 89 ++++++-
8 files changed, 576 insertions(+), 4 deletions(-)
create mode 100644 target/sparc/crypto_helper.c
base-commit: 11661d857254b27fca5568c6deacf4f6b6f3460f
--
2.43.0