From nobody Fri Oct 23 21:32:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=itx.no ARC-Seal: i=1; a=rsa-sha256; t=1792652550; cv=none; d=zohomail.com; s=zohoarc; b=fSxPbIJDSIdMOcp3OLd32Tx2BJ0ego4GJfuJn7KQobJzUKKi8806Zs0oPT1GV/dWU+fRq/saaHpyHAH9J7rkxSvEgpzcbjS1h0kS5Sqe4VxOUe+GbwigVTzg+9tecHFx/Evqp4lnLQHzaR6lFimOiYkQifohIkF76nYgPAwcNFI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792652550; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=N8S1gE9waKIsyA2TaGvT3mUme7EtsXYWFdPJ9syqTFY=; b=h/pdalAInJYn5FmK1Xi9G4pJjZZOO17eXoTtdVE+ARERkOnfX255pMS8HLwsbVS/m4YJV6m8g0Mctd+tZ2/swrPdrZgqMnAgiWt6UxxBOjwIdrDAf6AM2nbaqSC7EBZcmtzzIjmLqbBJxwxymrWOYg9AtPQfj4EuOB+hEdtRc2E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792652550371909.8603349562442; Thu, 22 Oct 2026 00:02:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJmoL-00030G-Sf; Thu, 22 Oct 2026 03:02:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJmnh-0002o3-DT for qemu-devel@nongnu.org; Thu, 22 Oct 2026 03:01:22 -0400 Received: from itx-kvm-14.itxnorge.no ([91.189.121.228] helo=mx.itxnorge.no) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJmne-0005uq-Pu for qemu-devel@nongnu.org; Thu, 22 Oct 2026 03:01:20 -0400 From: Stian Halseth DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=itx.no; s=mx.itx.no; t=1792652469; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=N8S1gE9waKIsyA2TaGvT3mUme7EtsXYWFdPJ9syqTFY=; b=lB2f7jIEfedI60t/x0LMwbYxoCxCFNcXYy+4JLeJjlZaakVu7WBAqKQwDFf5UggibFcezj t+jYeJpdwOSbLgPMB+qODaC9HU0MOprpreeOSomTS0oRxUVJ5QPLiefEDBmuF2D/H2QOtL Z+0tbNqCLkB7hR2hSZ3PXJdi/5ifh6c= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Helge Deller , Pierrick Bouvier , Eric Biggers , Stian Halseth Subject: [PATCH v3 1/8] target/sparc: Add crypto feature Date: Thu, 22 Oct 2026 09:00:52 +0200 Message-ID: <20261022070059.3861291-2-stian@itx.no> In-Reply-To: <20261022070059.3861291-1-stian@itx.no> References: <20261022070059.3861291-1-stian@itx.no> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=91.189.121.228; envelope-from=stian@itx.no; helo=mx.itxnorge.no X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @itx.no) X-ZM-MESSAGEID: 1792652552992158500 Add a "crypto" feature bit gating the OSA 2011 cryptographic instructions (AES, SHA-1/256/512, CRC32C, CFR in ASR 26). Off by default; no CPU model enables it yet; can be set explicitly with "-cpu ...,+crypto". SPARC64 only. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Stian Halseth Reviewed-by: Mark Cave-Ayland --- target/sparc/cpu-feature.h.inc | 1 + target/sparc/cpu.c | 3 +++ target/sparc/translate.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc index be81005237..4a32f49de4 100644 --- a/target/sparc/cpu-feature.h.inc +++ b/target/sparc/cpu-feature.h.inc @@ -16,3 +16,4 @@ FEATURE(FMAF) FEATURE(VIS3) FEATURE(IMA) FEATURE(VIS4) +FEATURE(CRYPTO) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ae9bdca9df..528a9d2bd8 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -560,6 +560,7 @@ static const char * const feature_name[] =3D { [CPU_FEATURE_BIT_VIS3] =3D "vis3", [CPU_FEATURE_BIT_IMA] =3D "ima", [CPU_FEATURE_BIT_VIS4] =3D "vis4", + [CPU_FEATURE_BIT_CRYPTO] =3D "crypto", #else [CPU_FEATURE_BIT_MUL] =3D "mul", [CPU_FEATURE_BIT_DIV] =3D "div", @@ -977,6 +978,8 @@ static const Property sparc_cpu_properties[] =3D { CPU_FEATURE_BIT_IMA, false), DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features, CPU_FEATURE_BIT_VIS4, false), + DEFINE_PROP_BIT("crypto", SPARCCPU, env.def.features, + CPU_FEATURE_BIT_CRYPTO, false), #else DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, CPU_FEATURE_BIT_MUL, false), diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3156be6a94..b93feb074b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2507,6 +2507,7 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_VIS3(C) ((C)->def->features & CPU_FEATURE_VIS3) # define avail_VIS3B(C) avail_VIS3(C) # define avail_VIS4(C) ((C)->def->features & CPU_FEATURE_VIS4) +# define avail_CRYPTO(C) ((C)->def->features & CPU_FEATURE_CRYPTO) #else # define avail_32(C) true # define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) @@ -2524,6 +2525,7 @@ static int extract_qfpreg(DisasContext *dc, int x) # define avail_VIS3(C) false # define avail_VIS3B(C) false # define avail_VIS4(C) false +# define avail_CRYPTO(C) false #endif =20 /* --=20 2.43.0 From nobody Fri Oct 23 21:32:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 22 Oct 2026 03:01:20 -0400 From: Stian Halseth DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=itx.no; s=mx.itx.no; t=1792652469; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4ISNFu9BwaApeD7sAFAEMcRN+Wq5WEv5tMgjEKvEE6Q=; b=P9Uk3XtDFgxgu1yHBbnqA/f2CAOos2d/SSJissqh4a7GH4IZ9Bm9YKV+A6bbwX6sljeET/ M+nGrpM/fktEJ64thKtbO7klrSMYZ1rxN10FENaNv4nLVvtgvgAP2hnOVxsxa8z9D1fZ/C GrECF2puC5nfp3nn1BsLmLqjQc/z8ko= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Helge Deller , Pierrick Bouvier , Eric Biggers , Stian Halseth Subject: [PATCH v3 2/8] target/sparc: Return CFR when crypto feature is enabled Date: Thu, 22 Oct 2026 09:00:53 +0200 Message-ID: <20261022070059.3861291-3-stian@itx.no> In-Reply-To: <20261022070059.3861291-1-stian@itx.no> References: <20261022070059.3861291-1-stian@itx.no> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=91.189.121.228; envelope-from=stian@itx.no; helo=mx.itxnorge.no X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @itx.no) X-ZM-MESSAGEID: 1792652567498158500 ASR 26 returns a Compatibility Feature Register (CFR) when the crypto feature is on. Without the crypto feature, a read keeps strand status as before. Return an empty CFR. Each instruction patch sets its bit. Guests can read the CFR before using each crypto instruction. Based on OSA (Oracle SPARC Architecture) 2011: - 5.5 (Ancillary State Registers), table 5-8 - 5.5.11 Compatibility Feature Register (CFR), table 5-15 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Stian Halseth Reviewed-by: Mark Cave-Ayland --- target/sparc/insns.decode | 5 ++++- target/sparc/translate.c | 14 ++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 242ec42016..55f8528ffe 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -106,7 +106,10 @@ CALL 01 i:s30 RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000 RDSTICK 10 rd:5 101000 11000 0 0000000000000 RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000 - RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 + { + RDCFR 10 rd:5 101000 11010 0 0000000000000 + RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 + } ] =20 # The v8 manual, section B.30 STBAR instruction, says diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b93feb074b..a1562f5047 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3022,6 +3022,20 @@ static TCGv do_rdstrand_status(DisasContext *dc, TCG= v dst) =20 TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_statu= s) =20 +/* CFR bits (OSA 2011, 5.5.11) */ +#define CFR_AES (1 << 0) +#define CFR_SHA1 (1 << 5) +#define CFR_SHA256 (1 << 6) +#define CFR_SHA512 (1 << 7) +#define CFR_CRC32C (1 << 11) + +static TCGv do_rdcfr(DisasContext *dc, TCGv dst) +{ + return tcg_constant_tl(0); +} + +TRANS(RDCFR, CRYPTO, do_rd_special, true, a->rd, do_rdcfr) + static TCGv do_rdpsr(DisasContext *dc, TCGv dst) { gen_helper_rdpsr(dst, tcg_env); --=20 2.43.0 From nobody Fri Oct 23 21:32:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=itx.no ARC-Seal: i=1; a=rsa-sha256; t=1792652518; cv=none; d=zohomail.com; s=zohoarc; b=BhoURt+k1HAelg74OuAO9MpSx9P9reZMUki5gPD906hGJHFnNwEAtdkD8GHUqr4CUd32sBVJ2ziDWxE7DOLGXb2d/9Lo0XwLT5/4XVS82RBB0ibz/vBZ+zhBmfqrwtB/re/cvWqTujna9pUG/De/UTuYwNF25hTv+hjVT77eLXY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792652518; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 22 Oct 2026 03:01:23 -0400 Received: from itx-kvm-14.itxnorge.no ([91.189.121.228] helo=mx.itxnorge.no) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJmne-0005up-P5 for qemu-devel@nongnu.org; Thu, 22 Oct 2026 03:01:21 -0400 From: Stian Halseth DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=itx.no; s=mx.itx.no; t=1792652469; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6epWgzjquJ4lHjBIoyWtxCEBvA3kIXAaPG8TU96aQvE=; b=UOpqYXO6UJdBryAjmEXr2DLURQHmRs5pqDQEpnEngFTgaSiKUz0fMzIui1PFzHZzE7cRBo KSXsN6v0jczbZy49ho2Bsip3Ng4W5J6q+KKsbBZfhrVVFZkMk0spjuPk6+qOQrsfsYdNhJ e+Pw5n8jutQH4nMZMBzrVzfg69H28Qg= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Helge Deller , Pierrick Bouvier , Eric Biggers , Stian Halseth Subject: [PATCH v3 3/8] target/sparc: Add the eight AES round instructions Date: Thu, 22 Oct 2026 09:00:54 +0200 Message-ID: <20261022070059.3861291-4-stian@itx.no> In-Reply-To: <20261022070059.3861291-1-stian@itx.no> References: <20261022070059.3861291-1-stian@itx.no> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=91.189.121.228; envelope-from=stian@itx.no; helo=mx.itxnorge.no X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @itx.no) X-ZM-MESSAGEID: 1792652521174158500 Implement the eight AES round instructions by using QEMU's shared crypto/aes-round.h, gated behind the crypto CPU feature: - AES_EROUND01/23 and last variants - AES_DROUND01/23 and last variants Based on OSA (Oracle SPARC Architecture) 2011, section 7.3: AES Cryptographic Operations (4 operand) Next commit will complete the feature and expose its availability to the guest by setting the AES bit in CFR. Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Stian Halseth Reviewed-by: Mark Cave-Ayland --- target/sparc/crypto_helper.c | 89 ++++++++++++++++++++++++++++++++++++ target/sparc/helper.h | 8 ++++ target/sparc/insns.decode | 9 ++++ target/sparc/meson.build | 2 +- target/sparc/translate.c | 16 +++++++ 5 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 target/sparc/crypto_helper.c diff --git a/target/sparc/crypto_helper.c b/target/sparc/crypto_helper.c new file mode 100644 index 0000000000..7dd4dd5144 --- /dev/null +++ b/target/sparc/crypto_helper.c @@ -0,0 +1,89 @@ +/* + * SPARC crypto instructions for QEMU + * + * Based on Oracle SPARC Architecture 2011 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "exec/helper-proto.h" +#include "crypto/aes-round.h" + +/* + * SPARC four-operand AES round (Section 7.3). + * s2:s3 holds the state; half selects output columns 0-1 or 2-3, and + * key supplies their round key. dec selects decryption; last omits + * MixColumns/InvMixColumns. Return the selected 64-bit half. + * + * Note all 64-bit values (state and key) hold AES bytes in big-endian + * order, i.e. the most significant byte is the first state byte. + */ +static uint64_t aes_round(uint64_t key, uint64_t s2, uint64_t s3, + int half, bool dec, bool last) +{ + AESState st, rk, r; + const unsigned first =3D HOST_BIG_ENDIAN ? 0 : 1; + const unsigned out =3D first ^ half; + + st.d[first] =3D s2; /* columns 0-1 */ + st.d[first ^ 1] =3D s3; /* columns 2-3 */ + rk.d[out] =3D key; + rk.d[out ^ 1] =3D 0; + + if (dec) { + if (last) { + aesdec_ISB_ISR_AK(&r, &st, &rk, true); + } else { + aesdec_ISB_ISR_AK_IMC(&r, &st, &rk, true); + } + } else { + if (last) { + aesenc_SB_SR_AK(&r, &st, &rk, true); + } else { + aesenc_SB_SR_MC_AK(&r, &st, &rk, true); + } + } + + return r.d[out]; +} + +uint64_t helper_aes_eround01(uint64_t key, uint64_t s2, uint64_t s3) +{ + return aes_round(key, s2, s3, 0, false, false); +} + +uint64_t helper_aes_eround23(uint64_t key, uint64_t s2, uint64_t s3) +{ + return aes_round(key, s2, s3, 1, false, false); +} + +uint64_t helper_aes_dround01(uint64_t key, uint64_t s2, uint64_t s3) +{ + return aes_round(key, s2, s3, 0, true, false); +} + +uint64_t helper_aes_dround23(uint64_t key, uint64_t s2, uint64_t s3) +{ + return aes_round(key, s2, s3, 1, true, false); +} + +uint64_t helper_aes_eround01_l(uint64_t key, uint64_t s2, uint64_t s3) +{ + return aes_round(key, s2, s3, 0, false, true); +} + +uint64_t helper_aes_eround23_l(uint64_t key, uint64_t s2, uint64_t s3) +{ + return aes_round(key, s2, s3, 1, false, true); +} + +uint64_t helper_aes_dround01_l(uint64_t key, uint64_t s2, uint64_t s3) +{ + return aes_round(key, s2, s3, 0, true, true); +} + +uint64_t helper_aes_dround23_l(uint64_t key, uint64_t s2, uint64_t s3) +{ + return aes_round(key, s2, s3, 1, true, true); +} diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 3a7f7dc129..9bfd643b09 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -122,6 +122,14 @@ DEF_HELPER_FLAGS_2(fchksm16, TCG_CALL_NO_RWG_SE, i64, = i64, i64) DEF_HELPER_FLAGS_2(fmean16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fslas16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fslas32, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_3(aes_eround01, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(aes_eround23, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(aes_dround01, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(aes_dround23, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(aes_eround01_l, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(aes_eround23_l, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(aes_dround01_l, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(aes_dround23_l, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##8, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 55f8528ffe..99c9147e7d 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -596,6 +596,15 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 } =20 +AES_EROUND01 10 ..... 011001 ..... ..... 0000 ..... @d_d_d_d +AES_EROUND23 10 ..... 011001 ..... ..... 0001 ..... @d_d_d_d +AES_DROUND01 10 ..... 011001 ..... ..... 0010 ..... @d_d_d_d +AES_DROUND23 10 ..... 011001 ..... ..... 0011 ..... @d_d_d_d +AES_EROUND01_L 10 ..... 011001 ..... ..... 0100 ..... @d_d_d_d +AES_EROUND23_L 10 ..... 011001 ..... ..... 0101 ..... @d_d_d_d +AES_DROUND01_L 10 ..... 011001 ..... ..... 0110 ..... @d_d_d_d +AES_DROUND23_L 10 ..... 011001 ..... ..... 0111 ..... @d_d_d_d + ## ## Major Opcode 11 -- load and store instructions ## diff --git a/target/sparc/meson.build b/target/sparc/meson.build index 46289c8669..af65c933bf 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -12,7 +12,7 @@ sparc_ss.add(files( 'win_helper.c', )) sparc_ss.add(when: 'TARGET_SPARC', if_true: files('int32_helper.c')) -sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int64_helper.c', 'vis= _helper.c')) +sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int64_helper.c', 'vis= _helper.c', 'crypto_helper.c')) =20 sparc_system_ss =3D ss.source_set() sparc_system_ss.add(files( diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a1562f5047..16907b1085 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -101,6 +101,14 @@ # define gen_helper_xmulx ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_xmulxhi ({ qemu_build_not_reached(); NULL= ; }) # define MAXTL_MASK 0 +# define gen_helper_aes_eround01 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_aes_eround23 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_aes_dround01 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_aes_dround23 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_aes_eround01_l ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_aes_eround23_l ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_aes_dround01_l ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_aes_dround23_l ({ qemu_build_not_reached(); NULL= ; }) #endif =20 #define DISAS_EXIT DISAS_TARGET_0 @@ -5418,6 +5426,14 @@ TRANS(FNMSUBd, FMAF, do_dddd, a, gen_op_fnmsubd) TRANS(FNMADDd, FMAF, do_dddd, a, gen_op_fnmaddd) TRANS(FPMADDX, IMA, do_dddd, a, gen_op_fpmaddx) TRANS(FPMADDXHI, IMA, do_dddd, a, gen_op_fpmaddxhi) +TRANS(AES_EROUND01, CRYPTO, do_dddd, a, gen_helper_aes_eround01) +TRANS(AES_EROUND23, CRYPTO, do_dddd, a, gen_helper_aes_eround23) +TRANS(AES_DROUND01, CRYPTO, do_dddd, a, gen_helper_aes_dround01) +TRANS(AES_DROUND23, CRYPTO, do_dddd, a, gen_helper_aes_dround23) +TRANS(AES_EROUND01_L, CRYPTO, do_dddd, a, gen_helper_aes_eround01_l) +TRANS(AES_EROUND23_L, CRYPTO, do_dddd, a, gen_helper_aes_eround23_l) +TRANS(AES_DROUND01_L, CRYPTO, do_dddd, a, gen_helper_aes_dround01_l) +TRANS(AES_DROUND23_L, CRYPTO, do_dddd, a, gen_helper_aes_dround23_l) =20 static bool trans_FALIGNDATAi(DisasContext *dc, arg_r_r_r *a) { --=20 2.43.0 From nobody Fri Oct 23 21:32:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 22 Oct 2026 03:01:21 -0400 From: Stian Halseth DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=itx.no; s=mx.itx.no; t=1792652469; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RG3kqcGpVFD3x3hnlWSljWb5C7SkKne+FuTFH9bJc5g=; b=FBJ24M7OsvW8xTYVLUqkS1ZDp11YUp04FKmTkc7i/+puby/5lnlx8v7eWBYz0oXdOy/urS ALMu/zkTnrzJAettjx+hsOHOC9VGUPRUyabjGSl/3l1lFjKyZqOGqjTUcxuCeV9Hz9Czf+ EEMiWv9U9aBJLyZJUVinNkwMg23U3oU= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Helge Deller , Pierrick Bouvier , Eric Biggers , Stian Halseth Subject: [PATCH v3 4/8] target/sparc: Add the AES key expansion instructions Date: Thu, 22 Oct 2026 09:00:55 +0200 Message-ID: <20261022070059.3861291-5-stian@itx.no> In-Reply-To: <20261022070059.3861291-1-stian@itx.no> References: <20261022070059.3861291-1-stian@itx.no> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=91.189.121.228; envelope-from=stian@itx.no; helo=mx.itxnorge.no X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @itx.no) X-ZM-MESSAGEID: 1792652591738158500 Implement the AES key expansion instructions according to OSA (Oracle SPARC Architecture) 2011 sections 7.3 and 7.4 and set the AES bit in the CFR. 4-operand form (7.3): - AES_KEXPAND1 3-operand form (7.4): - AES_KEXPAND0 - AES_KEXPAND2 Like the AES round instructions, they are gated behind the crypto CPU feature and disabled for sparc32. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Stian Halseth Reviewed-by: Mark Cave-Ayland --- target/sparc/crypto_helper.c | 58 ++++++++++++++++++++++++++++++++++++ target/sparc/helper.h | 3 ++ target/sparc/insns.decode | 7 +++++ target/sparc/translate.c | 30 ++++++++++++++++++- 4 files changed, 97 insertions(+), 1 deletion(-) diff --git a/target/sparc/crypto_helper.c b/target/sparc/crypto_helper.c index 7dd4dd5144..f04bd3569d 100644 --- a/target/sparc/crypto_helper.c +++ b/target/sparc/crypto_helper.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "exec/helper-proto.h" #include "crypto/aes-round.h" +#include "crypto/aes.h" =20 /* * SPARC four-operand AES round (Section 7.3). @@ -87,3 +88,60 @@ uint64_t helper_aes_dround23_l(uint64_t key, uint64_t s2= , uint64_t s3) { return aes_round(key, s2, s3, 1, true, true); } + +/* Combine the transformed word with the two words in rs1. */ +static uint64_t aes_kexpand(uint64_t rs1, uint32_t t) +{ + uint32_t hi =3D (rs1 >> 32) ^ t; + uint32_t lo =3D (uint32_t)rs1 ^ hi; + + return deposit64(lo, 32, 32, hi); +} + +/* Apply the AES S-box to each byte, preserving byte positions. */ +static uint32_t aes_subword(uint32_t x) +{ + return ((uint32_t)AES_sbox[x >> 24] << 24) | + ((uint32_t)AES_sbox[(x >> 16) & 0xff] << 16) | + ((uint32_t)AES_sbox[(x >> 8) & 0xff] << 8) | + (uint32_t)AES_sbox[x & 0xff]; +} + +/* + * AES Cryptographic Operations 4-operand (Section 7.3) + * AES key expansion with RotWord, SubWord, and RCON. + */ +uint64_t helper_aes_kexpand1(uint64_t rs1, uint64_t rs2, uint32_t imm) +{ + static const uint8_t rcon[10] =3D { + 0x01, 0x02, 0x04, 0x08, 0x10, + 0x20, 0x40, 0x80, 0x1b, 0x36, + }; + uint32_t t =3D rol32((uint32_t)rs2, 8); + + t =3D aes_subword(t); + + if (imm < ARRAY_SIZE(rcon)) { + t ^=3D (uint32_t)rcon[imm] << 24; + } + + return aes_kexpand(rs1, t); +} + +/* + * AES Cryptographic Operations 3-operand (Section 7.4) + * AES key expansion with SubWord, without RotWord or RCON. + */ +uint64_t helper_aes_kexpand0(uint64_t rs1, uint64_t rs2) +{ + return aes_kexpand(rs1, aes_subword(rs2)); +} + +/* + * AES Cryptographic Operations 3-operand (Section 7.4) + * AES key expansion without SubWord, RotWord, or RCON. + */ +uint64_t helper_aes_kexpand2(uint64_t rs1, uint64_t rs2) +{ + return aes_kexpand(rs1, (uint32_t)rs2); +} diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 9bfd643b09..685b89d9c5 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -130,6 +130,9 @@ DEF_HELPER_FLAGS_3(aes_eround01_l, TCG_CALL_NO_RWG_SE, = i64, i64, i64, i64) DEF_HELPER_FLAGS_3(aes_eround23_l, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(aes_dround01_l, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(aes_dround23_l, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) +DEF_HELPER_FLAGS_2(aes_kexpand0, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_3(aes_kexpand1, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) +DEF_HELPER_FLAGS_2(aes_kexpand2, TCG_CALL_NO_RWG_SE, i64, i64, i64) #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##8, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 99c9147e7d..96791c7658 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -86,6 +86,10 @@ CALL 01 i:s30 @d_d_d_d .. ..... ...... ..... ..... .... ..... \ &r_r_r_r rd=3D%dfp_rd rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 rs3=3D%dfp= _rs3 =20 +&r_r_i_r rd rs1 imm rs2 +@d_d_i_d .. ..... ...... ..... imm:5 .... ..... \ + &r_r_i_r rd=3D%dfp_rd rs1=3D%dfp_rs1 rs2=3D%dfp_rs2 + { [ STBAR_v9 10 00000 101000 01111 0 0000000000000 @@ -571,6 +575,8 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ FPMAXU8 10 ..... 110110 ..... 1 0101 1101 ..... @d_d_d FPMAXU16 10 ..... 110110 ..... 1 0101 1110 ..... @d_d_d FPMAXU32 10 ..... 110110 ..... 1 0101 1111 ..... @d_d_d + AES_KEXPAND0 10 ..... 110110 ..... 1 0011 0000 ..... @d_d_d + AES_KEXPAND2 10 ..... 110110 ..... 1 0011 0001 ..... @d_d_d =20 FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5 FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \ @@ -604,6 +610,7 @@ AES_EROUND01_L 10 ..... 011001 ..... ..... 0100 ..... = @d_d_d_d AES_EROUND23_L 10 ..... 011001 ..... ..... 0101 ..... @d_d_d_d AES_DROUND01_L 10 ..... 011001 ..... ..... 0110 ..... @d_d_d_d AES_DROUND23_L 10 ..... 011001 ..... ..... 0111 ..... @d_d_d_d +AES_KEXPAND1 10 ..... 011001 ..... ..... 1000 ..... @d_d_i_d =20 ## ## Major Opcode 11 -- load and store instructions diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 16907b1085..ad32b53cc3 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -109,6 +109,8 @@ # define gen_helper_aes_eround23_l ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_aes_dround01_l ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_aes_dround23_l ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_aes_kexpand0 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_aes_kexpand2 ({ qemu_build_not_reached(); NULL= ; }) #endif =20 #define DISAS_EXIT DISAS_TARGET_0 @@ -3039,7 +3041,7 @@ TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->= rd, do_rdstrand_status) =20 static TCGv do_rdcfr(DisasContext *dc, TCGv dst) { - return tcg_constant_tl(0); + return tcg_constant_tl(CFR_AES); } =20 TRANS(RDCFR, CRYPTO, do_rd_special, true, a->rd, do_rdcfr) @@ -5434,6 +5436,32 @@ TRANS(AES_EROUND01_L, CRYPTO, do_dddd, a, gen_helper= _aes_eround01_l) TRANS(AES_EROUND23_L, CRYPTO, do_dddd, a, gen_helper_aes_eround23_l) TRANS(AES_DROUND01_L, CRYPTO, do_dddd, a, gen_helper_aes_dround01_l) TRANS(AES_DROUND23_L, CRYPTO, do_dddd, a, gen_helper_aes_dround23_l) +TRANS(AES_KEXPAND0, CRYPTO, do_ddd, a, gen_helper_aes_kexpand0) +TRANS(AES_KEXPAND2, CRYPTO, do_ddd, a, gen_helper_aes_kexpand2) + +/* AES key expansion with RCON selected by the 5-bit immediate in imm */ +static bool trans_AES_KEXPAND1(DisasContext *dc, arg_r_r_i_r *a) +{ + #ifdef TARGET_SPARC64 + TCGv_i64 dst, src1, src2; + + if (!avail_CRYPTO(dc)) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst =3D tcg_temp_new_i64(); + src1 =3D gen_load_fpr_D(dc, a->rs1); + src2 =3D gen_load_fpr_D(dc, a->rs2); + gen_helper_aes_kexpand1(dst, src1, src2, tcg_constant_i32(a->imm)); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); + #else + return false; + #endif +} =20 static bool trans_FALIGNDATAi(DisasContext *dc, arg_r_r_r *a) { --=20 2.43.0 From nobody Fri Oct 23 21:32:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=itx.no ARC-Seal: i=1; a=rsa-sha256; t=1792652581; cv=none; d=zohomail.com; s=zohoarc; b=ko+g4bBmb1Y2Dy/K1x3Q8NhwUNDfhOKOnRhGbrqhkrmWK8tbLoWYHXN7rS3/uBB5/iBigyJ6l23oA4uh8vtTx2oLbiI2oon6E355zcNZLwPF/K7Eb61z2Tb+ET6frNQCB7e/ytpjgM8/4w3Mc8yNAtVbmgn+JrKA2Dgf9QUbi44= ARC-Message-Signature: i=1; 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Thu, 22 Oct 2026 03:01:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJmnl-0002p4-GZ for qemu-devel@nongnu.org; Thu, 22 Oct 2026 03:01:29 -0400 Received: from itx-kvm-14.itxnorge.no ([91.189.121.228] helo=mx.itxnorge.no) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJmni-0005vn-4p for qemu-devel@nongnu.org; Thu, 22 Oct 2026 03:01:24 -0400 From: Stian Halseth DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=itx.no; s=mx.itx.no; t=1792652469; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Klyy6f51u+zXBdawzmvctyasq9zfdOiKeiqql16F1L8=; b=QvY+9boRFHAOxdzFhmHqhpa6n+TipGfwOY1WHQkSd0SuzMTu44xnGH+X+tGlH8OEg5Tiwn QgQjiH0v5CYZBBTicrWwP3reTlU0k/gW6FlhNSrWqxaTFnsFzhZ7r2e+et/BXfbfoTPAuO hKVamnKZzSqNmL2fc0Dz68YJriWtJEU= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Helge Deller , Pierrick Bouvier , Eric Biggers , Stian Halseth Subject: [PATCH v3 5/8] target/sparc: Add the CRC32C instruction Date: Thu, 22 Oct 2026 09:00:56 +0200 Message-ID: <20261022070059.3861291-6-stian@itx.no> In-Reply-To: <20261022070059.3861291-1-stian@itx.no> References: <20261022070059.3861291-1-stian@itx.no> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=91.189.121.228; envelope-from=stian@itx.no; helo=mx.itxnorge.no X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @itx.no) X-ZM-MESSAGEID: 1792652583690158500 Implement the CRC32C instruction according to OSA (Oracle SPARC Architecture) 2011 section 7.19 and set the CRC32C bit in the CFR. Using QEMU's crc32c.h and bswap.h. Gated behind the crypto CPU feature and disabled for sparc32. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Stian Halseth Reviewed-by: Mark Cave-Ayland --- target/sparc/crypto_helper.c | 21 +++++++++++++++++++++ target/sparc/helper.h | 1 + target/sparc/insns.decode | 1 + target/sparc/translate.c | 4 +++- 4 files changed, 26 insertions(+), 1 deletion(-) diff --git a/target/sparc/crypto_helper.c b/target/sparc/crypto_helper.c index f04bd3569d..7189814b75 100644 --- a/target/sparc/crypto_helper.c +++ b/target/sparc/crypto_helper.c @@ -10,6 +10,8 @@ #include "exec/helper-proto.h" #include "crypto/aes-round.h" #include "crypto/aes.h" +#include "qemu/bswap.h" +#include "qemu/crc32c.h" =20 /* * SPARC four-operand AES round (Section 7.3). @@ -145,3 +147,22 @@ uint64_t helper_aes_kexpand2(uint64_t rs1, uint64_t rs= 2) { return aes_kexpand(rs1, (uint32_t)rs2); } + +/* + * CRC32C Operation 3-operand (Section 7.19) + * Accumulate CRC32C over the eight bytes of rs2, most significant first. + */ +uint64_t helper_crc32c(uint64_t rs1, uint64_t rs2) +{ + uint8_t buf[8]; + /* IV and result are byte-swapped in the register. */ + uint32_t crc =3D bswap32((uint32_t)rs1); + + stq_be_p(buf, rs2); + + /* Undo crc32c()'s final inversion for the instruction's raw result. */ + crc =3D crc32c(crc, buf, sizeof(buf)) ^ UINT32_MAX; + + /* Result lives in the low 32 bits; upper half reads as zero. */ + return (uint64_t)bswap32(crc); +} diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 685b89d9c5..1320f5ebba 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -133,6 +133,7 @@ DEF_HELPER_FLAGS_3(aes_dround23_l, TCG_CALL_NO_RWG_SE, = i64, i64, i64, i64) DEF_HELPER_FLAGS_2(aes_kexpand0, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_3(aes_kexpand1, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_2(aes_kexpand2, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, i64, i64, i64) #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##8, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 96791c7658..05c1e73d7f 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -577,6 +577,7 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 .....= \ FPMAXU32 10 ..... 110110 ..... 1 0101 1111 ..... @d_d_d AES_KEXPAND0 10 ..... 110110 ..... 1 0011 0000 ..... @d_d_d AES_KEXPAND2 10 ..... 110110 ..... 1 0011 0001 ..... @d_d_d + CRC32C 10 ..... 110110 ..... 1 0100 0111 ..... @d_d_d =20 FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5 FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ad32b53cc3..562bfb506b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -111,6 +111,7 @@ # define gen_helper_aes_dround23_l ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_aes_kexpand0 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_aes_kexpand2 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_crc32c ({ qemu_build_not_reached(); NULL= ; }) #endif =20 #define DISAS_EXIT DISAS_TARGET_0 @@ -3041,7 +3042,7 @@ TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->= rd, do_rdstrand_status) =20 static TCGv do_rdcfr(DisasContext *dc, TCGv dst) { - return tcg_constant_tl(CFR_AES); + return tcg_constant_tl(CFR_AES | CFR_CRC32C); } =20 TRANS(RDCFR, CRYPTO, do_rd_special, true, a->rd, do_rdcfr) @@ -5438,6 +5439,7 @@ TRANS(AES_DROUND01_L, CRYPTO, do_dddd, a, gen_helper_= aes_dround01_l) TRANS(AES_DROUND23_L, CRYPTO, do_dddd, a, gen_helper_aes_dround23_l) TRANS(AES_KEXPAND0, CRYPTO, do_ddd, a, gen_helper_aes_kexpand0) TRANS(AES_KEXPAND2, CRYPTO, do_ddd, a, gen_helper_aes_kexpand2) +TRANS(CRC32C, CRYPTO, do_ddd, a, gen_helper_crc32c) =20 /* AES key expansion with RCON selected by the 5-bit immediate in imm */ static bool trans_AES_KEXPAND1(DisasContext *dc, arg_r_r_i_r *a) --=20 2.43.0 From nobody Fri Oct 23 21:32:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 22 Oct 2026 03:01:25 -0400 From: Stian Halseth DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=itx.no; s=mx.itx.no; t=1792652469; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=z5pjPllneu+HLD+KvTKQNijwGzgGUr/ryUkmRGYQOHI=; b=FNT/2lyq8t/6SSsisCWznUFvSeVaacn3Xn91hRW44bnyCUx/J6fv9qNsRIfRbYBpi9iWpa OGgVVmX3qh3Gvmoc9ONM4k94ztShGxe2nWy5fst6OujC254vPMKo7ETC9CS3D6Cy1+b2wB 6C7buKbeoB3u7Ruwa13f8QA4JKA/9U0= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Helge Deller , Pierrick Bouvier , Eric Biggers , Stian Halseth Subject: [PATCH v3 6/8] target/sparc: Add the SHA instructions Date: Thu, 22 Oct 2026 09:00:57 +0200 Message-ID: <20261022070059.3861291-7-stian@itx.no> In-Reply-To: <20261022070059.3861291-1-stian@itx.no> References: <20261022070059.3861291-1-stian@itx.no> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=91.189.121.228; envelope-from=stian@itx.no; helo=mx.itxnorge.no X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @itx.no) X-ZM-MESSAGEID: 1792652593822158500 Implement the SHA1, SHA256 and SHA512 instructions according to OSA (Oracle SPARC Architecture) 2011 section 7.115, using the algorithms defined in FIPS 180-4, and set the SHA1/SHA256/SHA512 bits in the CFR. Read and update the fixed floating-point registers and mark the lower FPR bank dirty. Share the SHA-2 Boolean functions between the SHA256 and SHA512 helpers. Gated behind the crypto CPU feature and disabled for sparc32. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Stian Halseth Reviewed-by: Mark Cave-Ayland --- target/sparc/crypto_helper.c | 274 +++++++++++++++++++++++++++++++++++ target/sparc/helper.h | 4 + target/sparc/insns.decode | 4 + target/sparc/translate.c | 21 ++- 4 files changed, 302 insertions(+), 1 deletion(-) diff --git a/target/sparc/crypto_helper.c b/target/sparc/crypto_helper.c index 7189814b75..6b6c843b3d 100644 --- a/target/sparc/crypto_helper.c +++ b/target/sparc/crypto_helper.c @@ -12,6 +12,7 @@ #include "crypto/aes.h" #include "qemu/bswap.h" #include "qemu/crc32c.h" +#include "cpu.h" =20 /* * SPARC four-operand AES round (Section 7.3). @@ -166,3 +167,276 @@ uint64_t helper_crc32c(uint64_t rs1, uint64_t rs2) /* Result lives in the low 32 bits; upper half reads as zero. */ return (uint64_t)bswap32(crc); } + +/* + * Compress one SHA-1 block from f8-f23 into f0-f4. + * Clear f5 to match SPARC M7 behavior. + */ +void helper_sha1(CPUSPARCState *env) +{ + uint32_t a =3D env->fpr[0].l.upper; + uint32_t b =3D env->fpr[0].l.lower; + uint32_t c =3D env->fpr[1].l.upper; + uint32_t d =3D env->fpr[1].l.lower; + uint32_t e =3D env->fpr[2].l.upper; + uint32_t w[80]; + + /* Load 16 message words; each fpr[] entry holds two words. */ + for (int i =3D 0; i < 8; i++) { + w[2 * i] =3D env->fpr[4 + i].l.upper; + w[2 * i + 1] =3D env->fpr[4 + i].l.lower; + } + + /* Expand the message into the 80-word round schedule. */ + for (int i =3D 16; i < 80; i++) { + w[i] =3D rol32(w[i - 3] ^ w[i - 8] ^ + w[i - 14] ^ w[i - 16], 1); + } + + /* Each group of 20 rounds uses its own function and constant. */ + for (int i =3D 0; i < 80; i++) { + uint32_t f, k, t; + + if (i < 20) { + f =3D (b & c) | (~b & d); /* Choose */ + k =3D 0x5a827999; + } else if (i < 40) { + f =3D b ^ c ^ d; /* Parity */ + k =3D 0x6ed9eba1; + } else if (i < 60) { + f =3D (b & c) | (b & d) | (c & d); /* Majority */ + k =3D 0x8f1bbcdc; + } else { + f =3D b ^ c ^ d; /* Parity */ + k =3D 0xca62c1d6; + } + + /* Advance the five working words, with arithmetic modulo 2^32. */ + t =3D rol32(a, 5) + f + e + k + w[i]; + e =3D d; + d =3D c; + c =3D rol32(b, 30); + b =3D a; + a =3D t; + } + + /* Accumulate the hash in f0-f4 and clear the unused f5 word. */ + env->fpr[0].l.upper +=3D a; + env->fpr[0].l.lower +=3D b; + env->fpr[1].l.upper +=3D c; + env->fpr[1].l.lower +=3D d; + env->fpr[2].l.upper +=3D e; + env->fpr[2].l.lower =3D 0; +} + +/* SHA-2 Boolean functions. */ +static inline uint64_t sha_ch(uint64_t x, uint64_t y, uint64_t z) +{ + return (x & y) ^ (~x & z); +} + +static inline uint64_t sha_maj(uint64_t x, uint64_t y, uint64_t z) +{ + return (x & y) ^ (x & z) ^ (y & z); +} + +static const uint32_t sha256_k[64] =3D { + 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, + 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, + 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, + 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, + 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, + 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, + 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, + 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, + 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, + 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, + 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, + 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, + 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, + 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, + 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, + 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2, +}; + +static const uint64_t sha512_k[80] =3D { + UINT64_C(0x428a2f98d728ae22), UINT64_C(0x7137449123ef65cd), + UINT64_C(0xb5c0fbcfec4d3b2f), UINT64_C(0xe9b5dba58189dbbc), + UINT64_C(0x3956c25bf348b538), UINT64_C(0x59f111f1b605d019), + UINT64_C(0x923f82a4af194f9b), UINT64_C(0xab1c5ed5da6d8118), + UINT64_C(0xd807aa98a3030242), UINT64_C(0x12835b0145706fbe), + UINT64_C(0x243185be4ee4b28c), UINT64_C(0x550c7dc3d5ffb4e2), + UINT64_C(0x72be5d74f27b896f), UINT64_C(0x80deb1fe3b1696b1), + UINT64_C(0x9bdc06a725c71235), UINT64_C(0xc19bf174cf692694), + UINT64_C(0xe49b69c19ef14ad2), UINT64_C(0xefbe4786384f25e3), + UINT64_C(0x0fc19dc68b8cd5b5), UINT64_C(0x240ca1cc77ac9c65), + UINT64_C(0x2de92c6f592b0275), UINT64_C(0x4a7484aa6ea6e483), + UINT64_C(0x5cb0a9dcbd41fbd4), UINT64_C(0x76f988da831153b5), + UINT64_C(0x983e5152ee66dfab), UINT64_C(0xa831c66d2db43210), + UINT64_C(0xb00327c898fb213f), UINT64_C(0xbf597fc7beef0ee4), + UINT64_C(0xc6e00bf33da88fc2), UINT64_C(0xd5a79147930aa725), + UINT64_C(0x06ca6351e003826f), UINT64_C(0x142929670a0e6e70), + UINT64_C(0x27b70a8546d22ffc), UINT64_C(0x2e1b21385c26c926), + UINT64_C(0x4d2c6dfc5ac42aed), UINT64_C(0x53380d139d95b3df), + UINT64_C(0x650a73548baf63de), UINT64_C(0x766a0abb3c77b2a8), + UINT64_C(0x81c2c92e47edaee6), UINT64_C(0x92722c851482353b), + UINT64_C(0xa2bfe8a14cf10364), UINT64_C(0xa81a664bbc423001), + UINT64_C(0xc24b8b70d0f89791), UINT64_C(0xc76c51a30654be30), + UINT64_C(0xd192e819d6ef5218), UINT64_C(0xd69906245565a910), + UINT64_C(0xf40e35855771202a), UINT64_C(0x106aa07032bbd1b8), + UINT64_C(0x19a4c116b8d2d0c8), UINT64_C(0x1e376c085141ab53), + UINT64_C(0x2748774cdf8eeb99), UINT64_C(0x34b0bcb5e19b48a8), + UINT64_C(0x391c0cb3c5c95a63), UINT64_C(0x4ed8aa4ae3418acb), + UINT64_C(0x5b9cca4f7763e373), UINT64_C(0x682e6ff3d6b2b8a3), + UINT64_C(0x748f82ee5defb2fc), UINT64_C(0x78a5636f43172f60), + UINT64_C(0x84c87814a1f0ab72), UINT64_C(0x8cc702081a6439ec), + UINT64_C(0x90befffa23631e28), UINT64_C(0xa4506cebde82bde9), + UINT64_C(0xbef9a3f7b2c67915), UINT64_C(0xc67178f2e372532b), + UINT64_C(0xca273eceea26619c), UINT64_C(0xd186b8c721c0c207), + UINT64_C(0xeada7dd6cde0eb1e), UINT64_C(0xf57d4f7fee6ed178), + UINT64_C(0x06f067aa72176fba), UINT64_C(0x0a637dc5a2c898a6), + UINT64_C(0x113f9804bef90dae), UINT64_C(0x1b710b35131c471b), + UINT64_C(0x28db77f523047d84), UINT64_C(0x32caab7b40c72493), + UINT64_C(0x3c9ebe0a15c9bebc), UINT64_C(0x431d67c49c100d4c), + UINT64_C(0x4cc5d4becb3e42b6), UINT64_C(0x597f299cfc657e2a), + UINT64_C(0x5fcb6fab3ad6faec), UINT64_C(0x6c44198c4a475817), +}; + +/* Compress 16 numeric message words into the supplied SHA-256 state. */ +static void sha256_compress(uint32_t state[8], const uint32_t block[16]) +{ + uint32_t a =3D state[0], b =3D state[1], c =3D state[2], d =3D state[3= ]; + uint32_t e =3D state[4], f =3D state[5], g =3D state[6], h =3D state[7= ]; + uint32_t w[64]; + + /* Expand the message into the 64-word round schedule. */ + memcpy(w, block, 16 * sizeof(*w)); + for (int i =3D 16; i < 64; i++) { + uint32_t x =3D w[i - 15], y =3D w[i - 2]; + uint32_t s0 =3D ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3); + uint32_t s1 =3D ror32(y, 17) ^ ror32(y, 19) ^ (y >> 10); + + w[i] =3D w[i - 16] + s0 + w[i - 7] + s1; + } + + /* Perform 64 rounds with arithmetic modulo 2^32. */ + for (int i =3D 0; i < 64; i++) { + uint32_t s0 =3D ror32(a, 2) ^ ror32(a, 13) ^ ror32(a, 22); + uint32_t s1 =3D ror32(e, 6) ^ ror32(e, 11) ^ ror32(e, 25); + + /* sha_ch/sha_maj are shared with SHA-512; narrow to 32 bits. */ + uint32_t t1 =3D h + s1 + (uint32_t)sha_ch(e, f, g) + + sha256_k[i] + w[i]; + uint32_t t2 =3D s0 + (uint32_t)sha_maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + t1; + d =3D c; + c =3D b; + b =3D a; + a =3D t1 + t2; + } + + /* Add the working words to the original state. */ + state[0] +=3D a; + state[1] +=3D b; + state[2] +=3D c; + state[3] +=3D d; + state[4] +=3D e; + state[5] +=3D f; + state[6] +=3D g; + state[7] +=3D h; +} + +/* Compress 16 numeric message words into the supplied SHA-512 state. */ +static void sha512_compress(uint64_t state[8], const uint64_t block[16]) +{ + uint64_t a =3D state[0], b =3D state[1], c =3D state[2], d =3D state[3= ]; + uint64_t e =3D state[4], f =3D state[5], g =3D state[6], h =3D state[7= ]; + uint64_t w[80]; + + /* Expand the message into the 80-word round schedule. */ + memcpy(w, block, 16 * sizeof(*w)); + for (int i =3D 16; i < 80; i++) { + uint64_t x =3D w[i - 15], y =3D w[i - 2]; + uint64_t s0 =3D ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7); + uint64_t s1 =3D ror64(y, 19) ^ ror64(y, 61) ^ (y >> 6); + + w[i] =3D w[i - 16] + s0 + w[i - 7] + s1; + } + + /* Perform 80 rounds with arithmetic modulo 2^64. */ + for (int i =3D 0; i < 80; i++) { + uint64_t s0 =3D ror64(a, 28) ^ ror64(a, 34) ^ ror64(a, 39); + uint64_t s1 =3D ror64(e, 14) ^ ror64(e, 18) ^ ror64(e, 41); + uint64_t t1 =3D h + s1 + sha_ch(e, f, g) + sha512_k[i] + w[i]; + uint64_t t2 =3D s0 + sha_maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + t1; + d =3D c; + c =3D b; + b =3D a; + a =3D t1 + t2; + } + + /* Add the working words to the original state. */ + state[0] +=3D a; + state[1] +=3D b; + state[2] +=3D c; + state[3] +=3D d; + state[4] +=3D e; + state[5] +=3D f; + state[6] +=3D g; + state[7] +=3D h; +} + +/* Compress one SHA-256 block from f8-f23 into f0-f7. */ +void helper_sha256(CPUSPARCState *env) +{ + uint32_t state[8], block[16]; + + /* Each fpr[] entry holds two architectural 32-bit registers. */ + for (int i =3D 0; i < 4; i++) { + state[2 * i] =3D env->fpr[i].l.upper; + state[2 * i + 1] =3D env->fpr[i].l.lower; + } + for (int i =3D 0; i < 8; i++) { + block[2 * i] =3D env->fpr[4 + i].l.upper; + block[2 * i + 1] =3D env->fpr[4 + i].l.lower; + } + + sha256_compress(state, block); + + for (int i =3D 0; i < 4; i++) { + env->fpr[i].l.upper =3D state[2 * i]; + env->fpr[i].l.lower =3D state[2 * i + 1]; + } +} + +/* + * Compress one SHA-512 block from FD16, FD18, ..., FD46 + * into FD0, FD2, ..., FD14. + */ +void helper_sha512(CPUSPARCState *env) +{ + uint64_t state[8], block[16]; + + /* Each fpr[] entry holds one architectural 64-bit register. */ + for (int i =3D 0; i < 8; i++) { + state[i] =3D env->fpr[i].ll; + } + for (int i =3D 0; i < 16; i++) { + block[i] =3D env->fpr[8 + i].ll; + } + + sha512_compress(state, block); + + for (int i =3D 0; i < 8; i++) { + env->fpr[i].ll =3D state[i]; + } +} diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 1320f5ebba..fd280c426f 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -134,6 +134,10 @@ DEF_HELPER_FLAGS_2(aes_kexpand0, TCG_CALL_NO_RWG_SE, i= 64, i64, i64) DEF_HELPER_FLAGS_3(aes_kexpand1, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_2(aes_kexpand2, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_1(sha1, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_1(sha256, TCG_CALL_NO_RWG, void, env) +DEF_HELPER_FLAGS_1(sha512, TCG_CALL_NO_RWG, void, env) + #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##8, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 05c1e73d7f..edb82a492e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -575,9 +575,13 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ....= . \ FPMAXU8 10 ..... 110110 ..... 1 0101 1101 ..... @d_d_d FPMAXU16 10 ..... 110110 ..... 1 0101 1110 ..... @d_d_d FPMAXU32 10 ..... 110110 ..... 1 0101 1111 ..... @d_d_d + AES_KEXPAND0 10 ..... 110110 ..... 1 0011 0000 ..... @d_d_d AES_KEXPAND2 10 ..... 110110 ..... 1 0011 0001 ..... @d_d_d CRC32C 10 ..... 110110 ..... 1 0100 0111 ..... @d_d_d + SHA1 10 00000 110110 00000 1 0100 0001 00000 + SHA256 10 00000 110110 00000 1 0100 0010 00000 + SHA512 10 00000 110110 00000 1 0100 0011 00000 =20 FLCMPs 10 000 cc:2 110110 rs1:5 1 0101 0001 rs2:5 FLCMPd 10 000 cc:2 110110 ..... 1 0101 0010 ..... \ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 562bfb506b..921ffd2d1b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -112,6 +112,9 @@ # define gen_helper_aes_kexpand0 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_aes_kexpand2 ({ qemu_build_not_reached(); NULL= ; }) # define gen_helper_crc32c ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_sha1 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_sha256 ({ qemu_build_not_reached(); NULL= ; }) +# define gen_helper_sha512 ({ qemu_build_not_reached(); NULL= ; }) #endif =20 #define DISAS_EXIT DISAS_TARGET_0 @@ -3042,7 +3045,8 @@ TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->= rd, do_rdstrand_status) =20 static TCGv do_rdcfr(DisasContext *dc, TCGv dst) { - return tcg_constant_tl(CFR_AES | CFR_CRC32C); + return tcg_constant_tl(CFR_AES | CFR_CRC32C | CFR_SHA1 | + CFR_SHA256 | CFR_SHA512); } =20 TRANS(RDCFR, CRYPTO, do_rd_special, true, a->rd, do_rdcfr) @@ -5422,6 +5426,18 @@ static bool do_dddd(DisasContext *dc, arg_r_r_r_r *a, return advance_pc(dc); } =20 +/* SHA helpers update fixed registers in the lower FPR bank. */ +static bool do_sha(DisasContext *dc, void (*func)(TCGv_env)) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + + func(tcg_env); + gen_update_fprs_dirty(dc, 0); + return advance_pc(dc); +} + TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist) TRANS(FMADDd, FMAF, do_dddd, a, gen_op_fmaddd) TRANS(FMSUBd, FMAF, do_dddd, a, gen_op_fmsubd) @@ -5440,6 +5456,9 @@ TRANS(AES_DROUND23_L, CRYPTO, do_dddd, a, gen_helper_= aes_dround23_l) TRANS(AES_KEXPAND0, CRYPTO, do_ddd, a, gen_helper_aes_kexpand0) TRANS(AES_KEXPAND2, CRYPTO, do_ddd, a, gen_helper_aes_kexpand2) TRANS(CRC32C, CRYPTO, do_ddd, a, gen_helper_crc32c) +TRANS(SHA1, CRYPTO, do_sha, gen_helper_sha1) +TRANS(SHA256, CRYPTO, do_sha, gen_helper_sha256) +TRANS(SHA512, CRYPTO, do_sha, gen_helper_sha512) =20 /* AES key expansion with RCON selected by the 5-bit immediate in imm */ static bool trans_AES_KEXPAND1(DisasContext *dc, arg_r_r_i_r *a) --=20 2.43.0 From nobody Fri Oct 23 21:32:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792652542845767.7166998271864; Thu, 22 Oct 2026 00:02:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJmoF-0002uu-F5; Thu, 22 Oct 2026 03:01:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJmnj-0002oM-MJ for qemu-devel@nongnu.org; Thu, 22 Oct 2026 03:01:25 -0400 Received: from itx-kvm-14.itxnorge.no ([91.189.121.228] helo=mx.itxnorge.no) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJmni-0005vo-3x for qemu-devel@nongnu.org; Thu, 22 Oct 2026 03:01:23 -0400 From: Stian Halseth DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=itx.no; s=mx.itx.no; t=1792652469; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vxriTHHowpsSZLR87NAuAdPjs7ttJqW/KlYeswRB0m4=; b=jZfs/dwOCTMpzIcE+gRmaUs6O6YMx57X5KG+R42on1A1Faon2ALVvp04TgGm9rwYxL63u0 nOLmjqVLv+mO+PkmV6j6V5Ih25wMCcXxmto0wSnMe8cXLS4LgRVCnCWp2PsCxLLXi2Icy0 VkpENjewdQ8vQlpNyLSswJ89TrZ+k2A= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Helge Deller , Pierrick Bouvier , Eric Biggers , Stian Halseth Subject: [PATCH v3 7/8] target/sparc: Allow block-init stores when the CPU has the crypto feature Date: Thu, 22 Oct 2026 09:00:58 +0200 Message-ID: <20261022070059.3861291-8-stian@itx.no> In-Reply-To: <20261022070059.3861291-1-stian@itx.no> References: <20261022070059.3861291-1-stian@itx.no> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=91.189.121.228; envelope-from=stian@itx.no; helo=mx.itxnorge.no X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @itx.no) X-ZM-MESSAGEID: 1792652545065158500 Content-Type: text/plain; charset="utf-8" The next patch reports HWCAP_SPARC_CRYPTO to linux-user guests. A multiarch glibc then picks its niagara4 memcpy/memset, which store with ASI 0xe2. QEMU only allows that store on CPUs with HYPV, so every dynamically linked program dies with SIGILL. The crypto opcodes exist only on T4 and later, and all of those have the block-init ASIs. Reproduced with Gentoo sparc64 stage3 sysroot: qemu-sparc64 -L -cpu \ TI-UltraSparc-IIi,+crypto /usr/bin/dd --version Signed-off-by: Stian Halseth Reviewed-by: Mark Cave-Ayland --- target/sparc/translate.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 921ffd2d1b..931fc006ce 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1863,8 +1863,12 @@ static void gen_st_asi(DisasContext *dc, DisasASI *d= a, TCGv src, TCGv addr) if (TARGET_LONG_BITS =3D=3D 32) { gen_exception(dc, TT_ILL_INSN); break; - } else if (!(dc->def->features & CPU_FEATURE_HYPV)) { - /* Pre OpenSPARC CPUs don't have these */ + } else if (!(dc->def->features & + (CPU_FEATURE_HYPV | CPU_FEATURE_CRYPTO))) { + /* + * Pre-OpenSPARC CPUs lack block-init stores. Crypto instructi= ons + * imply T4 or later, which supports them. + */ gen_exception(dc, TT_ILL_INSN); break; } --=20 2.43.0 From nobody Fri Oct 23 21:32:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=itx.no ARC-Seal: i=1; a=rsa-sha256; t=1792652590; cv=none; d=zohomail.com; s=zohoarc; b=dSm8MutfYyQ8DgGL5IzMvVuBuYGL9YKtFzYi38stwbEMLEW3b3UwDCLAb81tWBIRldVG4aJu0ngrNs6Qgk9OpnjSwm6r/XSgOf7G8u2ycCm160Lz0tb44gKrsql6P2pNlKt6F4Oc0Ev4NdDdJSmgvglnvmXNWlAwovNEjdKEsUI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792652590; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 22 Oct 2026 03:01:25 -0400 Received: from itx-kvm-14.itxnorge.no ([91.189.121.228] helo=mx.itxnorge.no) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJmni-0005vp-5E for qemu-devel@nongnu.org; Thu, 22 Oct 2026 03:01:23 -0400 From: Stian Halseth DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=itx.no; s=mx.itx.no; t=1792652469; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/hYWmxUkKZzPcn+f2QGYdFeMzebAT/dEKFc9UdyBWqA=; b=iw9JYJ7LX3OMF4PfHVswoU5zxDq75gUjShny98ZJMNZYx/H8j2SmqGkd5XCRmEQwgL/SIv LyDpcVK3HLCTOwCEaIQ3PohjYZU1RPGFrukJzKu0ycMWI0vxuKZZxABVkRbbFRLn2iYl8t tBgKsFfyFotOv85ayxwoQ0o4ly2WH54= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Helge Deller , Pierrick Bouvier , Eric Biggers , Stian Halseth Subject: [PATCH v3 8/8] linux-user/sparc: Report HWCAP_SPARC_CRYPTO for crypto CPU feature Date: Thu, 22 Oct 2026 09:00:59 +0200 Message-ID: <20261022070059.3861291-9-stian@itx.no> In-Reply-To: <20261022070059.3861291-1-stian@itx.no> References: <20261022070059.3861291-1-stian@itx.no> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=91.189.121.228; envelope-from=stian@itx.no; helo=mx.itxnorge.no X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @itx.no) X-ZM-MESSAGEID: 1792652591633158500 Set HWCAP_SPARC_CRYPTO in AT_HWCAP like Linux does on real hardware that supports it. qemu-sparc64 defaults to "TI UltraSparc II", which has no crypto feature, so it must be enabled explicitly, e.g. -cpu TI-UltraSparc-II,+crypto Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Stian Halseth Reviewed-by: Mark Cave-Ayland --- linux-user/sparc/elfload.c | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/sparc/elfload.c b/linux-user/sparc/elfload.c index 181f1e00b5..0412741285 100644 --- a/linux-user/sparc/elfload.c +++ b/linux-user/sparc/elfload.c @@ -90,6 +90,7 @@ abi_ulong get_elf_hwcap(CPUState *cs) r |=3D features & CPU_FEATURE_FMAF ? HWCAP_SPARC_FMAF : 0; r |=3D features & CPU_FEATURE_VIS3 ? HWCAP_SPARC_VIS3 : 0; r |=3D features & CPU_FEATURE_IMA ? HWCAP_SPARC_IMA : 0; + r |=3D features & CPU_FEATURE_CRYPTO ? HWCAP_SPARC_CRYPTO : 0; #endif =20 return r; --=20 2.43.0