Hi,
It's time for a refresher of the hwtrace/e-trace support for RISC-V. It
has been awhile since v3 and we have Konstantin posting patches to
implement N-trace on top of it.
For this new version a couple of design changes were made, most notably
the FDT functions are now hosted in fdt-common.c and we're using an
EXT_TB_FLAG to enable/disable the trace session instead of using a TCG
global.
A new patch was also added to describe what we're implementing and some
design decisions made w.r.t TCG instrumentation and encoder parameters.
This emulation is being used to support the development of the Linux RISC-V
e-trace driver framework. Newest version can be found here:
("[PATCH v6 00/14] Linux RISC-V trace framework and drivers")
https://lists.infradead.org/pipermail/linux-riscv/2026-September/100456.html
Patches based on alistair/riscv-to-apply.next.
Changes from v3:
- patch 5:
- move FDT creation code to fdt-common.c
- patch 7:
- move trace_helper.c to tcg subdir
- use "CPU_TRACE_RUNNING" EXT_TB_FLAG and ctx->cpu_trace_running for insn instrumentation
instead of using a TCG global
- patch 14:
- use ctx->cpu_trace_running in gen_trace_branch()
- patch 16:
- use ctx->cpu_trace_running in gen_trace_branch()
- patch 18 (new):
- add documentation
- v3 link: https://lore.kernel.org/qemu-devel/20251229184656.2224369-1-daniel.barboza@oss.qualcomm.com/
Daniel Henrique Barboza (18):
hw/riscv: Trace Encoder initial impl
hw/riscv: Trace RAM Sink initial impl
hw/riscv/trace-encoder: add trace start/stop logic
hw/riscv/virt.c: add trace encoders and trace ram sinks
hw/riscv/virt.c add trace encoder and ramsink fdt nodes
hw/riscv: add e-trace message helpers
target/riscv: add initial trace instrumentation
hw/riscv/trace-encoder: write e-trace packets to RAM sink
test/qtest: add riscv-trace-test.c
hw/riscv/rv-trace-messages.c: add encoded trap message
hw/riscv, target/riscv: send trace trap messages
target/riscv, hw/riscv: send trace ppccd packets
hw/riscv/trace: add format2 msg helper
hw/riscv, target/riscv: send resync updiscon trace packets
hw/riscv/rv-trace-messages: add format 1 msgs with branch info
hw/riscv/trace-encoder: send branches info
hw/riscv/trace: update branch bit in sync messages
docs/specs: document RISC-V hwtrace (e-trace) support
docs/specs/index.rst | 1 +
docs/specs/riscv-hwtrace.rst | 96 +++
hw/riscv/Kconfig | 5 +
hw/riscv/fdt-common.c | 70 ++
hw/riscv/meson.build | 3 +-
hw/riscv/rv-trace-messages.c | 373 +++++++++++
hw/riscv/rv-trace-messages.h | 40 ++
hw/riscv/trace-encoder.c | 610 ++++++++++++++++++
hw/riscv/trace-encoder.h | 62 ++
hw/riscv/trace-events | 9 +
hw/riscv/trace-ram-sink.c | 263 ++++++++
hw/riscv/trace-ram-sink.h | 83 +++
hw/riscv/virt.c | 128 ++++
include/hw/riscv/fdt-common.h | 4 +
include/hw/riscv/virt.h | 2 +
target/riscv/cpu.h | 12 +
target/riscv/helper.h | 6 +
target/riscv/tcg/cpu_helper.c | 26 +-
.../tcg/insn_trans/trans_privileged.c.inc | 11 +
target/riscv/tcg/insn_trans/trans_rvi.c.inc | 13 +
target/riscv/tcg/meson.build | 6 +
target/riscv/tcg/tcg-cpu.c | 9 +
target/riscv/tcg/trace_helper.c | 62 ++
target/riscv/tcg/translate.c | 16 +
tests/qtest/meson.build | 2 +-
tests/qtest/riscv-trace-test.c | 120 ++++
26 files changed, 2029 insertions(+), 3 deletions(-)
create mode 100644 docs/specs/riscv-hwtrace.rst
create mode 100644 hw/riscv/rv-trace-messages.c
create mode 100644 hw/riscv/rv-trace-messages.h
create mode 100644 hw/riscv/trace-encoder.c
create mode 100644 hw/riscv/trace-encoder.h
create mode 100644 hw/riscv/trace-ram-sink.c
create mode 100644 hw/riscv/trace-ram-sink.h
create mode 100644 target/riscv/tcg/trace_helper.c
create mode 100644 tests/qtest/riscv-trace-test.c
--
2.43.0