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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624635326158500 Content-Type: text/plain; charset="utf-8" The Trace Encoder is a hardware module that interacts with a CPU, gathering execution information (a.k.a instruction delta trace), and send it downstream to other storage components such as a RAM Sink (a RAM storage). This trace info can then be read via software (e.g. perf) to reproduce the behavior of a given binary that ran in the CPU. This implementation is based on the Efficient Trace for RISC-V [1] and RISC-V Trace Control Interface Specification [2]. It's not intended to implement all spec features: the idea is to provide a base where we can add extra features on demand. We'll get back to the instruction delta trace and how we'll instrument TCG to produce it later. For now we'll set the minimal components to get the basic framework running. This Trace Encoder impl has just the minimal bits specified in [2], section "Minimal Implementation". RO and RSVP bits are taken verbatim from [2] without considering what we're actually going to support. The base impl is heavily inspired by the XLNZ-ZDMA device w.r.t the usage of the RegisterInfo and register.h framework. Discovery of the Trace Encoder will be made via fdt, a single entry per CPU. We'll connect each Trace Encoder to its CPU in the 'virt' board later. [1] https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.= 0-20250616/riscv-trace-spec-asciidoc.pdf [2] https://github.com/riscv-non-isa/tg-nexus-trace/releases/download/1.0_R= atified/RISC-V-Trace-Control-Interface.pdf Signed-off-by: Daniel Henrique Barboza --- hw/riscv/Kconfig | 5 + hw/riscv/meson.build | 2 +- hw/riscv/trace-encoder.c | 216 +++++++++++++++++++++++++++++++++++++++ hw/riscv/trace-encoder.h | 42 ++++++++ hw/riscv/trace-events | 4 + 5 files changed, 268 insertions(+), 1 deletion(-) create mode 100644 hw/riscv/trace-encoder.c create mode 100644 hw/riscv/trace-encoder.h diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index fb05031228..9f241d1273 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -7,6 +7,10 @@ config RISCV_NUMA config IBEX bool =20 +config RISCV_TRACE + bool + select REGISTER + # RISC-V machines in alphabetical order =20 config MICROCHIP_PFSOC @@ -68,6 +72,7 @@ config RISCV_VIRT select PLATFORM_BUS select ACPI select ACPI_PCI + select RISCV_TRACE =20 config RISCV_SERVER_PLATFORM_REF bool diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 6bdabb9544..1238cb3e1a 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -22,7 +22,7 @@ riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true:= files('xiangshan_kmh.c riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c')) riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'= )) riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c')) - +riscv_ss.add(when: 'CONFIG_RISCV_TRACE', if_true: files('trace-encoder.c')) riscv_ss.add(when: 'CONFIG_SOPHGO_CV1800B', if_true: files('cv1800b.c')) riscv_ss.add(when: 'CONFIG_MILKV_DUO', if_true: files('milkv_duo.c')) =20 diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c new file mode 100644 index 0000000000..19ab785334 --- /dev/null +++ b/hw/riscv/trace-encoder.c @@ -0,0 +1,216 @@ +/* + * Emulation of a RISC-V Trace Encoder + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "trace-encoder.h" +#include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "trace.h" +#include "system/device_tree.h" +#include "hw/core/register.h" +#include "cpu.h" + +/* + * trTeControl register fields + */ +REG32(TR_TE_CONTROL, 0x0) + FIELD(TR_TE_CONTROL, ACTIVE, 0, 1) + FIELD(TR_TE_CONTROL, ENABLE, 1, 1) + FIELD(TR_TE_CONTROL, INST_TRACING, 2, 1) + FIELD(TR_TE_CONTROL, EMPTY, 3, 1) + FIELD(TR_TE_CONTROL, INST_MODE, 4, 3) + FIELD(TR_TE_CONTROL, INST_SYNC_MODE, 16, 2) + FIELD(TR_TE_CONTROL, FORMAT, 24, 3) + /* reserved bits */ + FIELD(TR_TE_CONTROL, RSVP1, 7, 2) + FIELD(TR_TE_CONTROL, RSVP2, 10, 1) + FIELD(TR_TE_CONTROL, RSVP3, 14, 1) + FIELD(TR_TE_CONTROL, RSVP4, 18, 2) + FIELD(TR_TE_CONTROL, RSVP5, 27, 4) + +#define R_TR_TE_CONTROL_RSVP_BITS (MAKE_64BIT_MASK(32, 32) | \ + R_TR_TE_CONTROL_RSVP1_MASK | \ + R_TR_TE_CONTROL_RSVP2_MASK | \ + R_TR_TE_CONTROL_RSVP3_MASK | \ + R_TR_TE_CONTROL_RSVP4_MASK | \ + R_TR_TE_CONTROL_RSVP5_MASK) + +/* trTeControlEmpty is the only RO field and reset value */ +#define R_TR_TE_CONTROL_RESET R_TR_TE_CONTROL_EMPTY_MASK +#define R_TR_TE_CONTROL_RO_BITS R_TR_TE_CONTROL_EMPTY_MASK + +/* + * trTeImpl register fields + */ +REG32(TR_TE_IMPL, 0x4) + FIELD(TR_TE_IMPL, VER_MAJOR, 0, 4) + FIELD(TR_TE_IMPL, VER_MINOR, 4, 4) + FIELD(TR_TE_IMPL, COMP_TYPE, 8, 4) + FIELD(TR_TE_IMPL, PROTOCOL_MAJOR, 16, 4) + FIELD(TR_TE_IMPL, PROTOCOL_MINOR, 20, 4) + /* reserved bits */ + FIELD(TR_TE_IMPL, RSVP1, 12, 4) + FIELD(TR_TE_IMPL, RSVP2, 24, 8) + +#define R_TR_TE_IMPL_RSVP_BITS (MAKE_64BIT_MASK(32, 32) | \ + R_TR_TE_IMPL_RSVP1_MASK | \ + R_TR_TE_IMPL_RSVP2_MASK) + +#define R_TR_TE_IMPL_RO_BITS (R_TR_TE_IMPL_VER_MAJOR_MASK | \ + R_TR_TE_IMPL_VER_MINOR_MASK | \ + R_TR_TE_IMPL_COMP_TYPE_MASK | \ + R_TR_TE_IMPL_PROTOCOL_MAJOR_MASK | \ + R_TR_TE_IMPL_PROTOCOL_MINOR_MASK) + +#define R_TR_TE_IMPL_RESET (BIT(0) | BIT(8)) + +static RegisterAccessInfo trencoder_regs_info[] =3D { + { .name =3D "TR_TE_CONTROL", .addr =3D A_TR_TE_CONTROL, + .rsvd =3D R_TR_TE_CONTROL_RSVP_BITS, + .reset =3D R_TR_TE_CONTROL_RESET, + .ro =3D R_TR_TE_CONTROL_RO_BITS, + }, + { .name =3D "TR_TE_IMPL", .addr =3D A_TR_TE_IMPL, + .rsvd =3D R_TR_TE_IMPL_RSVP_BITS, + .reset =3D R_TR_TE_IMPL_RESET, + .ro =3D R_TR_TE_IMPL_RO_BITS, + }, +}; + +static uint64_t trencoder_read(void *opaque, hwaddr addr, unsigned size) +{ + TraceEncoder *te =3D TRACE_ENCODER(opaque); + RegisterInfo *r =3D &te->regs_info[addr / 4]; + + if (!r->data) { + trace_trencoder_read_error(addr); + return 0; + } + + return register_read(r, ~0, NULL, false); +} + +static void trencoder_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + TraceEncoder *te =3D TRACE_ENCODER(opaque); + RegisterInfo *r =3D &te->regs_info[addr / 4]; + + if (!r->data) { + trace_trencoder_write_error(addr, value); + return; + } + + register_write(r, value, ~0, NULL, false); +} + +static const MemoryRegionOps trencoder_ops =3D { + .read =3D trencoder_read, + .write =3D trencoder_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void trencoder_reset(DeviceState *dev) +{ + TraceEncoder *te =3D TRACE_ENCODER(dev); + + for (int i =3D 0; i < ARRAY_SIZE(te->regs_info); i++) { + register_reset(&te->regs_info[i]); + } +} + +static void trencoder_realize(DeviceState *dev, Error **errp) +{ + TraceEncoder *te =3D TRACE_ENCODER(dev); + + memory_region_init_io(&te->reg_mem, OBJECT(dev), + &trencoder_ops, te, + TYPE_TRACE_ENCODER, + te->reg_mem_size); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &te->reg_mem); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, te->baseaddr); + + /* RegisterInfo init taken from hw/dma/xlnx-zdma.c */ + for (int i =3D 0; i < ARRAY_SIZE(trencoder_regs_info); i++) { + uint32_t reg_idx =3D trencoder_regs_info[i].addr / 4; + RegisterInfo *r =3D &te->regs_info[reg_idx]; + + *r =3D (RegisterInfo) { + .data =3D (uint8_t *)&te->regs[reg_idx], + .data_size =3D sizeof(uint32_t), + .access =3D &trencoder_regs_info[i], + .opaque =3D te, + }; + } +} + +static const Property trencoder_props[] =3D { + /* + * We need a link to the associated CPU to + * enable/disable tracing. + */ + DEFINE_PROP_LINK("cpu", TraceEncoder, cpu, TYPE_RISCV_CPU, RISCVCPU *), + DEFINE_PROP_UINT64("baseaddr", TraceEncoder, baseaddr, 0), + DEFINE_PROP_UINT64("dest-baseaddr", TraceEncoder, dest_baseaddr, 0), + DEFINE_PROP_UINT64("ramsink-ramstart", TraceEncoder, + ramsink_ramstart, 0), + DEFINE_PROP_UINT64("ramsink-ramlimit", TraceEncoder, + ramsink_ramlimit, 0), + DEFINE_PROP_UINT32("reg-mem-size", TraceEncoder, + reg_mem_size, TRACE_R_MAX * 4), + DEFINE_PROP_INT32("cpu-id", TraceEncoder, cpu_id, 0), +}; + +static const VMStateDescription vmstate_trencoder =3D { + .name =3D TYPE_TRACE_ENCODER, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, TraceEncoder, TRACE_R_MAX), + VMSTATE_UINT64(baseaddr, TraceEncoder), + VMSTATE_UINT64(dest_baseaddr, TraceEncoder), + VMSTATE_UINT64(ramsink_ramstart, TraceEncoder), + VMSTATE_UINT64(ramsink_ramlimit, TraceEncoder), + VMSTATE_INT32(cpu_id, TraceEncoder), + VMSTATE_END_OF_LIST(), + } +}; + +static void trencoder_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_legacy_reset(dc, trencoder_reset); + device_class_set_props(dc, trencoder_props); + dc->realize =3D trencoder_realize; + dc->vmsd =3D &vmstate_trencoder; +} + +static const TypeInfo trencoder_info =3D { + .name =3D TYPE_TRACE_ENCODER, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(TraceEncoder), + .class_init =3D trencoder_class_init, +}; + +static void trencoder_register_types(void) +{ + type_register_static(&trencoder_info); +} + +type_init(trencoder_register_types) diff --git a/hw/riscv/trace-encoder.h b/hw/riscv/trace-encoder.h new file mode 100644 index 0000000000..8978865663 --- /dev/null +++ b/hw/riscv/trace-encoder.h @@ -0,0 +1,42 @@ +/* + * Emulation of a RISC-V Trace Encoder + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef RISCV_TRACE_ENCODER_H +#define RISCV_TRACE_ENCODER_H + +#include "hw/core/sysbus.h" +#include "hw/core/register.h" +#include "system/dma.h" +#include "qom/object.h" +#include "cpu.h" + +#define TRACE_R_MAX (0xFFF / 4) + +struct TraceEncoder { + /*< private >*/ + SysBusDevice parent_obj; + + RISCVCPU *cpu; + int cpu_id; + + MemoryRegion reg_mem; + uint32_t reg_mem_size; + + hwaddr baseaddr; + hwaddr dest_baseaddr; + hwaddr ramsink_ramstart; + hwaddr ramsink_ramlimit; + uint32_t regs[TRACE_R_MAX]; + RegisterInfo regs_info[TRACE_R_MAX]; +}; + +#define TYPE_TRACE_ENCODER "trace-encoder" + +OBJECT_DECLARE_SIMPLE_TYPE(TraceEncoder, TRACE_ENCODER) + +#endif diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events index b50b14a654..0cbf6ffcb6 100644 --- a/hw/riscv/trace-events +++ b/hw/riscv/trace-events @@ -24,3 +24,7 @@ riscv_iommu_hpm_incr_ctr(uint64_t cntr_val) "cntr_val 0x%= "PRIx64 riscv_iommu_hpm_iocntinh_cy(bool prev_cy_inh) "prev_cy_inh %d" riscv_iommu_hpm_cycle_write(uint32_t ovf, uint64_t val) "ovf 0x%x val 0x%"= PRIx64 riscv_iommu_hpm_evt_write(uint32_t ctr_idx, uint32_t ovf, uint64_t val) "c= tr_idx 0x%x ovf 0x%x val 0x%"PRIx64 + +# trace-encoder.c +trencoder_read_error(uint64_t addr) "addr 0x%" PRIx64 +trencoder_write_error(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " v= alue 0x%" PRIx64 --=20 2.43.0 From nobody Fri Oct 23 21:01:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 21 Oct 2026 16:14:05 -0700 (PDT) X-Received: by 2002:ac8:7f45:0:b0:536:6ff1:7568 with SMTP id d75a77b69052e-5369b889a2emr55189481cf.60.1792624445112; Wed, 21 Oct 2026 16:14:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, antikostya2@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH v4 02/18] hw/riscv: Trace RAM Sink initial impl Date: Wed, 21 Oct 2026 20:13:29 -0300 Message-ID: <20261021231346.2452179-3-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261021231346.2452179-1-daniel.barboza@oss.qualcomm.com> References: <20261021231346.2452179-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=C9Z8WgP+ c=1 sm=1 tr=0 ts=6ad9473e cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=QmVDPCq3bE4LYXGvZ20s0w==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=V1jnuoLLAAAA:20 a=EUspDBNiAAAA:8 a=aqjgF2fw9fj3PC3FA9IA:9 a=uxP6HrT_eTzRwkO_Te1X:22 a=bA3UWDv6hWIuX7UZL3qL:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA5MiBTYWx0ZWRfX+xitMlnUkO/+ JfYlQmkWwX5cxrfQELhTxJ1fwNSVGGDBaZbhxOTovPbFuv3E+QCNIFa9tXqWRgQ6CkA8O+dVaXX yXemzUFkzxfgEbZoqEjgL9OPKJyMk+0= X-Proofpoint-GUID: IiAGTcxIuaCMYTOaXCVAhckI4MH8E4rp X-Proofpoint-ORIG-GUID: IiAGTcxIuaCMYTOaXCVAhckI4MH8E4rp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA5MiBTYWx0ZWRfX0/trRIHirbMn H4XsheSICbosYxs4YpZzuBWzeHkA/iHQRk4AknPUtnjFqPLl5lI7UU9hj91UsLQJEAqHJt5QI2n vbVCzy85ZUn3dRxFoNtbcjQgVSeua/OcvPrw7npdCuQ0EH2aZ00P7zmyciVbU69x0JXuUTY6hvr iiX9JvfgPoVqAHU1e6o1aTUC1FGcnEp5nfIkw5tiDg/MjEgSxEy08dwnGJxi8j85NZ/0CiYgU4y aE6qzL40HHbpzDjOJcbR5Dys8n4Ncq/xhUKn5XSckp4lGHKwN7G3j0CZIWORSmtbqEbyhrpI5u8 Jw6kJTUq4podpIhVt0G8sp3k300Yt/d1BnwA6ezR8XYpuT9pf08YZsnmm2dED83FSBRyuK0goCv hYmBHzpTa855Tbpr7MJRryY4jXociQjYVyTpMfVN9w6B2R6Wz0bBh4UV7Pq8MHEKLiBvSD6r/st DfKNdBDkGHzAJtbFXSg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 suspectscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210092 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624610854158500 Content-Type: text/plain; charset="utf-8" Following the effort to implement the basic support for Efficient Trace (e-trace) in QEMU we'll add a Trace RAM Sink implementation. Similar to the Trace Encoder, this is inspired in both the Efficient Trace for RISC-V [1] and RISC-V Trace Control Interface Specification [2] specs. It implements a minimal set of features to get started - only SMEM will be supported for now. We'll implement the RAM sink logic in the next patches, although most of the work will be done by the trace encoder. [1] https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.= 0-20250616/riscv-trace-spec-asciidoc.pdf [2] https://github.com/riscv-non-isa/tg-nexus-trace/releases/download/1.0_R= atified/RISC-V-Trace-Control-Interface.pdf Signed-off-by: Daniel Henrique Barboza --- hw/riscv/meson.build | 2 +- hw/riscv/trace-events | 4 + hw/riscv/trace-ram-sink.c | 263 ++++++++++++++++++++++++++++++++++++++ hw/riscv/trace-ram-sink.h | 83 ++++++++++++ 4 files changed, 351 insertions(+), 1 deletion(-) create mode 100644 hw/riscv/trace-ram-sink.c create mode 100644 hw/riscv/trace-ram-sink.h diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 1238cb3e1a..97a39f85f9 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -22,7 +22,7 @@ riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true:= files('xiangshan_kmh.c riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c')) riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'= )) riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c')) -riscv_ss.add(when: 'CONFIG_RISCV_TRACE', if_true: files('trace-encoder.c')) +riscv_ss.add(when: 'CONFIG_RISCV_TRACE', if_true: files('trace-encoder.c',= 'trace-ram-sink.c')) riscv_ss.add(when: 'CONFIG_SOPHGO_CV1800B', if_true: files('cv1800b.c')) riscv_ss.add(when: 'CONFIG_MILKV_DUO', if_true: files('milkv_duo.c')) =20 diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events index 0cbf6ffcb6..14e333fd9e 100644 --- a/hw/riscv/trace-events +++ b/hw/riscv/trace-events @@ -28,3 +28,7 @@ riscv_iommu_hpm_evt_write(uint32_t ctr_idx, uint32_t ovf,= uint64_t val) "ctr_idx # trace-encoder.c trencoder_read_error(uint64_t addr) "addr 0x%" PRIx64 trencoder_write_error(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " v= alue 0x%" PRIx64 + +# trace-ram-sink.c +tr_ramsink_read_error(uint64_t addr) "addr 0x%" PRIx64 +tr_ramsink_write_error(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " = value 0x%" PRIx64 diff --git a/hw/riscv/trace-ram-sink.c b/hw/riscv/trace-ram-sink.c new file mode 100644 index 0000000000..33d033b72e --- /dev/null +++ b/hw/riscv/trace-ram-sink.c @@ -0,0 +1,263 @@ +/* + * Emulation of a RISC-V Trace RAM Sink + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "trace-ram-sink.h" +#include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" +#include "migration/vmstate.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "trace.h" +#include "system/device_tree.h" +#include "hw/core/sysbus.h" +#include "hw/core/register.h" + +#define R_TR_RAM_CONTROL_RSVP_BITS (MAKE_64BIT_MASK(32, 32) | \ + R_TR_RAM_CONTROL_RSVP1_MASK | \ + R_TR_RAM_CONTROL_RSVP2_MASK | \ + R_TR_RAM_CONTROL_RSVP3_MASK | \ + R_TR_RAM_CONTROL_RSVP4_MASK) + +/* trRamEmpty is the only RO field and reset value */ +#define R_TR_RAM_CONTROL_RESET R_TR_RAM_CONTROL_EMPTY_MASK +#define R_TR_RAM_CONTROL_RO_BITS R_TR_RAM_CONTROL_EMPTY_MASK + +#define R_TR_RAM_IMPL_RSVP_BITS (MAKE_64BIT_MASK(32, 32) | \ + R_TR_RAM_IMPL_RSVP1_MASK) + +#define R_TR_RAM_IMPL_RO_BITS (R_TR_RAM_IMPL_VER_MAJOR_MASK | \ + R_TR_RAM_IMPL_VER_MINOR_MASK | \ + R_TR_RAM_IMPL_COMP_TYPE_MASK | \ + R_TR_RAM_IMPL_HAS_SRAM_MASK | \ + R_TR_RAM_IMPL_HAS_SMEM_MASK) + +#define R_TR_RAM_IMPL_RESET (BIT(0) | 0x9 << 8) + +static RegisterAccessInfo tr_ramsink_regs_info[] =3D { + { .name =3D "TR_RAM_CONTROL", .addr =3D A_TR_RAM_CONTROL, + .rsvd =3D R_TR_RAM_CONTROL_RSVP_BITS, + .reset =3D R_TR_RAM_CONTROL_RESET, + .ro =3D R_TR_RAM_CONTROL_RO_BITS, + }, + { .name =3D "TR_RAM_IMPL", .addr =3D A_TR_RAM_IMPL, + .rsvd =3D R_TR_RAM_IMPL_RSVP_BITS, + .reset =3D R_TR_RAM_IMPL_RESET, + .ro =3D R_TR_RAM_IMPL_RO_BITS, + }, + { .name =3D "TR_RAM_START_LOW", .addr =3D A_TR_RAM_START_LOW, + }, + { .name =3D "TR_RAM_START_HIGH", .addr =3D A_TR_RAM_START_HIGH, + }, + { .name =3D "TR_RAM_LIMIT_LOW", .addr =3D A_TR_RAM_LIMIT_LOW, + }, + { .name =3D "TR_RAM_LIMIT_HIGH", .addr =3D A_TR_RAM_LIMIT_HIGH, + }, + { .name =3D "TR_RAM_WP_LOW", .addr =3D A_TR_RAM_WP_LOW, + }, + { .name =3D "TR_RAM_WP_HIGH", .addr =3D A_TR_RAM_WP_HIGH, + }, +}; + +static uint64_t tr_ramsink_regread(void *opaque, hwaddr addr, unsigned siz= e) +{ + TraceRamSink *tram =3D TRACE_RAM_SINK(opaque); + RegisterInfo *r =3D &tram->regs_info[addr / 4]; + + if (!r->data) { + trace_tr_ramsink_read_error(addr); + return 0; + } + + return register_read(r, ~0, NULL, false); +} + +static void tr_ramsink_regwrite(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + TraceRamSink *tram =3D TRACE_RAM_SINK(opaque); + RegisterInfo *r =3D &tram->regs_info[addr / 4]; + + if (!r->data) { + trace_tr_ramsink_write_error(addr, value); + return; + } + + register_write(r, value, ~0, NULL, false); +} + +static const MemoryRegionOps tr_ramsink_regops =3D { + .read =3D tr_ramsink_regread, + .write =3D tr_ramsink_regwrite, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static uint64_t tr_ramsink_msgread(void *opaque, hwaddr addr, unsigned siz= e) +{ + TraceRamSink *tram =3D TRACE_RAM_SINK(opaque); + + switch (size) { + case 1: + return tram->msgs[addr]; + case 2: + return (uint16_t)tram->msgs[addr]; + case 4: + return (uint32_t)tram->msgs[addr]; + default: + g_assert_not_reached(); + } +} + +static void tr_ramsink_msgwrite(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + TraceRamSink *tram =3D TRACE_RAM_SINK(opaque); + + switch (size) { + case 1: + tram->msgs[addr] =3D value; + break; + case 2: + tram->msgs[addr] =3D extract16(value, 0, 8); + tram->msgs[addr + 1] =3D extract16(value, 8, 8); + break; + case 4: + tram->msgs[addr] =3D extract32(value, 0, 8); + tram->msgs[addr + 1] =3D extract32(value, 8, 8); + tram->msgs[addr + 2] =3D extract32(value, 16, 8); + tram->msgs[addr + 3] =3D extract32(value, 24, 8); + break; + default: + g_assert_not_reached(); + } +} + +static const MemoryRegionOps tr_ramsink_smemops =3D { + .read =3D tr_ramsink_msgread, + .write =3D tr_ramsink_msgwrite, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 4, + }, +}; + +static void tr_ramsink_setup_regs(TraceRamSink *tram) +{ + hwaddr ramlimit =3D tram->smemaddr + tram->smemsize; + + ARRAY_FIELD_DP32(tram->regs, TR_RAM_START_LOW, ADDR, + extract64(tram->smemaddr, 2, 30)); + ARRAY_FIELD_DP32(tram->regs, TR_RAM_START_HIGH, ADDR, + extract64(tram->smemaddr, 32, 32)); + + ARRAY_FIELD_DP32(tram->regs, TR_RAM_WP_LOW, ADDR, + extract64(tram->smemaddr, 2, 30)); + ARRAY_FIELD_DP32(tram->regs, TR_RAM_WP_HIGH, ADDR, + extract64(tram->smemaddr, 32, 32)); + + ARRAY_FIELD_DP32(tram->regs, TR_RAM_LIMIT_LOW, ADDR, + extract64(ramlimit, 2, 30)); + ARRAY_FIELD_DP32(tram->regs, TR_RAM_LIMIT_HIGH, ADDR, + extract64(ramlimit, 32, 32)); +} + +static void tr_ramsink_reset(DeviceState *dev) +{ + TraceRamSink *tram =3D TRACE_RAM_SINK(dev); + + for (int i =3D 0; i < ARRAY_SIZE(tram->regs_info); i++) { + register_reset(&tram->regs_info[i]); + } + + tr_ramsink_setup_regs(tram); +} + +static void tr_ramsink_realize(DeviceState *dev, Error **errp) +{ + TraceRamSink *tram =3D TRACE_RAM_SINK(dev); + + memory_region_init_io(&tram->reg_mem, OBJECT(dev), + &tr_ramsink_regops, tram, + "trace-ram-sink-regs", + tram->reg_mem_size); + sysbus_init_mmio(SYS_BUS_DEVICE(tram), &tram->reg_mem); + sysbus_mmio_map(SYS_BUS_DEVICE(tram), 0, tram->baseaddr); + + g_assert(tram->smemsize > 0); + tram->msgs =3D g_malloc0(tram->smemsize); + + memory_region_init_io(&tram->smem, OBJECT(dev), + &tr_ramsink_smemops, tram, + "trace-ram-sink-smem", + tram->smemsize); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &tram->smem); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, tram->smemaddr); + + /* RegisterInfo init taken from hw/dma/xlnx-zdma.c */ + for (int i =3D 0; i < ARRAY_SIZE(tr_ramsink_regs_info); i++) { + uint32_t reg_idx =3D tr_ramsink_regs_info[i].addr / 4; + RegisterInfo *r =3D &tram->regs_info[reg_idx]; + + *r =3D (RegisterInfo) { + .data =3D (uint8_t *)&tram->regs[reg_idx], + .data_size =3D sizeof(uint32_t), + .access =3D &tr_ramsink_regs_info[i], + .opaque =3D tram, + }; + } +} + +static const Property tr_ramsink_props[] =3D { + DEFINE_PROP_UINT64("baseaddr", TraceRamSink, baseaddr, 0), + DEFINE_PROP_UINT64("smemaddr", TraceRamSink, smemaddr, 0), + DEFINE_PROP_UINT32("smemsize", TraceRamSink, smemsize, 0), + DEFINE_PROP_UINT32("reg-mem-size", TraceRamSink, + reg_mem_size, TR_DEV_REGMAP_SIZE), +}; + +static const VMStateDescription vmstate_tr_ramsink =3D { + .name =3D TYPE_TRACE_RAM_SINK, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, TraceRamSink, TRACE_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void tr_ramsink_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_legacy_reset(dc, tr_ramsink_reset); + device_class_set_props(dc, tr_ramsink_props); + dc->realize =3D tr_ramsink_realize; + dc->vmsd =3D &vmstate_tr_ramsink; +} + +static const TypeInfo tr_ramsink_info =3D { + .name =3D TYPE_TRACE_RAM_SINK, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(TraceRamSink), + .class_init =3D tr_ramsink_class_init, +}; + +static void tr_ramsink_register_types(void) +{ + type_register_static(&tr_ramsink_info); +} + +type_init(tr_ramsink_register_types) diff --git a/hw/riscv/trace-ram-sink.h b/hw/riscv/trace-ram-sink.h new file mode 100644 index 0000000000..99e49496df --- /dev/null +++ b/hw/riscv/trace-ram-sink.h @@ -0,0 +1,83 @@ +/* + * Emulation of a RISC-V Trace RAM Sink + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef RISCV_TRACE_RAM_SINK_H +#define RISCV_TRACE_RAM_SINK_H + +#include "hw/core/register.h" +#include "hw/core/sysbus.h" +#include "system/dma.h" +#include "qom/object.h" + +#define TRACE_R_MAX (0xFFF / 4) +#define TR_DEV_REGMAP_SIZE 0x1000 + +/* + * The Trace Encoder will read/write those regs so put their + * declaration in this header. + */ +REG32(TR_RAM_CONTROL, 0x0) + FIELD(TR_RAM_CONTROL, ACTIVE, 0, 1) + FIELD(TR_RAM_CONTROL, ENABLE, 1, 1) + FIELD(TR_RAM_CONTROL, EMPTY, 3, 1) + FIELD(TR_RAM_CONTROL, MODE, 4, 1) + FIELD(TR_RAM_CONTROL, STOP_ON_WRAP, 8, 1) + FIELD(TR_RAM_CONTROL, MEM_FORMAT, 9, 2) + /* reserved bits */ + FIELD(TR_RAM_CONTROL, RSVP1, 2, 1) + FIELD(TR_RAM_CONTROL, RSVP2, 5, 2) + FIELD(TR_RAM_CONTROL, RSVP3, 11, 1) + FIELD(TR_RAM_CONTROL, RSVP4, 15, 16) + +REG32(TR_RAM_IMPL, 0x4) + FIELD(TR_RAM_IMPL, VER_MAJOR, 0, 4) + FIELD(TR_RAM_IMPL, VER_MINOR, 4, 4) + FIELD(TR_RAM_IMPL, COMP_TYPE, 8, 4) + FIELD(TR_RAM_IMPL, HAS_SRAM, 12, 1) + FIELD(TR_RAM_IMPL, HAS_SMEM, 13, 1) + /* reserved bits */ + FIELD(TR_RAM_IMPL, RSVP1, 14, 18) + +REG32(TR_RAM_START_LOW, 0x010) + FIELD(TR_RAM_START_LOW, ADDR, 2, 30) +REG32(TR_RAM_START_HIGH, 0x014) + FIELD(TR_RAM_START_HIGH, ADDR, 0, 32) + +REG32(TR_RAM_LIMIT_LOW, 0x018) + FIELD(TR_RAM_LIMIT_LOW, ADDR, 2, 30) +REG32(TR_RAM_LIMIT_HIGH, 0x01C) + FIELD(TR_RAM_LIMIT_HIGH, ADDR, 0, 32) + +REG32(TR_RAM_WP_LOW, 0x020) + FIELD(TR_RAM_WP_LOW, WRAP, 0, 1) + FIELD(TR_RAM_WP_LOW, ADDR, 2, 30) +REG32(TR_RAM_WP_HIGH, 0x024) + FIELD(TR_RAM_WP_HIGH, ADDR, 0, 32) + +struct TraceRamSink { + /*< private >*/ + SysBusDevice parent_obj; + + MemoryRegion reg_mem; + uint32_t reg_mem_size; + + hwaddr baseaddr; + uint32_t regs[TRACE_R_MAX]; + RegisterInfo regs_info[TRACE_R_MAX]; + + hwaddr smemaddr; + MemoryRegion smem; + uint32_t smemsize; + uint8_t *msgs; +}; + +#define TYPE_TRACE_RAM_SINK "trace-ram-sink" + +OBJECT_DECLARE_SIMPLE_TYPE(TraceRamSink, TRACE_RAM_SINK) + +#endif --=20 2.43.0 From nobody Fri Oct 23 21:01:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792624474; cv=none; d=zohomail.com; s=zohoarc; b=dV2e19J3tStlmu5lF6D1UMnQkkkAf9dcS0MGVx8k1amnmhWm24UI7WrJhf1mjkrurkQzp/rE6fPQ73EvV9hlhycwE8assU9UhHysQEn8X/ZX1JBkDBmdZi409/FHoVhvaDxZ9oa/I/riD+iHgW0BODsKY99r38ua5guJGsVTd+M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624476568158500 Content-Type: text/plain; charset="utf-8" Starting/stopping a trace session will rely on two flags: - trace_next_insn: this flag will be used to signal the translation that the encoder wants to know the PC of the current insn. The translation helper (to be added) will clear this flag after sending the current insn to the encoder; - trace_running: shows that we're running a trace session and certain insns classes (traps, certain jumps and branches) need to report to the trace encoder. These flags are controlled by the trTeInstTracing bit. This bit requires other two bits to be set beforehand (ACTIVE and ENABLE). We'll revisit these bits in the future as more features are implemented. While we're at it, add hardwire bits to indicate which features we're (not) implementing at this time. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/trace-encoder.c | 107 +++++++++++++++++++++++++++++++++++++++ hw/riscv/trace-encoder.h | 4 ++ 2 files changed, 111 insertions(+) diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c index 19ab785334..99399a55e1 100644 --- a/hw/riscv/trace-encoder.c +++ b/hw/riscv/trace-encoder.c @@ -30,7 +30,11 @@ REG32(TR_TE_CONTROL, 0x0) FIELD(TR_TE_CONTROL, INST_TRACING, 2, 1) FIELD(TR_TE_CONTROL, EMPTY, 3, 1) FIELD(TR_TE_CONTROL, INST_MODE, 4, 3) + FIELD(TR_TE_CONTROL, CONTEXT, 9, 1) + FIELD(TR_TE_CONTROL, INST_STALL_ENA, 13, 1) + FIELD(TR_TE_CONTROL, INHIBIT_SRC, 15, 1) FIELD(TR_TE_CONTROL, INST_SYNC_MODE, 16, 2) + FIELD(TR_TE_CONTROL, INST_SYNC_MAX, 20, 4) FIELD(TR_TE_CONTROL, FORMAT, 24, 3) /* reserved bits */ FIELD(TR_TE_CONTROL, RSVP1, 7, 2) @@ -75,17 +79,116 @@ REG32(TR_TE_IMPL, 0x4) =20 #define R_TR_TE_IMPL_RESET (BIT(0) | BIT(8)) =20 +REG32(TR_TE_INST_FEATURES, 0x8) + FIELD(TR_TE_INST_FEATURES, NO_ADDR_DIFF, 0, 1) + +static uint64_t trencoder_te_ctrl_set_hardwire_vals(uint64_t input) +{ + input =3D FIELD_DP32(input, TR_TE_CONTROL, INST_MODE, 0x6); + input =3D FIELD_DP32(input, TR_TE_CONTROL, CONTEXT, 0); + input =3D FIELD_DP32(input, TR_TE_CONTROL, INST_STALL_ENA, 0); + input =3D FIELD_DP32(input, TR_TE_CONTROL, INHIBIT_SRC, 1); + input =3D FIELD_DP32(input, TR_TE_CONTROL, FORMAT, 0); + + /* SYNC_MODE and SYNC_MAX will be revisited */ + input =3D FIELD_DP32(input, TR_TE_CONTROL, INST_SYNC_MODE, 0); + input =3D FIELD_DP32(input, TR_TE_CONTROL, INST_SYNC_MAX, 0); + + return input; +} + +static uint64_t trencoder_te_ctrl_prew(RegisterInfo *reg, uint64_t val) +{ + TraceEncoder *te =3D TRACE_ENCODER(reg->opaque); + uint32_t trTeActive =3D ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, ACTI= VE); + uint32_t trTeInstTracing =3D ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, + INST_TRACING); + uint32_t temp; + + val =3D trencoder_te_ctrl_set_hardwire_vals(val); + + if (!trTeActive) { + /* + * 11.2 Reset and discovery, table 58, trTeControl =3D 0x1 + * means "Release from reset and set all defaults." Do + * that only if trTeActive is 0. + */ + if (val =3D=3D 0x1) { + val =3D FIELD_DP32(val, TR_TE_CONTROL, EMPTY, 1); + + return val; + } + + /* + * 11.3 Enabling and Disabling hints that the device must + * be activated first (trTeActive =3D 1), then enabled. + * Do not enable the device if it's not active + * beforehand. + */ + temp =3D FIELD_EX32(val, TR_TE_CONTROL, ENABLE); + if (temp) { + val =3D FIELD_DP32(val, TR_TE_CONTROL, ENABLE, 0); + } + } + + /* + * Do not allow inst tracing to start if the device isn't + * already enabled. Do not allow enabling the devince and + * and enable tracing at the same time. + */ + if (!te->enabled && trTeInstTracing) { + val =3D FIELD_DP32(val, TR_TE_CONTROL, INST_TRACING, 0); + } + + return val; +} + +static void trencoder_te_ctrl_postw(RegisterInfo *reg, uint64_t val) +{ + TraceEncoder *te =3D TRACE_ENCODER(reg->opaque); + uint32_t trTeActive =3D ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, ACTI= VE); + uint32_t trTeEnable =3D ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, ENAB= LE); + uint32_t trTeInstTracing =3D ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, + INST_TRACING); + + if (!trTeActive) { + te->enabled =3D false; + te->trace_running =3D false; + te->trace_next_insn =3D false; + return; + } + + if (te->enabled && !trTeEnable) { + /* TODO: this should cause a pending trace data flush. */ + } + + te->enabled =3D trTeEnable ? true : false; + + if (!te->trace_running && trTeInstTracing) { + /* Starting trace. Ask the CPU for the first trace insn */ + te->trace_next_insn =3D true; + } + + te->trace_running =3D trTeInstTracing ? true : false; +} + static RegisterAccessInfo trencoder_regs_info[] =3D { { .name =3D "TR_TE_CONTROL", .addr =3D A_TR_TE_CONTROL, .rsvd =3D R_TR_TE_CONTROL_RSVP_BITS, .reset =3D R_TR_TE_CONTROL_RESET, .ro =3D R_TR_TE_CONTROL_RO_BITS, + .pre_write =3D &trencoder_te_ctrl_prew, + .post_write =3D &trencoder_te_ctrl_postw, }, { .name =3D "TR_TE_IMPL", .addr =3D A_TR_TE_IMPL, .rsvd =3D R_TR_TE_IMPL_RSVP_BITS, .reset =3D R_TR_TE_IMPL_RESET, .ro =3D R_TR_TE_IMPL_RO_BITS, }, + { .name =3D "TR_TE_INST_FEATURES", .addr =3D A_TR_TE_INST_FEATURES, + .reset =3D R_TR_TE_INST_FEATURES_NO_ADDR_DIFF_MASK, + .ro =3D ~0, + }, }; =20 static uint64_t trencoder_read(void *opaque, hwaddr addr, unsigned size) @@ -132,6 +235,10 @@ static void trencoder_reset(DeviceState *dev) for (int i =3D 0; i < ARRAY_SIZE(te->regs_info); i++) { register_reset(&te->regs_info[i]); } + + te->enabled =3D false; + te->trace_running =3D false; + te->trace_next_insn =3D false; } =20 static void trencoder_realize(DeviceState *dev, Error **errp) diff --git a/hw/riscv/trace-encoder.h b/hw/riscv/trace-encoder.h index 8978865663..30d118be1e 100644 --- a/hw/riscv/trace-encoder.h +++ b/hw/riscv/trace-encoder.h @@ -33,6 +33,10 @@ struct TraceEncoder { hwaddr ramsink_ramlimit; uint32_t regs[TRACE_R_MAX]; RegisterInfo regs_info[TRACE_R_MAX]; + + bool enabled; + bool trace_running; + bool trace_next_insn; }; =20 #define TYPE_TRACE_ENCODER "trace-encoder" --=20 2.43.0 From nobody Fri Oct 23 21:01:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792624484; cv=none; d=zohomail.com; s=zohoarc; b=X+hld36o5l0F5YJHbrd/UK19mFEpr7xYctyEnDdCrEUqeKOn0fT4NN5JDZY2NhWzcbF9TCyMwmrLMJzbexOnUmxw5QTKCv31aMqlKIPNNqKzdraEC+BlopClGBkjV/FaTrsLuOjafBuNijC7v3O3zqlTACOuyPYcM3YjdcYHwfY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792624484; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bdN8gpFlkwMerf3PXBCI0/AZ4mp6NhyzqrQZk/FHQ0E=; b=Otkpy+RlKH9eNeu1mXMei9CXZYDgQHJS3ZH60qw6fjaj34aMCb+IeF95fQJC6vC52lnQuMba9/YJ83x/bkSqI8NYlbSFny8f6h7s0m7m2vdnacwkPM8JrVXknHPSpbmBVhZhMlYYAWRSCdLt71YevIpWM+CsR5fqO1Vn26dhptk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792624484061605.1459755172989; Wed, 21 Oct 2026 16:14:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJfVg-0007UK-W9; Wed, 21 Oct 2026 19:14:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJfVe-0007Ty-S4 for qemu-devel@nongnu.org; Wed, 21 Oct 2026 19:14:15 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJfVc-0004y3-Us for qemu-devel@nongnu.org; Wed, 21 Oct 2026 19:14:14 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69LKeRe21502571 for ; Wed, 21 Oct 2026 23:14:12 GMT Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hf0k2hg8t-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 21 Oct 2026 23:14:11 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-5338ff2cf14so26768971cf.1 for ; Wed, 21 Oct 2026 16:14:11 -0700 (PDT) Received: from QCOM-UWl2o8bcGT.qualcomm.com (200-204-190-237.dsl.telesp.net.br. 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Wed, 21 Oct 2026 16:14:11 -0700 (PDT) X-Received: by 2002:a05:622a:588e:b0:532:9a2a:f37 with SMTP id d75a77b69052e-5369b677beemr55774351cf.18.1792624450735; Wed, 21 Oct 2026 16:14:10 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, antikostya2@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH v4 04/18] hw/riscv/virt.c: add trace encoders and trace ram sinks Date: Wed, 21 Oct 2026 20:13:31 -0300 Message-ID: <20261021231346.2452179-5-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261021231346.2452179-1-daniel.barboza@oss.qualcomm.com> References: <20261021231346.2452179-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA5MiBTYWx0ZWRfXwXI3gIs6eE5G h+MyU4fu87nu/GvVw7M2fCBZOdGXZzsH+25w410rddVP8PvEfjaajS9vG4D5bzAfu890ZCZqAr6 JXrojKW/r7oTrHG/hn65JcBwCEk56FI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA5MiBTYWx0ZWRfX0288bTcZIAuG li6ki3rjq3OuUIuz6HeD98fllJwGn9nYwFovz7afQAXCs+ARNtHXFusmhq3j6sl9PqZpcsJtU8E PTsOdutfB3wTGuhtkPDxid8r0BIveSi8+XT8B7QrqXNcvfMvwNk+KCw5f+nr9QxrbVeC55WVk6n zoxvQJrovyCXpAFlFep/L6frGOguXyWgaOg/u84t3EL278G1ZZxCov33bTh6Q4spuXbQCe6CxoP IFeoWbGpS3JD3A+JTYCYBwW51c1U7954d8zsp7yii37Pq8XBIizo1xP5mpAwYnCQKZmIj2Y1z0h K9HYLw78i2XLLgd9CQGMwVfxQfu1n/H1SFpq2CNEqCx1Kk26XmX+E6p0LRE2tfjn/nvk7Dtf5qR 5yy5oNGpXbcvhWe06VFeTanGNLTs8ZaT4LbYWojcFBCfD0Ku4BlJXksXYjYmWadw7bHVxFnEY5z fFgdwRso6+4Ifvk28Qw== X-Proofpoint-ORIG-GUID: K3SsIY9UuOllNIJPdSIaKPjcUcUpuPiY X-Proofpoint-GUID: K3SsIY9UuOllNIJPdSIaKPjcUcUpuPiY X-Authority-Analysis: v=2.4 cv=K/+3jCWI c=1 sm=1 tr=0 ts=6ad94743 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=QmVDPCq3bE4LYXGvZ20s0w==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=GcwozZFMniDO5iVAK48A:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210092 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624486645158500 Content-Type: text/plain; charset="utf-8" Add the minimal topology required for e-trace support in the virt machine, e.g. each CPU will have a single trace encoder, and each trace encoder will communicate to a single associated trace ram sink. At this moment we're not going to support more complex topologies with trace funnels and so on. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 81 ++++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 2 + target/riscv/cpu.h | 9 +++++ target/riscv/tcg/tcg-cpu.c | 5 +++ 4 files changed, 97 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d4b501802f..d47b295f0c 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -60,6 +60,8 @@ #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" #include "hw/uefi/var-service-api.h" +#include "hw/riscv/trace-encoder.h" +#include "hw/riscv/trace-ram-sink.h" =20 #include "aia.h" =20 @@ -83,6 +85,17 @@ static bool virt_aclint_allowed(void) return tcg_enabled() || qtest_enabled(); } =20 +#define TR_DEV_REGMAP_SIZE 0x1000 +/* For VIRT_CPUS_MAX =3D 512: TRACE_DEV_REG_MAX =3D 0x200000 */ +#define TRACE_DEV_REG_MAX (TR_DEV_REGMAP_SIZE * VIRT_CPUS_MAX) + +/* + * 64k for the RAM Sink that includes the 4k (0x1000) + * for regs, for each possible CPU. For 512 max CPUs, + * total size =3D 0x2000000. + */ +#define TRACE_RAM_SINK_SIZE (1UL << 16) + static const MemMapEntry virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, [VIRT_MROM] =3D { 0x1000, 0xf000 }, @@ -92,7 +105,9 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_ACLINT_SSWI] =3D { 0x2F00000, 0x4000 }, [VIRT_PCIE_PIO] =3D { 0x3000000, 0x10000 }, [VIRT_IOMMU_SYS] =3D { 0x3010000, 0x1000 }, + [VIRT_TR_ENCODERS] =3D { 0x3020000, TRACE_DEV_REG_MAX }, [VIRT_PLATFORM_BUS] =3D { 0x4000000, 0x2000000 }, + [VIRT_TR_RAM_SINKS] =3D { 0x6000000, TRACE_RAM_SINK_SIZE * VIRT_CPUS_= MAX }, [VIRT_PLIC] =3D { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2= ) }, [VIRT_APLIC_M] =3D { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, [VIRT_APLIC_S] =3D { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, @@ -710,6 +725,68 @@ static void virt_machine_done(Notifier *notifier, void= *data) } } =20 +/* + * Must be called after 'soc' realize since it + * uses CPU objs. + */ +static void virt_init_socket_trace_hw(RISCVVirtState *s, int socket_num) +{ + int hartid_base =3D s->soc[socket_num].hartid_base; + + for (int cpu =3D 0; cpu < s->soc[socket_num].num_harts; cpu++) { + RISCVCPU *cpu_ptr =3D &s->soc[socket_num].harts[cpu]; + DeviceState *trencoder, *ram_sink; + uint64_t trencoder_addr, ram_sink_addr, smem_addr; + uint32_t smem_size =3D TRACE_RAM_SINK_SIZE - TR_DEV_REGMAP_SIZE; + int cpu_id =3D hartid_base + cpu; + + ram_sink =3D qdev_new(TYPE_TRACE_RAM_SINK); + + ram_sink_addr =3D virt_memmap[VIRT_TR_RAM_SINKS].base + + TRACE_RAM_SINK_SIZE * cpu_id; + /* smem is located right after ram sink base */ + smem_addr =3D ram_sink_addr + TR_DEV_REGMAP_SIZE; + + object_property_set_uint(OBJECT(ram_sink), "baseaddr", + ram_sink_addr, &error_fatal); + object_property_set_uint(OBJECT(ram_sink), "smemaddr", + smem_addr, &error_fatal); + object_property_set_uint(OBJECT(ram_sink), "smemsize", + smem_size, &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(ram_sink), &error_fatal); + + /* + * We can't do object_property_set_link() because we're + * coming after cpu.realize() (the riscv_hart obj creates + * the CPU objs in its realize() since it has no init). + * We need changes in how riscv_hart works to use + * set_link() and to not manually realize the trace + * encoder. + * + * For now do everything manually. + */ + trencoder =3D qdev_new(TYPE_TRACE_ENCODER); + cpu_ptr->trencoder =3D OBJECT(trencoder); + + trencoder_addr =3D virt_memmap[VIRT_TR_ENCODERS].base + + TR_DEV_REGMAP_SIZE * cpu_id; + + object_property_set_link(OBJECT(trencoder), "cpu", + OBJECT(cpu_ptr), &error_fatal); + object_property_set_int(OBJECT(trencoder), "cpu-id", cpu_id, + &error_fatal); + object_property_set_uint(OBJECT(trencoder), "baseaddr", + trencoder_addr, &error_fatal); + object_property_set_uint(OBJECT(trencoder), "dest-baseaddr", + ram_sink_addr, &error_fatal); + object_property_set_uint(OBJECT(trencoder), "ramsink-ramstart", + smem_addr, &error_fatal); + object_property_set_uint(OBJECT(trencoder), "ramsink-ramlimit", + smem_addr + smem_size, &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(trencoder), &error_fatal); + } +} + static void virt_machine_init(MachineState *machine) { RISCVVirtState *s =3D RISCV_VIRT_MACHINE(machine); @@ -765,6 +842,10 @@ static void virt_machine_init(MachineState *machine) hart_count, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); =20 + if (tcg_enabled()) { + virt_init_socket_trace_hw(s, i); + } + if (virt_aclint_allowed() && s->have_aclint) { if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { /* Per-socket ACLINT MTIMER */ diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index e516898f9a..f3744f48c2 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -91,6 +91,8 @@ enum { VIRT_PLATFORM_BUS, VIRT_PCIE_ECAM, VIRT_IOMMU_SYS, + VIRT_TR_ENCODERS, + VIRT_TR_RAM_SINKS, }; =20 enum { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b65d631994..e2ded4c257 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -593,6 +593,15 @@ struct ArchCPU { GHashTable *misa_ext_user_opts; GHashTable *multi_ext_user_opts; const GPtrArray *decoders; + +#ifndef CONFIG_USER_ONLY + /* + * Associated Trace Encoder. It will not be NULL if + * we're running with TCG and initialized manually by + * the board. + */ + Object *trencoder; +#endif }; =20 typedef struct RISCVCSR RISCVCSR; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e07ca95e49..6e74d6a4de 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -39,6 +39,7 @@ #include "exec/icount.h" #include "target/riscv/tcg/debug.h" #include "target/riscv/tcg/csr.h" +#include "hw/riscv/trace-encoder.h" #endif =20 static GHashTable *multi_ext_implied_rules; @@ -1366,6 +1367,10 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Erro= r **errp) if (riscv_has_ext(env, RVH)) { env->mideleg =3D MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; } + + if (cpu->trencoder) { + qdev_realize(DEVICE(cpu->trencoder), NULL, &error_fatal); + } #endif =20 return true; --=20 2.43.0 From nobody Fri Oct 23 21:01:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792624519; cv=none; d=zohomail.com; s=zohoarc; b=bTfaEN4JovxAzRlfn9HNRthfQHWj5vCxXckzH88IgfQteJ0/1QbBHg+7ZUjt3EcMcN98FtrRHJsiPy6cVu7yH05ccf0nDJF4e7NXeoutSeIyUxEk8/7+PrAK9GKsP6bM+6z9YHhFoMzwVk84LMrzjbiLUDsJMNh45AMXWUcYPWI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792624519; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aZTPn3dLfVQQbusORahx+nzRUWSRdq1k8r7nhB7U/pA=; b=OcV34jfW/wxMHbATxqolx/A4SfNl6gHkJKc9/D7Lc4SetprCBXUPxVehiaK1V0/3KmMYpUveh6TBVSWP8fzf+YyY5ozDBwKAnBfUFg50dKCOxMhweVt1Kd6GqCcaaFFKKIyZ8Q7tLf0z+IGVzNyji/v7N4UmyiSHyq+E71yOxLc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792624519499753.5174165399876; Wed, 21 Oct 2026 16:15:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJfVj-0007Uz-7u; Wed, 21 Oct 2026 19:14:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJfVh-0007Uj-OT for qemu-devel@nongnu.org; Wed, 21 Oct 2026 19:14:17 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJfVf-0004ya-Jg for qemu-devel@nongnu.org; Wed, 21 Oct 2026 19:14:17 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69LKeJHQ2160543 for ; Wed, 21 Oct 2026 23:14:14 GMT Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hf1u3h348-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 21 Oct 2026 23:14:14 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-532f343a55bso23569631cf.3 for ; Wed, 21 Oct 2026 16:14:14 -0700 (PDT) Received: from QCOM-UWl2o8bcGT.qualcomm.com (200-204-190-237.dsl.telesp.net.br. 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Wed, 21 Oct 2026 16:14:13 -0700 (PDT) X-Received: by 2002:ac8:5f0b:0:b0:536:66ec:1b06 with SMTP id d75a77b69052e-5369b89c2e8mr55336341cf.50.1792624453373; Wed, 21 Oct 2026 16:14:13 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, antikostya2@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH v4 05/18] hw/riscv/virt.c add trace encoder and ramsink fdt nodes Date: Wed, 21 Oct 2026 20:13:32 -0300 Message-ID: <20261021231346.2452179-6-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261021231346.2452179-1-daniel.barboza@oss.qualcomm.com> References: <20261021231346.2452179-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=S8ZMU4sP c=1 sm=1 tr=0 ts=6ad94746 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=QmVDPCq3bE4LYXGvZ20s0w==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=mr6zqDPyyxlTI8rpP2AA:9 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-ORIG-GUID: 4Uppqn9bVh51mPvyazwVgAZ1Z2ErLM1v X-Proofpoint-GUID: 4Uppqn9bVh51mPvyazwVgAZ1Z2ErLM1v X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA5MiBTYWx0ZWRfX/J8SLyHqJTYC H0sKh7of+Y9U3I6iTMK3+/mHbnwMMNNPefPHTqwW/Rh2v5OXOxGaCugM4fCMyi9N0nqNPpjCWty 962ALlN2frp0JrPNgi1QoVYiLH88TZLCgn8QUZ1yw1iZAaArS9LvCvDA7kXnWxB2zqHH7mQJoEz uLZyhLTAsUZV76ansmBSdcndxFYd8mcaXvPzImea/+elP7TSqwIdFcXfc9RfifelMI7Ogc/54bt w6ZDXIwfrhEEETAnZGs2d2qdJtudb2HeblZv1xLqz/NGoN3j15GrH7/j/pgCLiZReHqdjqgrkuF iAz5wXXO2t4NcRkIwtrAiPUt6zcrUhE2RpVEDMz3qvnnglj8Juv7bpeh1iUv5xVQNI14XurlMZa naXZ6khUCm3rhJIEidxC314UqAeKrSW9YrNErY0+wo1MVA7g+M0wFHhbkJmuR3p0zZKjqh8zdTU 40Rd9qWpde+EN8gXwyw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA5MiBTYWx0ZWRfX0uzpChH98SRV 6aEi+MUBF5b/Ci+wmwLySF7+A+C71PtBPr75jeJ/EzAC3Wf5yTA16cf4OHhGnNDRs+U00Ikrz0S fDhuT5qBxaYeBTdaZ8Bm3ycUTA4O3mY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 clxscore=1015 adultscore=0 impostorscore=0 malwarescore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210092 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624521128158500 Content-Type: text/plain; charset="utf-8" The trace encoder and trace ramsink nodes should confirm to the bindings described in "riscv,trace-component.yaml" in the Linux kernel. That way, encoder and ramsink devices get populated on the rvtrace bus and perf record is able to capture the trace data in the auxtrace section as expected. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/fdt-common.c | 70 +++++++++++++++++++++++++++++++++++ hw/riscv/virt.c | 47 +++++++++++++++++++++++ include/hw/riscv/fdt-common.h | 4 ++ 3 files changed, 121 insertions(+) diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index ce2dcb43b4..6130b1bcc1 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -105,6 +105,12 @@ void riscv_fdt_create_cpu_socket_subnode(void *fdt, qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); } =20 +/* Caller must free string after use */ +static char* fdt_get_cpu_nodename(int cpu_id) +{ + return g_strdup_printf("/cpus/cpu@%d", cpu_id); +} + static void create_fdt_socket_cpu_internal(void *fdt, char *clust_name, RISCVCPU *cpu_= ptr, int cpu, int socket_id, int socket_hartid_b= ase, @@ -849,3 +855,67 @@ void riscv_create_fdt_rtc(void *fdt, const MemMapEntry= *rtc_mem, qemu_fdt_setprop_cells(fdt, name, "interrupts", rtc_irq, 0x4); } } + +/* Returns the 'out-ports/port/endpoint' nodepath. Caller + must free the string after use. */ +char *riscv_create_fdt_trace_encoder(void *fdt, hwaddr addr, hwaddr size, + int cpu_id) +{ + static const char * const tr_compat[2] =3D { "qemu,trace-component", + "riscv,trace-component" }; + g_autofree char *cpu_nodename =3D fdt_get_cpu_nodename(cpu_id); + g_autofree char *trencoder_name =3D NULL; + char *endpoint =3D NULL; + + trencoder_name =3D g_strdup_printf("/soc/encoder@%"HWADDR_PRIx, addr); + qemu_fdt_add_subnode(fdt, trencoder_name); + + qemu_fdt_setprop_sized_cells(fdt, trencoder_name, "reg", + 2, addr, + 2, size); + + qemu_fdt_setprop_string_array(fdt, trencoder_name, "compatible", + (char **)&tr_compat, + ARRAY_SIZE(tr_compat)); + + qemu_fdt_setprop_phandle(fdt, trencoder_name, "cpus", cpu_nodename); + + endpoint =3D g_strdup_printf("%s/out-ports/port/endpoint", trencoder_n= ame); + qemu_fdt_add_path(fdt, endpoint); + qemu_fdt_setprop_cell(fdt, endpoint, "phandle", + qemu_fdt_alloc_phandle(fdt)); + + return endpoint; +} + +/* Returns the 'in-ports/port/endpoint' nodepath. Caller + must free the string after use. */ +char *riscv_create_fdt_trace_ramsink(void *fdt, hwaddr addr, hwaddr size, + int cpu_id) +{ + static const char * const tr_compat[2] =3D { "qemu,trace-component", + "riscv,trace-component" }; + g_autofree char *cpu_nodename =3D fdt_get_cpu_nodename(cpu_id); + g_autofree char *ramsink_name =3D NULL; + char *endpoint =3D NULL; + + ramsink_name =3D g_strdup_printf("/soc/ramsink@%"HWADDR_PRIx, addr); + qemu_fdt_add_subnode(fdt, ramsink_name); + + qemu_fdt_setprop_sized_cells(fdt, ramsink_name, "reg", + 2, addr, + 2, size); + + qemu_fdt_setprop_string_array(fdt, ramsink_name, "compatible", + (char **)&tr_compat, + ARRAY_SIZE(tr_compat)); + + qemu_fdt_setprop_phandle(fdt, ramsink_name, "cpus", cpu_nodename); + + endpoint =3D g_strdup_printf("%s/in-ports/port/endpoint", ramsink_name= ); + qemu_fdt_add_path(fdt, endpoint); + qemu_fdt_setprop_cell(fdt, endpoint, "phandle", + qemu_fdt_alloc_phandle(fdt)); + + return endpoint; +} diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d47b295f0c..6bc8d384ec 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -479,6 +479,51 @@ static void create_fdt_iommu(RISCVVirtState *s, uint16= _t bdf) s->pci_iommu_bdf =3D bdf; } =20 +static void create_fdt_rvtrace(RISCVVirtState *s) +{ + MachineState *ms =3D MACHINE(s); + int socket_count =3D riscv_socket_count(ms); + hwaddr encoder_addr, ramsink_addr, size =3D 0x100; + RISCVCPU *cpu_ptr; + int cpu_id; + + for (int i =3D 0; i < socket_count; i++) { + for (int cpu =3D 0; cpu < s->soc[i].num_harts; cpu++) { + g_autofree char *in_endpoint =3D NULL; + g_autofree char *out_endpoint =3D NULL; + + cpu_ptr =3D &s->soc[i].harts[cpu]; + if (!cpu_ptr->trencoder) { + continue; + } + + encoder_addr =3D object_property_get_uint(cpu_ptr->trencoder, + "baseaddr", + &error_abort); + ramsink_addr =3D object_property_get_uint(cpu_ptr->trencoder, + "dest-baseaddr", + &error_abort); + cpu_id =3D s->soc[i].hartid_base + cpu; + + in_endpoint =3D riscv_create_fdt_trace_ramsink(ms->fdt, + ramsink_addr, + size, cpu_id); + + out_endpoint =3D riscv_create_fdt_trace_encoder(ms->fdt, + encoder_addr, + size, cpu_id); + + /* The remote-endpoint property is bidirectional, i.e. the + in-ports endpoint must point to the out-ports endpoint + and vice-versa. */ + qemu_fdt_setprop_phandle(ms->fdt, in_endpoint, + "remote-endpoint", out_endpoint); + qemu_fdt_setprop_phandle(ms->fdt, out_endpoint, + "remote-endpoint", in_endpoint); + } + } +} + static void finalize_fdt(RISCVVirtState *s) { uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; @@ -520,6 +565,8 @@ static void finalize_fdt(RISCVVirtState *s) =20 riscv_create_fdt_rtc(MACHINE(s)->fdt, &s->memmap[VIRT_RTC], RTC_IRQ, s->aia_type, irq_mmio_phandle); + + create_fdt_rvtrace(s); } =20 static void create_fdt(RISCVVirtState *s) diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index eb9db8278d..fd03a9e0ab 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -136,4 +136,8 @@ void riscv_create_fdt_uart(void *fdt, const MemMapEntry= *uart_mem, void riscv_create_fdt_rtc(void *fdt, const MemMapEntry *rtc_mem, int rtc_irq, int aia_type, uint32_t irq_phandle); +char *riscv_create_fdt_trace_encoder(void *fdt, hwaddr addr, hwaddr size, + int cpu_id); +char *riscv_create_fdt_trace_ramsink(void *fdt, hwaddr addr, hwaddr size, + int cpu_id); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624610797158501 Content-Type: text/plain; charset="utf-8" Before making the trace encoder writing into the RAM sink we need a way to encode the messages/packets. The encoding is LSB (least significant bit) based. The doc "Efficient Trace for RISC-V", Chapter 7, mentions: "The remainder of this section describes the contents of the payload portion which should be independent of the infrastructure. In each table, the fields are listed in transmission order: first field in the table is transmitted first, and multi-bit fields are transmitted LSB first." The "RISC-V Trace Control Interface Specification" docs, Chapter 7, states when talking about the Trace RAM Sink: "Trace data is placed in memory in LSB order (first byte of trace packet/data is placed on LSB)." This means that the LSB encoding must be used to write into the RAM Sink memory, which is our goal. The design we're going for is to have all these encoder helpers, along with the message formats, in a separated file. The trace encoder will make use of these helpers to blindly write a byte array with the packet desired, and then write it as is in the RAM Sink. We'll start by modeling the synchronisation packet first, adding more formats as we increment the Trace Encoder capabilities. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/meson.build | 3 +- hw/riscv/rv-trace-messages.c | 94 ++++++++++++++++++++++++++++++++++++ hw/riscv/rv-trace-messages.h | 25 ++++++++++ 3 files changed, 121 insertions(+), 1 deletion(-) create mode 100644 hw/riscv/rv-trace-messages.c create mode 100644 hw/riscv/rv-trace-messages.h diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 97a39f85f9..87ac6d73b3 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -22,7 +22,8 @@ riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true:= files('xiangshan_kmh.c riscv_ss.add(when: 'CONFIG_RISCV_MIPS_CPS', if_true: files('cps.c')) riscv_ss.add(when: 'CONFIG_MIPS_BOSTON_AIA', if_true: files('boston-aia.c'= )) riscv_ss.add(when: 'CONFIG_K230', if_true: files('k230.c')) -riscv_ss.add(when: 'CONFIG_RISCV_TRACE', if_true: files('trace-encoder.c',= 'trace-ram-sink.c')) +riscv_ss.add(when: 'CONFIG_RISCV_TRACE', if_true: files('trace-encoder.c', + 'trace-ram-sink.c', 'rv-trace-messages.c')) riscv_ss.add(when: 'CONFIG_SOPHGO_CV1800B', if_true: files('cv1800b.c')) riscv_ss.add(when: 'CONFIG_MILKV_DUO', if_true: files('milkv_duo.c')) =20 diff --git a/hw/riscv/rv-trace-messages.c b/hw/riscv/rv-trace-messages.c new file mode 100644 index 0000000000..01ff51c715 --- /dev/null +++ b/hw/riscv/rv-trace-messages.c @@ -0,0 +1,94 @@ +/* + * Helpers for RISC-V Trace Messages + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "rv-trace-messages.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "trace.h" + +typedef struct RVTraceMessageHeader { + uint8_t length:5; + uint8_t flow:2; + uint8_t extend:1; +} RVTraceMessageHeader; +#define HEADER_SIZE 1 + +/* + * Format 3 subformat 0 without 'time' and 'context' fields + */ +typedef struct RVTraceSyncPayload { + uint8_t format:2; + uint8_t subformat:2; + uint8_t branch:1; + uint8_t privilege:3; + uint32_t addressLow; + uint32_t addressHigh; +} RVTraceSyncPayload; +#define SYNC_PAYLOAD_SIZE_64BITS 9 + +static void rv_etrace_write_bits(uint8_t *bytes, uint32_t bit_pos, + uint32_t num_bits, uint32_t val) +{ + uint32_t pos, byte_index, byte_pos, byte_bits =3D 0; + + if (!num_bits || 32 < num_bits) { + return; + } + + for (pos =3D 0; pos < num_bits; pos +=3D byte_bits) { + byte_index =3D (bit_pos + pos) >> 3; + byte_pos =3D (bit_pos + pos) & 0x7; + byte_bits =3D (8 - byte_pos) < (num_bits - pos) ? + (8 - byte_pos) : (num_bits - pos); + bytes[byte_index] &=3D ~(((1U << byte_bits) - 1) << byte_pos); + bytes[byte_index] |=3D ((val >> pos) & ((1U << byte_bits) - 1)) <<= byte_pos; + } +} + +static void rv_etrace_write_header(uint8_t *buf, RVTraceMessageHeader head= er) +{ + /* flow and extend are always zero, i.e just write length */ + rv_etrace_write_bits(buf, 0, 5, header.length); +} + +size_t rv_etrace_gen_encoded_sync_msg(uint8_t *buf, uint64_t pc, + TracePrivLevel priv_level) +{ + RVTraceSyncPayload payload =3D {.format =3D 0b11, + .subformat =3D 0b00, + .branch =3D 1, + .privilege =3D priv_level}; + RVTraceMessageHeader header =3D {.flow =3D 0, .extend =3D 0, + .length =3D SYNC_PAYLOAD_SIZE_64BITS}; + uint8_t bit_pos; + + payload.addressLow =3D extract64(pc, 0, 32); + payload.addressHigh =3D extract64(pc, 32, 32); + + rv_etrace_write_header(buf, header); + bit_pos =3D 8; + + rv_etrace_write_bits(buf, bit_pos, 2, payload.format); + bit_pos +=3D 2; + rv_etrace_write_bits(buf, bit_pos, 2, payload.subformat); + bit_pos +=3D 2; + rv_etrace_write_bits(buf, bit_pos, 1, payload.branch); + bit_pos +=3D 1; + rv_etrace_write_bits(buf, bit_pos, 3, payload.privilege); + bit_pos +=3D 3; + + rv_etrace_write_bits(buf, bit_pos, 32, payload.addressLow); + bit_pos +=3D 32; + rv_etrace_write_bits(buf, bit_pos, 32, payload.addressHigh); + + return HEADER_SIZE + SYNC_PAYLOAD_SIZE_64BITS; +} diff --git a/hw/riscv/rv-trace-messages.h b/hw/riscv/rv-trace-messages.h new file mode 100644 index 0000000000..c7226b50a9 --- /dev/null +++ b/hw/riscv/rv-trace-messages.h @@ -0,0 +1,25 @@ +/* + * Helpers for RISC-V Trace Messages + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef RISCV_RV_TRACE_MESSAGES_H +#define RISCV_RV_TRACE_MESSAGES_H + +typedef enum { + U =3D 0, + S_HS =3D 1, + RESERVED =3D 2, + M =3D 3, + D =3D 4, + VU =3D 5, + VS =3D 6, +} TracePrivLevel; + +size_t rv_etrace_gen_encoded_sync_msg(uint8_t *buf, uint64_t pc, + TracePrivLevel priv_level); + +#endif --=20 2.43.0 From nobody Fri Oct 23 21:01:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792624651; cv=none; d=zohomail.com; s=zohoarc; b=WEmcHXNLPr3pwkpzn4m7E7gK/j/CVp9v+fxm2wCobHcgTTmFpMmLt0bx5IOD2u44eoAIRWm4c4FwK77H1qDYOe/LNu9vn0C5YUH8DYQAfJAU5HN+J/7qwZbgM/IZ8+InXH6wI2O3lVS5TEu4fL/znRjbCFfKaYDJ2Ow1cs6kaYQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792624651; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=imggVMD/TaZWMeer1ygFhdYQWn4q+sa8kaNN50YrEb8=; b=m9mq//ZdrjsoDJDr8IAcGhOaS+dQb3F1Ies/DQ0a6wbs3yfPi27YKhd+/6fAh5c3gBye/oclNucM7yVFXbW+fs4MDNILanrVFgpADHRSdrTfvguYXEjfBld/6PykAn9mm5Zcum774DuX9yMMKc/p8nMPdvdhYCGWXU4jkb9S+To= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792624651732790.2896190333418; Wed, 21 Oct 2026 16:17:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJfW5-0007eN-QX; Wed, 21 Oct 2026 19:14:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJfVy-0007bS-8U for qemu-devel@nongnu.org; Wed, 21 Oct 2026 19:14:34 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJfVv-0004zB-A3 for qemu-devel@nongnu.org; Wed, 21 Oct 2026 19:14:33 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69LKe96o1501680 for ; Wed, 21 Oct 2026 23:14:20 GMT Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hf0k2hg9d-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 21 Oct 2026 23:14:20 +0000 (GMT) Received: by mail-qt1-f198.google.com with SMTP id d75a77b69052e-535066512b0so37115591cf.0 for ; Wed, 21 Oct 2026 16:14:20 -0700 (PDT) Received: from QCOM-UWl2o8bcGT.qualcomm.com (200-204-190-237.dsl.telesp.net.br. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624653631158500 Content-Type: text/plain; charset="utf-8" We'll have to instrument some RISC-V translations, as well as the start of a translation block, communicating with the associated trace encoder in case we're running a trace session. The trace encoder needs to report the first insn of the session so we'll start with that. Add a new EXT_TB_FLAGS called CPU_TRACE_RUNNING, along with its ctx->cpu_trace_running boolean, to track when we should call the hwtrace helpers. For now we care about just the first insn of the trace session. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/trace-encoder.c | 17 ++++++++++++++++ hw/riscv/trace-encoder.h | 4 ++++ hw/riscv/trace-events | 1 + target/riscv/cpu.h | 3 +++ target/riscv/helper.h | 4 ++++ target/riscv/tcg/meson.build | 6 ++++++ target/riscv/tcg/tcg-cpu.c | 4 ++++ target/riscv/tcg/trace_helper.c | 36 +++++++++++++++++++++++++++++++++ target/riscv/tcg/translate.c | 9 +++++++++ 9 files changed, 84 insertions(+) create mode 100644 target/riscv/tcg/trace_helper.c diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c index 99399a55e1..1f89dc24fc 100644 --- a/hw/riscv/trace-encoder.c +++ b/hw/riscv/trace-encoder.c @@ -150,11 +150,15 @@ static void trencoder_te_ctrl_postw(RegisterInfo *reg= , uint64_t val) uint32_t trTeEnable =3D ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, ENAB= LE); uint32_t trTeInstTracing =3D ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, INST_TRACING); + RISCVCPU *cpu =3D te->cpu; + CPURISCVState *env =3D &cpu->env; =20 if (!trTeActive) { te->enabled =3D false; te->trace_running =3D false; te->trace_next_insn =3D false; + + env->trace_running =3D false; return; } =20 @@ -170,6 +174,7 @@ static void trencoder_te_ctrl_postw(RegisterInfo *reg, = uint64_t val) } =20 te->trace_running =3D trTeInstTracing ? true : false; + env->trace_running =3D te->trace_running; } =20 static RegisterAccessInfo trencoder_regs_info[] =3D { @@ -231,6 +236,8 @@ static const MemoryRegionOps trencoder_ops =3D { static void trencoder_reset(DeviceState *dev) { TraceEncoder *te =3D TRACE_ENCODER(dev); + RISCVCPU *cpu =3D te->cpu; + CPURISCVState *env =3D &cpu->env; =20 for (int i =3D 0; i < ARRAY_SIZE(te->regs_info); i++) { register_reset(&te->regs_info[i]); @@ -239,6 +246,7 @@ static void trencoder_reset(DeviceState *dev) te->enabled =3D false; te->trace_running =3D false; te->trace_next_insn =3D false; + env->trace_running =3D false; } =20 static void trencoder_realize(DeviceState *dev, Error **errp) @@ -266,6 +274,14 @@ static void trencoder_realize(DeviceState *dev, Error = **errp) } } =20 +void trencoder_set_first_trace_insn(Object *trencoder_obj, uint64_t pc) +{ + TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); + + trencoder->first_pc =3D pc; + trace_trencoder_first_trace_insn(pc); +} + static const Property trencoder_props[] =3D { /* * We need a link to the associated CPU to @@ -294,6 +310,7 @@ static const VMStateDescription vmstate_trencoder =3D { VMSTATE_UINT64(ramsink_ramstart, TraceEncoder), VMSTATE_UINT64(ramsink_ramlimit, TraceEncoder), VMSTATE_INT32(cpu_id, TraceEncoder), + VMSTATE_UINT64(first_pc, TraceEncoder), VMSTATE_END_OF_LIST(), } }; diff --git a/hw/riscv/trace-encoder.h b/hw/riscv/trace-encoder.h index 30d118be1e..1801193e15 100644 --- a/hw/riscv/trace-encoder.h +++ b/hw/riscv/trace-encoder.h @@ -27,6 +27,8 @@ struct TraceEncoder { MemoryRegion reg_mem; uint32_t reg_mem_size; =20 + uint64_t first_pc; + hwaddr baseaddr; hwaddr dest_baseaddr; hwaddr ramsink_ramstart; @@ -43,4 +45,6 @@ struct TraceEncoder { =20 OBJECT_DECLARE_SIMPLE_TYPE(TraceEncoder, TRACE_ENCODER) =20 +void trencoder_set_first_trace_insn(Object *trencoder_obj, uint64_t pc); + #endif diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events index 14e333fd9e..dc25377acf 100644 --- a/hw/riscv/trace-events +++ b/hw/riscv/trace-events @@ -28,6 +28,7 @@ riscv_iommu_hpm_evt_write(uint32_t ctr_idx, uint32_t ovf,= uint64_t val) "ctr_idx # trace-encoder.c trencoder_read_error(uint64_t addr) "addr 0x%" PRIx64 trencoder_write_error(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " v= alue 0x%" PRIx64 +trencoder_first_trace_insn(uint64_t pc) "pc 0x%" PRIx64 =20 # trace-ram-sink.c tr_ramsink_read_error(uint64_t addr) "addr 0x%" PRIx64 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e2ded4c257..e9a80365bf 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -551,6 +551,8 @@ struct CPUArchState { uint32_t kvm_mp_state; bool kvm_mp_state_loaded; #endif /* CONFIG_KVM */ + + bool trace_running; }; =20 /* @@ -791,6 +793,7 @@ FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1) FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) /* sdext single-step needs a TB flag to build 1-insn TBs */ FIELD(EXT_TB_FLAGS, SDEXT_STEP, 34, 1) +FIELD(EXT_TB_FLAGS, CPU_TRACE_RUNNING, 35, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 372f104972..0832159adc 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -129,6 +129,10 @@ DEF_HELPER_4(csrrw, tl, env, int, tl, tl) DEF_HELPER_2(csrr_i128, tl, env, int) DEF_HELPER_4(csrw_i128, void, env, int, tl, tl) DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) + +/* Trace helpers (should be put inside ifdef) */ +DEF_HELPER_2(trace_insn, void, env, i64) + #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build index 86805b30cb..e5c72889eb 100644 --- a/target/riscv/tcg/meson.build +++ b/target/riscv/tcg/meson.build @@ -10,6 +10,12 @@ riscv_ss.add(files( 'fpu_helper.c', 'm128_helper.c', 'op_helper.c', + + # In theory the RISC-V HW e-trace support is system_ss only, + # but we're instrumeting TCG code that is visible to riscv_ss + # ae well, ergo the helper needs to be visible in user-mode too. + 'trace_helper.c', + 'translate.c', 'tcg-cpu.c', 'vcrypto_helper.c', diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 6e74d6a4de..8419eeca5f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -201,6 +201,10 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *= cs) if (cpu->cfg.ext_sdext && !env->debug_mode && (env->dcsr & DCSR_STEP))= { ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, SDEXT_STEP, 1); } + + if (env->trace_running) { + ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, CPU_TRACE_RUNNIN= G, 1); + } #endif =20 return (TCGTBCPUState){ diff --git a/target/riscv/tcg/trace_helper.c b/target/riscv/tcg/trace_helpe= r.c new file mode 100644 index 0000000000..5a6d725f56 --- /dev/null +++ b/target/riscv/tcg/trace_helper.c @@ -0,0 +1,36 @@ +/* + * RISC-V Trace Support TCG helpers + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "cpu.h" +#include "trace.h" +#include "exec/helper-proto.h" + +#ifndef CONFIG_USER_ONLY +#include "hw/riscv/trace-encoder.h" +#endif + +#ifndef CONFIG_USER_ONLY +void helper_trace_insn(CPURISCVState *env, uint64_t pc) +{ + RISCVCPU *cpu =3D env_archcpu(env); + TraceEncoder *te =3D TRACE_ENCODER(cpu->trencoder); + + if (te->trace_next_insn) { + trencoder_set_first_trace_insn(cpu->trencoder, pc); + te->trace_next_insn =3D false; + } +} +#else /* #ifndef CONFIG_USER_ONLY */ +void helper_trace_insn(CPURISCVState *env, uint64_t pc) +{ + return; +} +#endif /* #ifndef CONFIG_USER_ONLY*/ diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c index ede9c2563f..fb82a6b2fa 100644 --- a/target/riscv/tcg/translate.c +++ b/target/riscv/tcg/translate.c @@ -125,6 +125,8 @@ typedef struct DisasContext { bool bcfi_enabled; /* Data endianness from MSTATUS UBE/SBE/MBE */ MemOp mo_endianness; + /* Detect if we're in the middle of a CPU trace session. */ + bool cpu_trace_running; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -1368,10 +1370,17 @@ static void riscv_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) ctx->decoders =3D cpu->decoders; ctx->mo_endianness =3D FIELD_EX64(ext_tb_flags, EXT_TB_FLAGS, BIG_ENDI= AN) ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624643414158501 Content-Type: text/plain; charset="utf-8" We have the needed pieces to make the trace encoder write messages (or packets, in e-trace lingo) in its associated RAM sink. We'll start by writing a sync message that we're already able to fetch from the TCG instruction train. The trace encoder must be able to read/write TR_RAM_WP RAM sink regs to know where it is supposed to write packets, thus a handful of helpers are added to manipulate both the ram sink SMEM memory and relevant registers. The bulk of the work is done in trencoder_send_message_smem() where the trace encoder writes each trace packet. The 'wrap' mechanism is implemented to keep writing the RAM sink memory even after a SMEM workflow. If we can't fit a full packet in the end of the ring buffer we're filling with NULLs and writing a new packet back to ramstart. In an overflow event we'll wrap the TR_RAM_WP_LOW WRAP bit and userspace is supposed to clear it after the wrapping was handled (i.e. userspace read the whole ring buffer back to the start). We're also allowing userspace to freely set ramsink and ramstart before the trace session begins, allowing for more freedom w.r.t where the SMEM will be written by the encoder. Note that this also means that userspace is responsible for setting at least TR_RAM_WP_LOW and TR_RAM_WP_HIGH before starting a trace session. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/trace-encoder.c | 122 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c index 1f89dc24fc..2b358b2699 100644 --- a/hw/riscv/trace-encoder.c +++ b/hw/riscv/trace-encoder.c @@ -18,8 +18,37 @@ #include "qapi/error.h" #include "trace.h" #include "system/device_tree.h" +#include "system/physmem.h" #include "hw/core/register.h" #include "cpu.h" +#include "hw/riscv/trace-ram-sink.h" +#include "rv-trace-messages.h" + +/* + * Size of header + payload since we're not sending + * srcID and timestamp. + */ +#define TRACE_MSG_MAX_SIZE 32 + +static TracePrivLevel trencoder_get_curr_priv_level(TraceEncoder *te) +{ + CPURISCVState *env =3D &te->cpu->env; + + switch (env->priv) { + case PRV_U: + return env->virt_enabled ? VU : U; + case PRV_S: + return env->virt_enabled ? VS : S_HS; + case PRV_M: + return M; + } + + /* + * Return a reserved value to signal an error. + * TODO: handle Debug (D). + */ + return RESERVED; +} =20 /* * trTeControl register fields @@ -82,6 +111,41 @@ REG32(TR_TE_IMPL, 0x4) REG32(TR_TE_INST_FEATURES, 0x8) FIELD(TR_TE_INST_FEATURES, NO_ADDR_DIFF, 0, 1) =20 +static uint32_t trencoder_read_reg(TraceEncoder *te, uint32_t reg_addr) +{ + hwaddr addr =3D te->dest_baseaddr + reg_addr; + uint32_t val; + + physical_memory_read(addr, &val, sizeof(uint32_t)); + return val; +} + +static void trencoder_write_reg(TraceEncoder *te, uint32_t reg_addr, + uint32_t val) +{ + hwaddr addr =3D te->dest_baseaddr + reg_addr; + + physical_memory_write(addr, &val, sizeof(uint32_t)); +} + +static hwaddr trencoder_read_ramsink_writep(TraceEncoder *te) +{ + hwaddr ret =3D trencoder_read_reg(te, A_TR_RAM_WP_HIGH); + ret <<=3D 32; + ret +=3D trencoder_read_reg(te, A_TR_RAM_WP_LOW); + + return ret; +} + +static hwaddr trencoder_read_ramsink_ramlimit(TraceEncoder *te) +{ + hwaddr ret =3D trencoder_read_reg(te, A_TR_RAM_LIMIT_HIGH); + ret <<=3D 32; + ret +=3D trencoder_read_reg(te, A_TR_RAM_LIMIT_LOW); + + return ret; +} + static uint64_t trencoder_te_ctrl_set_hardwire_vals(uint64_t input) { input =3D FIELD_DP32(input, TR_TE_CONTROL, INST_MODE, 0x6); @@ -171,6 +235,9 @@ static void trencoder_te_ctrl_postw(RegisterInfo *reg, = uint64_t val) if (!te->trace_running && trTeInstTracing) { /* Starting trace. Ask the CPU for the first trace insn */ te->trace_next_insn =3D true; + + te->ramsink_ramstart =3D trencoder_read_ramsink_writep(te); + te->ramsink_ramlimit =3D trencoder_read_ramsink_ramlimit(te); } =20 te->trace_running =3D trTeInstTracing ? true : false; @@ -274,12 +341,67 @@ static void trencoder_realize(DeviceState *dev, Error= **errp) } } =20 +static void trencoder_update_ramsink_writep(TraceEncoder *te, + hwaddr wp_val, + bool wrapped) +{ + uint32_t wp_low =3D trencoder_read_reg(te, A_TR_RAM_WP_LOW); + + wp_low =3D FIELD_DP32(wp_low, TR_RAM_WP_LOW, ADDR, + extract64(wp_val, 2, 30)); + + if (wrapped) { + wp_low =3D FIELD_DP32(wp_low, TR_RAM_WP_LOW, WRAP, 1); + } + + trencoder_write_reg(te, A_TR_RAM_WP_LOW, wp_low); + trencoder_write_reg(te, A_TR_RAM_WP_HIGH, extract64(wp_val, 32, 32)); +} + +static void trencoder_send_message_smem(TraceEncoder *trencoder, + uint8_t *msg, uint8_t msg_size) +{ + hwaddr dest =3D trencoder_read_ramsink_writep(trencoder); + bool wrapped =3D false; + + msg_size =3D QEMU_ALIGN_UP(msg_size, 4); + + /* clear trRamWrap before writing to SMEM */ + dest =3D FIELD_DP64(dest, TR_RAM_WP_LOW, WRAP, 0); + + /* + * Fill with null bytes if we can't fit the packet in + * ramlimit, set wrap and write the packet in ramstart. + */ + if (dest + msg_size > trencoder->ramsink_ramlimit) { + g_autofree uint8_t *null_packet =3D NULL; + uint8_t null_size =3D trencoder->ramsink_ramlimit - dest; + + null_packet =3D g_malloc0(null_size); + physical_memory_write(dest, null_packet, null_size); + + dest =3D trencoder->ramsink_ramstart; + wrapped =3D true; + } + + physical_memory_write(dest, msg, msg_size); + dest +=3D msg_size; + + trencoder_update_ramsink_writep(trencoder, dest, wrapped); +} + void trencoder_set_first_trace_insn(Object *trencoder_obj, uint64_t pc) { TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); + TracePrivLevel priv =3D trencoder_get_curr_priv_level(trencoder); + g_autofree uint8_t *msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); + uint8_t msg_size; =20 trencoder->first_pc =3D pc; trace_trencoder_first_trace_insn(pc); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624567961158500 Content-Type: text/plain; charset="utf-8" Add a simple smoke test for the trace encoder/trace ram sink integration with the RISC-V 'virt' machine. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 2 +- tests/qtest/meson.build | 2 +- tests/qtest/riscv-trace-test.c | 120 +++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/riscv-trace-test.c diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6bc8d384ec..60d1ab3a90 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -889,7 +889,7 @@ static void virt_machine_init(MachineState *machine) hart_count, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); =20 - if (tcg_enabled()) { + if (tcg_enabled() || qtest_enabled()) { virt_init_socket_trace_hw(s, i); } =20 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 019c63ca60..b1249eb733 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -311,7 +311,7 @@ qtests_s390x =3D \ qtests_riscv32 =3D \ (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watc= hdog-test'] : []) =20 -qtests_riscv64 =3D ['riscv-csr-test'] + \ +qtests_riscv64 =3D ['riscv-csr-test', 'riscv-trace-test'] + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ (config_all_devices.has_key('CONFIG_IOMMU_TESTDEV') and config_all_devices.has_key('CONFIG_RISCV_IOMMU') ? diff --git a/tests/qtest/riscv-trace-test.c b/tests/qtest/riscv-trace-test.c new file mode 100644 index 0000000000..8015a00b76 --- /dev/null +++ b/tests/qtest/riscv-trace-test.c @@ -0,0 +1,120 @@ +/* + * Testcase for RISC-V Trace framework + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "qemu/timer.h" +#include "qemu/bitops.h" +#include "libqtest.h" +#include "hw/core/registerfields.h" + +/* taken from virt machine memmap */ +#define TE_BASE 0x3020000 +#define TRAM_BASE 0x6000000 + +REG32(TR_TE_CONTROL, 0x0) + FIELD(TR_TE_CONTROL, ACTIVE, 0, 1) + FIELD(TR_TE_CONTROL, ENABLE, 1, 1) + FIELD(TR_TE_CONTROL, INST_TRACING, 2, 1) + +REG32(TR_RAM_START_LOW, 0x010) + FIELD(TR_RAM_START_LOW, ADDR, 0, 32) +REG32(TR_RAM_START_HIGH, 0x014) + FIELD(TR_RAM_START_HIGH, ADDR, 0, 32) + +REG32(TR_RAM_LIMIT_LOW, 0x018) + FIELD(TR_RAM_LIMIT_LOW, ADDR, 0, 32) +REG32(TR_RAM_LIMIT_HIGH, 0x01C) + FIELD(TR_RAM_LIMIT_HIGH, ADDR, 0, 32) + +REG32(TR_RAM_WP_LOW, 0x020) + FIELD(TR_RAM_WP_LOW, WRAP, 0, 1) + FIELD(TR_RAM_WP_LOW, ADDR, 0, 32) +REG32(TR_RAM_WP_HIGH, 0x024) + FIELD(TR_RAM_WP_HIGH, ADDR, 0, 32) + +static uint32_t test_read_te_control(QTestState *qts) +{ + return qtest_readl(qts, TE_BASE + A_TR_TE_CONTROL); +} + +static void test_write_te_control(QTestState *qts, uint32_t val) +{ + qtest_writel(qts, TE_BASE + A_TR_TE_CONTROL, val); +} + +static uint64_t test_read_tram_ramstart(QTestState *qts) +{ + uint64_t reg =3D qtest_readl(qts, TRAM_BASE + A_TR_RAM_START_HIGH); + + reg <<=3D 32; + reg +=3D qtest_readl(qts, TRAM_BASE + A_TR_RAM_START_LOW); + return reg; +} + +static uint64_t test_read_tram_writep(QTestState *qts) +{ + uint64_t reg =3D qtest_readl(qts, TRAM_BASE + A_TR_RAM_WP_HIGH); + + reg <<=3D 32; + reg +=3D qtest_readl(qts, TRAM_BASE + A_TR_RAM_WP_LOW); + return reg; +} + +static void test_trace_simple(void) +{ + QTestState *qts =3D qtest_init("-machine virt -accel tcg"); + double timeout_sec =3D 0.5; + uint64_t reg_tram_start, reg_tram_writep; + uint32_t reg; + + reg =3D test_read_te_control(qts); + reg =3D FIELD_DP32(reg, TR_TE_CONTROL, ACTIVE, 1); + test_write_te_control(qts, reg); + reg =3D test_read_te_control(qts); + g_assert(1 =3D=3D FIELD_EX32(reg, TR_TE_CONTROL, ACTIVE)); + + reg =3D FIELD_DP32(reg, TR_TE_CONTROL, ENABLE, 1); + test_write_te_control(qts, reg); + reg =3D test_read_te_control(qts); + g_assert(1 =3D=3D FIELD_EX32(reg, TR_TE_CONTROL, ENABLE)); + + /* + * Verify if RAM Sink write pointer is equal to + * ramstart before start tracing. + */ + reg_tram_start =3D test_read_tram_ramstart(qts); + g_assert(reg_tram_start > 0); + reg_tram_writep =3D test_read_tram_writep(qts); + g_assert(reg_tram_writep =3D=3D reg_tram_start); + + reg =3D FIELD_DP32(reg, TR_TE_CONTROL, INST_TRACING, 1); + test_write_te_control(qts, reg); + reg =3D test_read_te_control(qts); + g_assert(1 =3D=3D FIELD_EX32(reg, TR_TE_CONTROL, INST_TRACING)); + + g_test_timer_start(); + for (;;) { + reg_tram_writep =3D test_read_tram_writep(qts); + if (reg_tram_writep > reg_tram_start) { + break; + } + + g_assert(g_test_timer_elapsed() <=3D timeout_sec); + } + + qtest_quit(qts); +} + +int main(int argc, char *argv[]) +{ + g_test_init(&argc, &argv, NULL); + qtest_add_func("/riscv-trace-test/test-trace-simple", + test_trace_simple); + return g_test_run(); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624631152158500 Content-Type: text/plain; charset="utf-8" The trap message consists of a Format 3 Subformat 1 e-trace message. According to the Efficient Trace for RISC-V spec, section "Format 3 thaddr, address and privilege fields", the 'thaddr' will be zero if: - we can't infer the EPC after an uninferable PC discontinuity (like traps). This doesn't happen in our current TCG backend - we'll always know the trap EPC in riscv_cpu_do_interrupt(); - a second interrupt/exception happens while the handler of the first trap hasn't exited. This also doesn't happen in TCG given that we do not emulate a multi-insn pipeline model, i.e. we'll only retire one insns at a time. This means that we'll always send trap packets with 'thaddr' set to 1, thus we're hardcoding it in the message helper. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/rv-trace-messages.c | 94 ++++++++++++++++++++++++++++++++++++ hw/riscv/rv-trace-messages.h | 5 ++ 2 files changed, 99 insertions(+) diff --git a/hw/riscv/rv-trace-messages.c b/hw/riscv/rv-trace-messages.c index 01ff51c715..7ea1c87fff 100644 --- a/hw/riscv/rv-trace-messages.c +++ b/hw/riscv/rv-trace-messages.c @@ -35,6 +35,24 @@ typedef struct RVTraceSyncPayload { } RVTraceSyncPayload; #define SYNC_PAYLOAD_SIZE_64BITS 9 =20 +/* + * Format 3 subformat 1 without 'time' and 'context' fields + */ +typedef struct RVTraceTrapPayload { + uint8_t format:2; + uint8_t subformat:2; + uint8_t branch:1; + uint8_t privilege:3; + uint8_t ecause:6; + uint8_t interrupt:1; + uint8_t thaddr:1; + uint32_t addressLow; + uint32_t addressHigh; + uint32_t tvalLow; + uint32_t tvalHigh; +} RVTraceTrapPayload; +#define TRAP_PAYLOAD_SIZE_64BITS 18 + static void rv_etrace_write_bits(uint8_t *bytes, uint32_t bit_pos, uint32_t num_bits, uint32_t val) { @@ -92,3 +110,79 @@ size_t rv_etrace_gen_encoded_sync_msg(uint8_t *buf, uin= t64_t pc, =20 return HEADER_SIZE + SYNC_PAYLOAD_SIZE_64BITS; } + +/* + * Note: this function assumes thaddr =3D 1. + */ +size_t rv_etrace_gen_encoded_trap_msg(uint8_t *buf, uint64_t trap_addr, + TracePrivLevel priv_level, + uint8_t ecause, + bool is_interrupt, + uint64_t tval) +{ + RVTraceTrapPayload payload =3D {.format =3D 0b11, + .subformat =3D 0b01, + .branch =3D 1, + .privilege =3D priv_level, + .ecause =3D ecause}; + RVTraceMessageHeader header =3D {.flow =3D 0, .extend =3D 0, + .length =3D TRAP_PAYLOAD_SIZE_64BITS}; + uint8_t bit_pos; + + payload.addressLow =3D extract64(trap_addr, 0, 32); + payload.addressHigh =3D extract64(trap_addr, 32, 32); + + /* + * When interrupt =3D 1 'tval' is ommited. Take 8 bytes + * from the final size. + */ + if (is_interrupt) { + header.length =3D TRAP_PAYLOAD_SIZE_64BITS - 8; + } + + rv_etrace_write_header(buf, header); + bit_pos =3D 8; + + rv_etrace_write_bits(buf, bit_pos, 2, payload.format); + bit_pos +=3D 2; + rv_etrace_write_bits(buf, bit_pos, 2, payload.subformat); + bit_pos +=3D 2; + rv_etrace_write_bits(buf, bit_pos, 1, payload.branch); + bit_pos +=3D 1; + rv_etrace_write_bits(buf, bit_pos, 3, payload.privilege); + bit_pos +=3D 3; + + rv_etrace_write_bits(buf, bit_pos, 6, payload.ecause); + bit_pos +=3D 6; + + if (is_interrupt) { + rv_etrace_write_bits(buf, bit_pos, 1, 1); + } else { + rv_etrace_write_bits(buf, bit_pos, 1, 0); + } + bit_pos +=3D 1; + + /* thaddr is hardcoded to 1 for now */ + rv_etrace_write_bits(buf, bit_pos, 1, 1); + bit_pos +=3D 1; + + rv_etrace_write_bits(buf, bit_pos, 32, payload.addressLow); + bit_pos +=3D 32; + rv_etrace_write_bits(buf, bit_pos, 32, payload.addressHigh); + bit_pos +=3D 32; + + /* Skip trap_addr if is_interrupt */ + if (is_interrupt) { + goto out; + } + + payload.tvalLow =3D extract64(trap_addr, 0, 32); + payload.tvalHigh =3D extract64(trap_addr, 32, 32); + + rv_etrace_write_bits(buf, bit_pos, 32, payload.tvalLow); + bit_pos +=3D 32; + rv_etrace_write_bits(buf, bit_pos, 32, payload.tvalHigh); + +out: + return HEADER_SIZE + header.length; +} diff --git a/hw/riscv/rv-trace-messages.h b/hw/riscv/rv-trace-messages.h index c7226b50a9..f210e048dd 100644 --- a/hw/riscv/rv-trace-messages.h +++ b/hw/riscv/rv-trace-messages.h @@ -21,5 +21,10 @@ typedef enum { =20 size_t rv_etrace_gen_encoded_sync_msg(uint8_t *buf, uint64_t pc, TracePrivLevel priv_level); +size_t rv_etrace_gen_encoded_trap_msg(uint8_t *buf, uint64_t trap_addr, + TracePrivLevel priv_level, + uint8_t ecause, + bool is_interrupt, + uint64_t tval); =20 #endif --=20 2.43.0 From nobody Fri Oct 23 21:01:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792624629; cv=none; d=zohomail.com; s=zohoarc; b=ewsc3LjCemponzIR+Rn1LRZq+MiA4zWPY2WTfa4LCLRDgINQO9ZdoD8JLNsyYWAdWCN8zpB/VC7UJmXXKG5tQhdkgMJGvHFdSaN2UMoymOtQwEQx1aW+UPmexHa18COIdje+Edvz4pGus6DdtRPwSbXm0QyhX02fpWPEm8lV6WU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792624629; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=umQBs0jc4pQgaMYkFT6HH+2iJmSyQyXzAG5XzBVFQBA=; b=SexlJHnFXL3WO5tD+Jln/xEHUxaD1NoTCh9cGzoUIII65OKhCvVBxP/qwIiTF2fh/YTIuU9o2Z3xKuPgREN3ZTUa5zKroaABrk3OqQSqem0BUgeZvZ4Z+34Z0xaWOLb4NyZursdyRhndWLuwWpKZInV8XB87Z99cztDYsv0iQfo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792624629952255.15053471086082; Wed, 21 Oct 2026 16:17:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJfW6-0007fJ-43; Wed, 21 Oct 2026 19:14:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJfW1-0007cC-EI for qemu-devel@nongnu.org; Wed, 21 Oct 2026 19:14:37 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJfVy-00051Q-3Y for qemu-devel@nongnu.org; Wed, 21 Oct 2026 19:14:37 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69LKdwmv816935 for ; Wed, 21 Oct 2026 23:14:32 GMT Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hex58a92d-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 21 Oct 2026 23:14:31 +0000 (GMT) Received: by mail-qt1-f200.google.com with SMTP id d75a77b69052e-53380b67cfdso29475521cf.1 for ; Wed, 21 Oct 2026 16:14:31 -0700 (PDT) Received: from QCOM-UWl2o8bcGT.qualcomm.com (200-204-190-237.dsl.telesp.net.br. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624631115158500 Content-Type: text/plain; charset="utf-8" Use the rv_etrace_gen_encoded_trap_msg() helper we added in the previous patch to encode trap packets to be written in the RAM sink SMEM. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/trace-encoder.c | 17 +++++++++++++++++ hw/riscv/trace-encoder.h | 4 ++++ target/riscv/tcg/cpu_helper.c | 13 +++++++++++++ 3 files changed, 34 insertions(+) diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c index 2b358b2699..0e912952eb 100644 --- a/hw/riscv/trace-encoder.c +++ b/hw/riscv/trace-encoder.c @@ -404,6 +404,23 @@ void trencoder_set_first_trace_insn(Object *trencoder_= obj, uint64_t pc) trencoder_send_message_smem(trencoder, msg, msg_size); } =20 +void trencoder_trace_trap_insn(Object *trencoder_obj, + uint64_t pc, uint32_t ecause, + bool is_interrupt, + uint64_t tval) +{ + TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); + TracePrivLevel priv =3D trencoder_get_curr_priv_level(trencoder); + g_autofree uint8_t *msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); + uint8_t msg_size; + + msg_size =3D rv_etrace_gen_encoded_trap_msg(msg, pc, priv, + ecause, is_interrupt, + tval); + + trencoder_send_message_smem(trencoder, msg, msg_size); +} + static const Property trencoder_props[] =3D { /* * We need a link to the associated CPU to diff --git a/hw/riscv/trace-encoder.h b/hw/riscv/trace-encoder.h index 1801193e15..75645218ba 100644 --- a/hw/riscv/trace-encoder.h +++ b/hw/riscv/trace-encoder.h @@ -46,5 +46,9 @@ struct TraceEncoder { OBJECT_DECLARE_SIMPLE_TYPE(TraceEncoder, TRACE_ENCODER) =20 void trencoder_set_first_trace_insn(Object *trencoder_obj, uint64_t pc); +void trencoder_trace_trap_insn(Object *trencoder_obj, + uint64_t pc, uint32_t ecause, + bool is_interrupt, + uint64_t tval); =20 #endif diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 58e98e975c..8bacf0ca59 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -40,6 +40,10 @@ #include "pmp.h" #include "qemu/plugin.h" =20 +#ifndef CONFIG_USER_ONLY +#include "hw/riscv/trace-encoder.h" +#endif + int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY @@ -2300,6 +2304,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); =20 + if (cpu->trencoder) { + TraceEncoder *te =3D TRACE_ENCODER(cpu->trencoder); + + if (te->trace_running) { + trencoder_trace_trap_insn(cpu->trencoder, env->pc, + cause, async, tval); + } + } + mode =3D env->priv <=3D PRV_S && cause < 64 && (((deleg >> cause) & 1) || s_injected || vs_injected) ? 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Wed, 21 Oct 2026 16:14:33 -0700 (PDT) X-Received: by 2002:a05:622a:301:b0:533:3627:49fd with SMTP id d75a77b69052e-5369b8055a9mr64006631cf.18.1792624473068; Wed, 21 Oct 2026 16:14:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, antikostya2@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH v4 12/18] target/riscv, hw/riscv: send trace ppccd packets Date: Wed, 21 Oct 2026 20:13:39 -0300 Message-ID: <20261021231346.2452179-13-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261021231346.2452179-1-daniel.barboza@oss.qualcomm.com> References: <20261021231346.2452179-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA5MiBTYWx0ZWRfX7V6Gfz9GRLsU VtZnW+Gv478mqiK4hIrHvGXZELfxwU7X7SqKkfz6qJESGi166EvjF+pAwPNe85LbuoX1+JhrV/Z hGSViDDqsma2CwNXmz/slTXVu5wNdio= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA5MiBTYWx0ZWRfX4XS4D0GQHuzn HPlF6er20dcRvgOhmviIqO2yhrKJu5tYPc0HhcuKgzDLy6ANrBtgZWupN0SRPMNX3C+7NatcVrx fydhadmWwrxcNk+aQ+XsXgkdddJRi6oMoumRnPjyDdlbrWw4v1ypnQvt9WaUhDbM9YWm3wSli9c wMRbd2JA6j3IKZ7hSAsz11PZSfc3HSFIlumhQ/pVvTOu51fAygasT6pVf31OcyXKYC6Vx3iu/ph Cz/uxQU2zypdCz1BK7pfw60KusdP10BsFlcZls0DIHXQAff7qbiaBy+F7VofklHKwnfkJDF+shs hMzXWq8GAoE/oQ8NQNIeaaUWqUB+vxKiPNSmHE5IClrxoR1hrPQEsHFPOQ+WUKRQy1Sv2S8OlKu WlYtjtTGNSEBiOCm11UpQtjVyao37L/O/nB5eqyiP/GQkz6Vjf6S9SKrJSyUxcQI04nJPEfNk4w r0rZzLpjMqs3nPig9tg== X-Proofpoint-ORIG-GUID: x6fXZMklyFMhJutTbess6u_OwZfzjABc X-Proofpoint-GUID: x6fXZMklyFMhJutTbess6u_OwZfzjABc X-Authority-Analysis: v=2.4 cv=K/+3jCWI c=1 sm=1 tr=0 ts=6ad9475a cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=QmVDPCq3bE4LYXGvZ20s0w==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=AAlH0JvuWwwlC_hcYokA:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210092 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624565948158500 Content-Type: text/plain; charset="utf-8" The ppccd (privilege change) trace packets consists of sync packets like we already sent during trace start and resyncs. The privilege change is being fetched via riscv_cpu_set_mode(). Signed-off-by: Daniel Henrique Barboza --- hw/riscv/trace-encoder.c | 18 ++++++++++++++++++ hw/riscv/trace-encoder.h | 1 + target/riscv/tcg/cpu_helper.c | 13 ++++++++++++- 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c index 0e912952eb..b2e2707e0c 100644 --- a/hw/riscv/trace-encoder.c +++ b/hw/riscv/trace-encoder.c @@ -390,6 +390,19 @@ static void trencoder_send_message_smem(TraceEncoder *= trencoder, trencoder_update_ramsink_writep(trencoder, dest, wrapped); } =20 +static void trencoder_send_sync_msg(Object *trencoder_obj, uint64_t pc) +{ + TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); + TracePrivLevel priv =3D trencoder_get_curr_priv_level(trencoder); + g_autofree uint8_t *msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); + uint8_t msg_size; + + trencoder->first_pc =3D pc; + msg_size =3D rv_etrace_gen_encoded_sync_msg(msg, pc, priv); + + trencoder_send_message_smem(trencoder, msg, msg_size); +} + void trencoder_set_first_trace_insn(Object *trencoder_obj, uint64_t pc) { TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); @@ -421,6 +434,11 @@ void trencoder_trace_trap_insn(Object *trencoder_obj, trencoder_send_message_smem(trencoder, msg, msg_size); } =20 +void trencoder_trace_ppccd(Object *trencoder_obj, uint64_t pc) +{ + trencoder_send_sync_msg(trencoder_obj, pc); +} + static const Property trencoder_props[] =3D { /* * We need a link to the associated CPU to diff --git a/hw/riscv/trace-encoder.h b/hw/riscv/trace-encoder.h index 75645218ba..64e19c5752 100644 --- a/hw/riscv/trace-encoder.h +++ b/hw/riscv/trace-encoder.h @@ -50,5 +50,6 @@ void trencoder_trace_trap_insn(Object *trencoder_obj, uint64_t pc, uint32_t ecause, bool is_interrupt, uint64_t tval); +void trencoder_trace_ppccd(Object *trencoder_obj, uint64_t pc); =20 #endif diff --git a/target/riscv/tcg/cpu_helper.c b/target/riscv/tcg/cpu_helper.c index 8bacf0ca59..f23b89ccf2 100644 --- a/target/riscv/tcg/cpu_helper.c +++ b/target/riscv/tcg/cpu_helper.c @@ -943,11 +943,22 @@ void riscv_cpu_set_mode(CPURISCVState *env, privilege= _mode_t newpriv, { g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); =20 + CPUState *cs =3D env_cpu(env); + if (newpriv !=3D env->priv || env->virt_enabled !=3D virt_en) { if (icount_enabled()) { riscv_itrigger_update_priv(env); } =20 + if (newpriv !=3D env->priv) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (cpu->trencoder && + TRACE_ENCODER(cpu->trencoder)->trace_running) { + trencoder_trace_ppccd(cpu->trencoder, env->pc); + } + } + riscv_pmu_update_fixed_ctrs(env, newpriv, virt_en); } =20 @@ -968,7 +979,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, privilege_m= ode_t newpriv, if (riscv_has_ext(env, RVH)) { /* Flush the TLB on all virt mode changes. */ if (env->virt_enabled !=3D virt_en) { - tlb_flush(env_cpu(env)); + tlb_flush(cs); } =20 env->virt_enabled =3D virt_en; --=20 2.43.0 From nobody Fri Oct 23 21:01:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624523000158500 Content-Type: text/plain; charset="utf-8" Before handling updiscon (uninferable PC discontinuity) cases add the encoded message we're going to use, format 2. Format 1 will be added when we add the branch map. There are design decisions worth documenting in this patch. For irreport, the e-trace-encap spec [1] in section 7.6. "Format 2 packets", says that we should make this bit !updiscon if we're either: "following a return because its address differs from the predicted return address at the top of the implicit_return return address stack, or the last retired before an exception, interrupt, privilege change or resync because it is necessary to report the current address stack depth or nested call count." We do not implement any form of call/return prediction in the encoder, and TCG will always retire a single insn per cycle. This means that we'll never set irreport, i.e. irreport will always be equal to updiscon. If this interpretation turns out to be wrong we'll revisit this helper. Likewise, irdepth is also not implemented since we'll always return a package where irreport =3D=3D updiscon. The size of the field is arbitrarily set to '3' to avoid adding padding in the end of the msg to complete an extra byte. [1] https://github.com/riscv-non-isa/e-trace-encap/releases/tag/v1.0 Signed-off-by: Daniel Henrique Barboza --- hw/riscv/rv-trace-messages.c | 59 ++++++++++++++++++++++++++++++++++++ hw/riscv/rv-trace-messages.h | 2 ++ 2 files changed, 61 insertions(+) diff --git a/hw/riscv/rv-trace-messages.c b/hw/riscv/rv-trace-messages.c index 7ea1c87fff..83d3436e2e 100644 --- a/hw/riscv/rv-trace-messages.c +++ b/hw/riscv/rv-trace-messages.c @@ -53,6 +53,17 @@ typedef struct RVTraceTrapPayload { } RVTraceTrapPayload; #define TRAP_PAYLOAD_SIZE_64BITS 18 =20 +typedef struct RVTraceFormat2Payload { + uint8_t format:2; + uint32_t addressLow; + uint32_t addressHigh; + uint8_t notify:1; + uint8_t updiscon:1; + uint8_t irreport:1; + uint8_t irdepth:3; +} RVTraceFormat2Payload; +#define FORMAT2_PAYLOAD_SIZE_64BITS 9 + static void rv_etrace_write_bits(uint8_t *bytes, uint32_t bit_pos, uint32_t num_bits, uint32_t val) { @@ -186,3 +197,51 @@ size_t rv_etrace_gen_encoded_trap_msg(uint8_t *buf, ui= nt64_t trap_addr, out: return HEADER_SIZE + header.length; } + +/* + * Note: irreport and irdepth is always =3D=3D updiscon. + * + * return_stack_size_p + call_counter_size_p is hardcoded + * to 3 since we don't implement neither ATM. + */ +size_t rv_etrace_gen_encoded_format2_msg(uint8_t *buf, uint64_t addr, + bool notify, bool updiscon) +{ + RVTraceFormat2Payload payload =3D {.format =3D 0b11, + .notify =3D notify, + .updiscon =3D updiscon}; + RVTraceMessageHeader header =3D {.flow =3D 0, .extend =3D 0, + .length =3D FORMAT2_PAYLOAD_SIZE_64BITS= }; + uint8_t bit_pos; + + payload.addressLow =3D extract64(addr, 0, 32); + payload.addressHigh =3D extract64(addr, 32, 32); + + payload.irreport =3D updiscon; + if (updiscon) { + payload.irdepth =3D 0b111; + } else { + payload.irdepth =3D 0; + } + + rv_etrace_write_header(buf, header); + bit_pos =3D 8; + + rv_etrace_write_bits(buf, bit_pos, 2, payload.format); + bit_pos +=3D 2; + + rv_etrace_write_bits(buf, bit_pos, 32, payload.addressLow); + bit_pos +=3D 32; + rv_etrace_write_bits(buf, bit_pos, 32, payload.addressHigh); + bit_pos +=3D 32; + + rv_etrace_write_bits(buf, bit_pos, 1, payload.notify); + bit_pos +=3D 1; + rv_etrace_write_bits(buf, bit_pos, 1, payload.updiscon); + bit_pos +=3D 1; + rv_etrace_write_bits(buf, bit_pos, 1, payload.irreport); + bit_pos +=3D 1; + rv_etrace_write_bits(buf, bit_pos, 3, payload.irdepth); + + return HEADER_SIZE + header.length; +} diff --git a/hw/riscv/rv-trace-messages.h b/hw/riscv/rv-trace-messages.h index f210e048dd..89f30e7d36 100644 --- a/hw/riscv/rv-trace-messages.h +++ b/hw/riscv/rv-trace-messages.h @@ -26,5 +26,7 @@ size_t rv_etrace_gen_encoded_trap_msg(uint8_t *buf, uint6= 4_t trap_addr, uint8_t ecause, bool is_interrupt, uint64_t tval); +size_t rv_etrace_gen_encoded_format2_msg(uint8_t *buf, uint64_t addr, + bool notify, bool updiscon); =20 #endif --=20 2.43.0 From nobody Fri Oct 23 21:01:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 21 Oct 2026 16:14:38 -0700 (PDT) X-Received: by 2002:a05:622a:1aa5:b0:536:6902:db04 with SMTP id d75a77b69052e-5369bb9b16emr55839861cf.75.1792624478067; Wed, 21 Oct 2026 16:14:38 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, chao.liu@processmission.com, antikostya2@gmail.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH v4 14/18] hw/riscv, target/riscv: send resync updiscon trace packets Date: Wed, 21 Oct 2026 20:13:41 -0300 Message-ID: <20261021231346.2452179-15-daniel.barboza@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261021231346.2452179-1-daniel.barboza@oss.qualcomm.com> References: <20261021231346.2452179-1-daniel.barboza@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA5MiBTYWx0ZWRfXwba38xLQ3lNg X/eZRKsJk0ZbGhItFHNHKZZ4Ppmt33jC4SYLflu/nZKnR2y8R023LbZBEgFez5fBOazHDHGmOT4 z/r2TFKLIMVHFpRTXIuYspaOcCVXqP4= X-Authority-Analysis: v=2.4 cv=eJaGH3p1 c=1 sm=1 tr=0 ts=6ad9475f cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=QmVDPCq3bE4LYXGvZ20s0w==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=v6o39jtdX7kFEx2kGjIA:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: 8FBOQRyrqy48SWeBMkID5RZyT-AdwCOn X-Proofpoint-ORIG-GUID: 8FBOQRyrqy48SWeBMkID5RZyT-AdwCOn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA5MiBTYWx0ZWRfX6mRUp1PeG8L4 osiKEyodDbC7lH4i7usRr6JNXnExTM6u2sZtaoebSiN8qdNKFu0ZnEY+a5uNwwyR8HzsdClMkLH 4Cb+sDSuz06clqsAWvVxfDPp8CcrnbETbDcsBuU+9xLHYwrnvVK/1YWKbqZsgQFNt6NrC9vBV3A 6r1Trq1DVXmRmhLipATqNMTtBGHyXfJGj9V2u625NmdrA29Vy3CXuw92hWNRhCVZmF544soct4l 62Jr06XESbMuzjjy1Nr0iNMOJFiPSx4gs/pTiK942cdMsNKArhiG1rLfEuU8m90kxr+frozzjL+ jeeo7J1FBKG8bKyVHBkQFy6Ef6UlApTaXGyYnjGsw4OJn+jrezcSRR88Jl+6V8KCO/51cXfKHix ji7XSTlbhM6D6+Fd70APLe4R1IRkOnOR+qOxP1aLTwlvs63eJNM/h7QMaJMX6HVxeIJyxXR/YvM zOymDX8oiO0wFF0ZEBw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 adultscore=0 spamscore=0 clxscore=1015 bulkscore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210092 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624559824158501 Content-Type: text/plain; charset="utf-8" Send updiscon packets based on the constraints already discussed in the previous patch: - We do not implement any form of call/return prediction in the encoder, and TCG will always retire a single insn per cycle, e.g. irreport will always be equal to updiscon; - irdepth is not implemented since we'll always return a package where irreport =3D=3D updiscon. Note that we're sending an updiscon packet if the 'updiscon_pending' flag is set when we're about the send a resync or a trap packet. The TCG helper in this case is just setting the trace encoder flags instead of actually triggering a RAM sink SMEM write. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/trace-encoder.c | 37 +++++++++++++++++++ hw/riscv/trace-encoder.h | 3 ++ target/riscv/helper.h | 1 + .../tcg/insn_trans/trans_privileged.c.inc | 11 ++++++ target/riscv/tcg/insn_trans/trans_rvi.c.inc | 2 + target/riscv/tcg/trace_helper.c | 14 +++++++ target/riscv/tcg/translate.c | 7 ++++ 7 files changed, 75 insertions(+) diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c index b2e2707e0c..b9121d93a7 100644 --- a/hw/riscv/trace-encoder.c +++ b/hw/riscv/trace-encoder.c @@ -403,6 +403,22 @@ static void trencoder_send_sync_msg(Object *trencoder_= obj, uint64_t pc) trencoder_send_message_smem(trencoder, msg, msg_size); } =20 +static void trencoder_send_updiscon(TraceEncoder *trencoder, uint64_t pc) +{ + g_autofree uint8_t *format2_msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); + uint8_t addr_msb =3D extract64(pc, 31, 1); + bool notify =3D addr_msb; + bool updiscon =3D !notify; + uint8_t msg_size; + + msg_size =3D rv_etrace_gen_encoded_format2_msg(format2_msg, pc, + notify, + updiscon); + trencoder_send_message_smem(trencoder, format2_msg, msg_size); + + trencoder->updiscon_pending =3D false; +} + void trencoder_set_first_trace_insn(Object *trencoder_obj, uint64_t pc) { TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); @@ -410,6 +426,10 @@ void trencoder_set_first_trace_insn(Object *trencoder_= obj, uint64_t pc) g_autofree uint8_t *msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); uint8_t msg_size; =20 + if (trencoder->updiscon_pending) { + trencoder_send_updiscon(trencoder, pc); + } + trencoder->first_pc =3D pc; trace_trencoder_first_trace_insn(pc); msg_size =3D rv_etrace_gen_encoded_sync_msg(msg, pc, priv); @@ -427,6 +447,10 @@ void trencoder_trace_trap_insn(Object *trencoder_obj, g_autofree uint8_t *msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); uint8_t msg_size; =20 + if (trencoder->updiscon_pending) { + trencoder_send_updiscon(trencoder, pc); + } + msg_size =3D rv_etrace_gen_encoded_trap_msg(msg, pc, priv, ecause, is_interrupt, tval); @@ -436,9 +460,22 @@ void trencoder_trace_trap_insn(Object *trencoder_obj, =20 void trencoder_trace_ppccd(Object *trencoder_obj, uint64_t pc) { + TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); + + if (trencoder->updiscon_pending) { + trencoder_send_updiscon(trencoder, pc); + } + trencoder_send_sync_msg(trencoder_obj, pc); } =20 +void trencoder_report_updiscon(Object *trencoder_obj) +{ + TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); + + trencoder->updiscon_pending =3D true; +} + static const Property trencoder_props[] =3D { /* * We need a link to the associated CPU to diff --git a/hw/riscv/trace-encoder.h b/hw/riscv/trace-encoder.h index 64e19c5752..9116fe4f56 100644 --- a/hw/riscv/trace-encoder.h +++ b/hw/riscv/trace-encoder.h @@ -36,6 +36,8 @@ struct TraceEncoder { uint32_t regs[TRACE_R_MAX]; RegisterInfo regs_info[TRACE_R_MAX]; =20 + bool updiscon_pending; + bool enabled; bool trace_running; bool trace_next_insn; @@ -51,5 +53,6 @@ void trencoder_trace_trap_insn(Object *trencoder_obj, bool is_interrupt, uint64_t tval); void trencoder_trace_ppccd(Object *trencoder_obj, uint64_t pc); +void trencoder_report_updiscon(Object *trencoder_obj); =20 #endif diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 0832159adc..68348e5473 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -132,6 +132,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) =20 /* Trace helpers (should be put inside ifdef) */ DEF_HELPER_2(trace_insn, void, env, i64) +DEF_HELPER_1(trace_updiscon, void, env) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) diff --git a/target/riscv/tcg/insn_trans/trans_privileged.c.inc b/target/ri= scv/tcg/insn_trans/trans_privileged.c.inc index e22df6fbe7..531eb40595 100644 --- a/target/riscv/tcg/insn_trans/trans_privileged.c.inc +++ b/target/riscv/tcg/insn_trans/trans_privileged.c.inc @@ -26,6 +26,8 @@ =20 static bool trans_ecall(DisasContext *ctx, arg_ecall *a) { + gen_trace_updiscon(ctx); + /* always generates U-level ECALL, fixed in do_interrupt handler */ generate_exception(ctx, RISCV_EXCP_U_ECALL); return true; @@ -40,6 +42,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) uint32_t ebreak =3D 0; uint32_t post =3D 0; =20 + gen_trace_updiscon(ctx); + /* * The RISC-V semihosting spec specifies the following * three-instruction sequence to flag a semihosting call: @@ -101,6 +105,8 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY if (has_ext(ctx, RVS)) { + gen_trace_updiscon(ctx); + decode_save_opc(ctx, 0); translator_io_start(&ctx->base); gen_update_pc(ctx, 0); @@ -119,6 +125,8 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY + gen_trace_updiscon(ctx); + decode_save_opc(ctx, 0); translator_io_start(&ctx->base); gen_update_pc(ctx, 0); @@ -153,6 +161,9 @@ static bool trans_mnret(DisasContext *ctx, arg_mnret *a) { #ifndef CONFIG_USER_ONLY REQUIRE_SMRNMI(ctx); + + gen_trace_updiscon(ctx); + decode_save_opc(ctx, 0); gen_helper_mnret(cpu_pc, tcg_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ diff --git a/target/riscv/tcg/insn_trans/trans_rvi.c.inc b/target/riscv/tcg= /insn_trans/trans_rvi.c.inc index cc1b5dbbad..2de67c1a88 100644 --- a/target/riscv/tcg/insn_trans/trans_rvi.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvi.c.inc @@ -183,6 +183,8 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) } } =20 + gen_trace_updiscon(ctx); + lookup_and_goto_ptr(ctx); =20 if (misaligned) { diff --git a/target/riscv/tcg/trace_helper.c b/target/riscv/tcg/trace_helpe= r.c index 5a6d725f56..a4c5720a65 100644 --- a/target/riscv/tcg/trace_helper.c +++ b/target/riscv/tcg/trace_helper.c @@ -28,9 +28,23 @@ void helper_trace_insn(CPURISCVState *env, uint64_t pc) te->trace_next_insn =3D false; } } + +void helper_trace_updiscon(CPURISCVState *env) +{ + RISCVCPU *cpu =3D env_archcpu(env); + TraceEncoder *te =3D TRACE_ENCODER(cpu->trencoder); + + te->updiscon_pending =3D true; + te->trace_next_insn =3D true; +} #else /* #ifndef CONFIG_USER_ONLY */ void helper_trace_insn(CPURISCVState *env, uint64_t pc) { return; } + +void helper_trace_updiscon(CPURISCVState *env) +{ + return; +} #endif /* #ifndef CONFIG_USER_ONLY*/ diff --git a/target/riscv/tcg/translate.c b/target/riscv/tcg/translate.c index fb82a6b2fa..7f6dc6e9e3 100644 --- a/target/riscv/tcg/translate.c +++ b/target/riscv/tcg/translate.c @@ -627,6 +627,13 @@ static void gen_ctr_jal(DisasContext *ctx, int rd, tar= get_ulong imm) } #endif =20 +static void gen_trace_updiscon(DisasContext *ctx) +{ + if (ctx->cpu_trace_running) { + gen_helper_trace_updiscon(tcg_env); + } +} + static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) { TCGv succ_pc =3D dest_gpr(ctx, rd); --=20 2.43.0 From nobody Fri Oct 23 21:01:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624543724158500 Content-Type: text/plain; charset="utf-8" Add encoded message helpers to send branch information trace packets. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/rv-trace-messages.c | 126 +++++++++++++++++++++++++++++++++++ hw/riscv/rv-trace-messages.h | 7 ++ 2 files changed, 133 insertions(+) diff --git a/hw/riscv/rv-trace-messages.c b/hw/riscv/rv-trace-messages.c index 83d3436e2e..46445a47da 100644 --- a/hw/riscv/rv-trace-messages.c +++ b/hw/riscv/rv-trace-messages.c @@ -64,6 +64,31 @@ typedef struct RVTraceFormat2Payload { } RVTraceFormat2Payload; #define FORMAT2_PAYLOAD_SIZE_64BITS 9 =20 +typedef struct RVTraceFormat1BasePayload { + uint8_t format:2; + uint8_t branches:5; + uint32_t branch_map:31; +} RVTraceFormat1BasePayload; +#define FORMAT1_BASE_PAYLOAD_SIZE_64BITS 5 + +typedef struct RVTraceFormat1Payload { + uint8_t format:2; + uint8_t branches:5; + uint32_t branch_map; + uint32_t addressLow; + uint32_t addressHigh; + uint8_t notify:1; + uint8_t updiscon:1; + uint8_t irreport:1; + uint8_t irdepth:3; +} RVTraceFormat1Payload; + +/* + * FORMAT2_PAYLOAD_SIZE_64BITS =3D 9 plus 5 bits of 'branches', + * plus minimal 3 bits of 'branch_map' =3D 10 bytes. + */ +#define FORMAT1_PAYLOAD_MIN_SIZE_64BITS 10 + static void rv_etrace_write_bits(uint8_t *bytes, uint32_t bit_pos, uint32_t num_bits, uint32_t val) { @@ -245,3 +270,104 @@ size_t rv_etrace_gen_encoded_format2_msg(uint8_t *buf= , uint64_t addr, =20 return HEADER_SIZE + header.length; } + +size_t rv_etrace_gen_encoded_format1_noaddr(uint8_t *buf, + uint8_t branches, + uint32_t branch_map) +{ + RVTraceMessageHeader header =3D {.flow =3D 0, .extend =3D 0, + .length =3D FORMAT1_BASE_PAYLOAD_SIZE_64BITS}; + RVTraceFormat1BasePayload payload =3D {.format =3D 0b01, + .branches =3D branches, .branch_map =3D branch_map}; + uint8_t bit_pos; + + rv_etrace_write_header(buf, header); + bit_pos =3D 8; + + rv_etrace_write_bits(buf, bit_pos, 2, payload.format); + bit_pos +=3D 2; + + rv_etrace_write_bits(buf, bit_pos, 5, payload.branches); + bit_pos +=3D 5; + + rv_etrace_write_bits(buf, bit_pos, 31, payload.branch_map); + + return HEADER_SIZE + header.length; +} + +/* + * Same reservations made in the format 2 helper: + * + * - irreport and irdepth is always =3D=3D updiscon; + * + * - return_stack_size_p + call_counter_size_p is hardcoded + * to 3 since we don't implement neither ATM. + */ +size_t rv_etrace_gen_encoded_format1(uint8_t *buf, + uint8_t branches, uint32_t branch_map, + uint64_t addr, + bool notify, bool updiscon) +{ + RVTraceMessageHeader header =3D {.flow =3D 0, .extend =3D 0}; + RVTraceFormat1Payload payload =3D {.format =3D 0b01, + .branches =3D branches, + .notify =3D notify, + .updiscon =3D updiscon}; + uint8_t payload_size =3D FORMAT1_PAYLOAD_MIN_SIZE_64BITS; + uint8_t branch_map_size =3D 0; + uint8_t bit_pos; + + g_assert(branches < 32); + + if (branches <=3D 3) { + branch_map_size =3D 3; + } else if (branches <=3D 7) { + branch_map_size =3D 7; + payload_size++; + } else if (branches <=3D 15) { + branch_map_size =3D 15; + payload_size +=3D 2; + } else { + branch_map_size =3D 31; + payload_size +=3D 4; + } + + header.length =3D payload_size; + + rv_etrace_write_header(buf, header); + bit_pos =3D 8; + + payload.addressLow =3D extract64(addr, 0, 32); + payload.addressHigh =3D extract64(addr, 32, 32); + + payload.irreport =3D updiscon; + if (updiscon) { + payload.irdepth =3D 0b111; + } else { + payload.irdepth =3D 0; + } + + rv_etrace_write_bits(buf, bit_pos, 2, payload.format); + bit_pos +=3D 2; + + rv_etrace_write_bits(buf, bit_pos, 5, payload.branches); + bit_pos +=3D 5; + + rv_etrace_write_bits(buf, bit_pos, branch_map_size, payload.branch_map= ); + bit_pos +=3D branch_map_size; + + rv_etrace_write_bits(buf, bit_pos, 32, payload.addressLow); + bit_pos +=3D 32; + rv_etrace_write_bits(buf, bit_pos, 32, payload.addressHigh); + bit_pos +=3D 32; + + rv_etrace_write_bits(buf, bit_pos, 1, payload.notify); + bit_pos +=3D 1; + rv_etrace_write_bits(buf, bit_pos, 1, payload.updiscon); + bit_pos +=3D 1; + rv_etrace_write_bits(buf, bit_pos, 1, payload.irreport); + bit_pos +=3D 1; + rv_etrace_write_bits(buf, bit_pos, 3, payload.irdepth); + + return HEADER_SIZE + header.length; +} diff --git a/hw/riscv/rv-trace-messages.h b/hw/riscv/rv-trace-messages.h index 89f30e7d36..f8f1830852 100644 --- a/hw/riscv/rv-trace-messages.h +++ b/hw/riscv/rv-trace-messages.h @@ -28,5 +28,12 @@ size_t rv_etrace_gen_encoded_trap_msg(uint8_t *buf, uint= 64_t trap_addr, uint64_t tval); size_t rv_etrace_gen_encoded_format2_msg(uint8_t *buf, uint64_t addr, bool notify, bool updiscon); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624584245158500 Content-Type: text/plain; charset="utf-8" Branch info is reported via the TCG helpers, updating the trace encoder internal branch map. Branch packets are sent in two circunstances: - when the branch map is full; - when an updiscon packet is about to be sent and the branch map isn't empty. The former will trigger a Format 1 no-addr packet, the latter a Format 1 with the updiscon address. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/trace-encoder.c | 52 ++++++++++++++++++++- hw/riscv/trace-encoder.h | 4 ++ target/riscv/helper.h | 1 + target/riscv/tcg/insn_trans/trans_rvi.c.inc | 11 +++++ target/riscv/tcg/trace_helper.c | 12 +++++ 5 files changed, 79 insertions(+), 1 deletion(-) diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c index b9121d93a7..290e648083 100644 --- a/hw/riscv/trace-encoder.c +++ b/hw/riscv/trace-encoder.c @@ -30,6 +30,8 @@ */ #define TRACE_MSG_MAX_SIZE 32 =20 +#define TRACE_MAX_BRANCHES 31 + static TracePrivLevel trencoder_get_curr_priv_level(TraceEncoder *te) { CPURISCVState *env =3D &te->cpu->env; @@ -314,6 +316,9 @@ static void trencoder_reset(DeviceState *dev) te->trace_running =3D false; te->trace_next_insn =3D false; env->trace_running =3D false; + + te->branch_map =3D 0; + te->branches =3D 0; } =20 static void trencoder_realize(DeviceState *dev, Error **errp) @@ -411,9 +416,20 @@ static void trencoder_send_updiscon(TraceEncoder *tren= coder, uint64_t pc) bool updiscon =3D !notify; uint8_t msg_size; =20 - msg_size =3D rv_etrace_gen_encoded_format2_msg(format2_msg, pc, + if (trencoder->branches > 0) { + msg_size =3D rv_etrace_gen_encoded_format1(format2_msg, + trencoder->branches, + trencoder->branch_map, + pc, notify, updiscon); + trencoder->branches =3D 0; + } else { + msg_size =3D rv_etrace_gen_encoded_format2_msg(format2_msg, pc, + notify, + updiscon); + } + trencoder_send_message_smem(trencoder, format2_msg, msg_size); =20 trencoder->updiscon_pending =3D false; @@ -458,6 +474,40 @@ void trencoder_trace_trap_insn(Object *trencoder_obj, trencoder_send_message_smem(trencoder, msg, msg_size); } =20 +static void trencoder_send_branch_map(Object *trencoder_obj) +{ + TraceEncoder *te =3D TRACE_ENCODER(trencoder_obj); + g_autofree uint8_t *msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); + uint8_t msg_size; + + msg_size =3D rv_etrace_gen_encoded_format1_noaddr(msg, + te->branches, + te->branch_map); + trencoder_send_message_smem(te, msg, msg_size); +} + +void trencoder_report_branch(Object *trencoder_obj, uint64_t pc, bool take= n) +{ + TraceEncoder *te =3D TRACE_ENCODER(trencoder_obj); + + /* + * Note: the e-trace spec determines the value '1' for a + * branch *not* taken. The helper API is using taken =3D 1 + * to be more intuitive when reading TCG code. + */ + if (!taken) { + te->branch_map =3D deposit32(te->branch_map, te->branches, 1, 1); + } + + te->last_branch_pc =3D pc; + te->branches++; + + if (te->branches =3D=3D TRACE_MAX_BRANCHES) { + trencoder_send_branch_map(trencoder_obj); + te->branches =3D 0; + } +} + void trencoder_trace_ppccd(Object *trencoder_obj, uint64_t pc) { TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); diff --git a/hw/riscv/trace-encoder.h b/hw/riscv/trace-encoder.h index 9116fe4f56..0fc24bc967 100644 --- a/hw/riscv/trace-encoder.h +++ b/hw/riscv/trace-encoder.h @@ -28,6 +28,9 @@ struct TraceEncoder { uint32_t reg_mem_size; =20 uint64_t first_pc; + uint64_t last_branch_pc; + uint32_t branch_map; + uint8_t branches; =20 hwaddr baseaddr; hwaddr dest_baseaddr; @@ -54,5 +57,6 @@ void trencoder_trace_trap_insn(Object *trencoder_obj, uint64_t tval); void trencoder_trace_ppccd(Object *trencoder_obj, uint64_t pc); void trencoder_report_updiscon(Object *trencoder_obj); +void trencoder_report_branch(Object *trencoder_obj, uint64_t pc, bool take= n); =20 #endif diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 68348e5473..2d4392807b 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -133,6 +133,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) /* Trace helpers (should be put inside ifdef) */ DEF_HELPER_2(trace_insn, void, env, i64) DEF_HELPER_1(trace_updiscon, void, env) +DEF_HELPER_3(trace_branch, void, env, tl, int) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) diff --git a/target/riscv/tcg/insn_trans/trans_rvi.c.inc b/target/riscv/tcg= /insn_trans/trans_rvi.c.inc index 2de67c1a88..8b32686073 100644 --- a/target/riscv/tcg/insn_trans/trans_rvi.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvi.c.inc @@ -268,6 +268,13 @@ static void gen_setcond_i128(TCGv rl, TCGv rh, tcg_gen_movi_tl(rh, 0); } =20 +static void gen_trace_branch(DisasContext *ctx, int taken) +{ + if (ctx->cpu_trace_running) { + gen_helper_trace_branch(tcg_env, cpu_pc, tcg_constant_i32(taken)); + } +} + static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) { TCGLabel *l =3D gen_new_label(); @@ -299,11 +306,15 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, T= CGCond cond) } #endif =20 + gen_trace_branch(ctx, 0); + gen_goto_tb(ctx, 1, ctx->cur_insn_len); ctx->pc_save =3D orig_pc_save; =20 gen_set_label(l); /* branch taken */ =20 + gen_trace_branch(ctx, 1); + if (!riscv_cpu_allow_16bit_insn(ctx->cfg_ptr, ctx->priv_ver, ctx->misa_ext) && diff --git a/target/riscv/tcg/trace_helper.c b/target/riscv/tcg/trace_helpe= r.c index a4c5720a65..cd57641d9b 100644 --- a/target/riscv/tcg/trace_helper.c +++ b/target/riscv/tcg/trace_helper.c @@ -37,6 +37,13 @@ void helper_trace_updiscon(CPURISCVState *env) te->updiscon_pending =3D true; te->trace_next_insn =3D true; } + +void helper_trace_branch(CPURISCVState *env, target_ulong pc, int taken) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + trencoder_report_branch(cpu->trencoder, pc, taken); +} #else /* #ifndef CONFIG_USER_ONLY */ void helper_trace_insn(CPURISCVState *env, uint64_t pc) { @@ -47,4 +54,9 @@ void helper_trace_updiscon(CPURISCVState *env) { return; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624653532158500 Content-Type: text/plain; charset="utf-8" Now that we have a working branch map update the branch bit in sync messages by checking if the sync address is a branch address that was taken (or not). Signed-off-by: Daniel Henrique Barboza --- hw/riscv/rv-trace-messages.c | 6 +++--- hw/riscv/rv-trace-messages.h | 3 ++- hw/riscv/trace-encoder.c | 30 ++++++++++++++++++++++++++++-- 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/hw/riscv/rv-trace-messages.c b/hw/riscv/rv-trace-messages.c index 46445a47da..0118ca073b 100644 --- a/hw/riscv/rv-trace-messages.c +++ b/hw/riscv/rv-trace-messages.c @@ -115,11 +115,12 @@ static void rv_etrace_write_header(uint8_t *buf, RVTr= aceMessageHeader header) } =20 size_t rv_etrace_gen_encoded_sync_msg(uint8_t *buf, uint64_t pc, - TracePrivLevel priv_level) + TracePrivLevel priv_level, + bool pc_is_branch) { RVTraceSyncPayload payload =3D {.format =3D 0b11, .subformat =3D 0b00, - .branch =3D 1, + .branch =3D pc_is_branch, .privilege =3D priv_level}; RVTraceMessageHeader header =3D {.flow =3D 0, .extend =3D 0, .length =3D SYNC_PAYLOAD_SIZE_64BITS}; @@ -158,7 +159,6 @@ size_t rv_etrace_gen_encoded_trap_msg(uint8_t *buf, uin= t64_t trap_addr, { RVTraceTrapPayload payload =3D {.format =3D 0b11, .subformat =3D 0b01, - .branch =3D 1, .privilege =3D priv_level, .ecause =3D ecause}; RVTraceMessageHeader header =3D {.flow =3D 0, .extend =3D 0, diff --git a/hw/riscv/rv-trace-messages.h b/hw/riscv/rv-trace-messages.h index f8f1830852..6f700eac8e 100644 --- a/hw/riscv/rv-trace-messages.h +++ b/hw/riscv/rv-trace-messages.h @@ -20,7 +20,8 @@ typedef enum { } TracePrivLevel; =20 size_t rv_etrace_gen_encoded_sync_msg(uint8_t *buf, uint64_t pc, - TracePrivLevel priv_level); + TracePrivLevel priv_level, + bool pc_is_branch); size_t rv_etrace_gen_encoded_trap_msg(uint8_t *buf, uint64_t trap_addr, TracePrivLevel priv_level, uint8_t ecause, diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c index 290e648083..d5d5ed9563 100644 --- a/hw/riscv/trace-encoder.c +++ b/hw/riscv/trace-encoder.c @@ -395,15 +395,38 @@ static void trencoder_send_message_smem(TraceEncoder = *trencoder, trencoder_update_ramsink_writep(trencoder, dest, wrapped); } =20 +static bool trencoder_addr_is_branch_taken(TraceEncoder *te, uint64_t addr) +{ + uint8_t last_branch; + + if (te->branches =3D=3D 0) { + return false; + } + + if (te->last_branch_pc =3D=3D addr) { + last_branch =3D extract32(te->branches, te->branches - 1, 1); + + /* 0: branch taken, 1: not taken*/ + if (last_branch =3D=3D 0) { + return true; + } + } + + return false; +} + static void trencoder_send_sync_msg(Object *trencoder_obj, uint64_t pc) { TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); TracePrivLevel priv =3D trencoder_get_curr_priv_level(trencoder); g_autofree uint8_t *msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); uint8_t msg_size; + bool is_branch_taken; =20 trencoder->first_pc =3D pc; - msg_size =3D rv_etrace_gen_encoded_sync_msg(msg, pc, priv); + is_branch_taken =3D trencoder_addr_is_branch_taken(trencoder, pc); + msg_size =3D rv_etrace_gen_encoded_sync_msg(msg, pc, priv, + is_branch_taken); =20 trencoder_send_message_smem(trencoder, msg, msg_size); } @@ -441,6 +464,7 @@ void trencoder_set_first_trace_insn(Object *trencoder_o= bj, uint64_t pc) TracePrivLevel priv =3D trencoder_get_curr_priv_level(trencoder); g_autofree uint8_t *msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); uint8_t msg_size; + bool is_branch_taken; =20 if (trencoder->updiscon_pending) { trencoder_send_updiscon(trencoder, pc); @@ -448,7 +472,9 @@ void trencoder_set_first_trace_insn(Object *trencoder_o= bj, uint64_t pc) =20 trencoder->first_pc =3D pc; trace_trencoder_first_trace_insn(pc); - msg_size =3D rv_etrace_gen_encoded_sync_msg(msg, pc, priv); + is_branch_taken =3D trencoder_addr_is_branch_taken(trencoder, pc); + msg_size =3D rv_etrace_gen_encoded_sync_msg(msg, pc, priv, + is_branch_taken); =20 trencoder_send_message_smem(trencoder, msg, msg_size); } --=20 2.43.0 From nobody Fri Oct 23 21:01:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792624577; cv=none; d=zohomail.com; s=zohoarc; b=cdUFsjZGhtZYRUyUtkR0zUidfPhD7/D/jy4NrQzfk/WkaAaNsyB6RVhHNtgQ4/HWfv0f4aYnBQJ9bXdSZ+9r2Gxv3kjbNhKF+l+dEjooGF8UIeBdlgkRyJpSoj2x5w9yapnZMYxIVv80fdzbm1hLbanblDvWBKIJ3mVvVXc1NxI= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=daniel.barboza@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792624578084158500 Content-Type: text/plain; charset="utf-8" Add extra information and context about the e-trace support added in QEMU. Most of the information documented is already presented in the commit messages, albeit in a more pleasant way. Signed-off-by: Daniel Henrique Barboza --- docs/specs/index.rst | 1 + docs/specs/riscv-hwtrace.rst | 96 ++++++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 docs/specs/riscv-hwtrace.rst diff --git a/docs/specs/index.rst b/docs/specs/index.rst index 44e108db02..4c18fd5b7f 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -43,3 +43,4 @@ guest hardware that is specific to QEMU. aspeed-intc iommu-testdev s390x-secure-ipl + riscv-hwtrace diff --git a/docs/specs/riscv-hwtrace.rst b/docs/specs/riscv-hwtrace.rst new file mode 100644 index 0000000000..d9400eab00 --- /dev/null +++ b/docs/specs/riscv-hwtrace.rst @@ -0,0 +1,96 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +.. _riscv-hwtrace: + +RISC-V Hardware Trace support for RISC-V CPUs +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +QEMU implements a hardware tracing support based on the Efficient Trace +for RISC-V v2.0 specification (`etrace spec`_) and the RISC-V Trace Control +Interface Specification (`trace control spec`_). Only a subset of all +available features are implemented at this point. More features will being +added along the way, probably including support for N-trace support as wel= l. + +What is available at this moment as far as hardware model are concerned: + +- e-trace supported added in the 'virt' RISC-V machine; +- support for all TCG RISC-V CPU models, i.e. all available CPUs are able + to use the hw trace; +- topology: one trace encoder/trace ram sink pair per CPU; +- trace encoder has just the minimal bits specified in `trace control spec= `_, + section "Minimal Implementation"; +- trace ramsink has SMEM support only; +- no trace funnel support. + +A lot of considerations and simplications were made to adapt to the current +TCG RISC-V model we have in place: + +- We do not have a pipeline model for QEMU RISC-V TCG CPUs. This means + that an instruction that is emitted will be retired shortly after. Ther= e's + no concurrent insns being executed in the same CPU thread; +- all trap packets are sent with 'thaddr' set to 1 because (1) we'll always + know the trap EPC during a CPU interrupt and (2) there's no scenario whe= re + a second trap is fired while the handler of the first trap is still in + flight because, as said above, we do not have a pipeline model in QEMU + RISC-V and all insns are emitted and retired in order; +- irreport will never be set, i.e. irreport =3D=3D updiscon, because we'll + always retire one insns per cycle. Likewise, irdepth is not implemented. + +This emulation is compatible with the riscv-etrace-lib library located her= e: + +https://github.com/riscv-software-src/riscv-etrace-lib.git + +And some of the code being used to generated the packets were borrowed from +this library. At this point there are no plans to make riscv-etrace-lib a +dependency for this emulation. + +Encoding parameters +------------------- + +Several assumptions and simplifications were made in the code, in particul= ar +with the so called packet and itrace parameters used to write the mesasage= s. +The present emulation does not allow changing these parameters, i.e. there= 's +no way of changing the iaddress_width_p value. In case there's enough dem= and +and use cases we'll consider creating encoding properties to make them +configurable. + +Here is a list of the parameters being used in the encoding process: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Param name Hardcoded value +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +.packet.srcid_bytes_p 0 +.packet.tstamp_bytes_p 0 +.packet.type_width_p 0 +.itrace.arch_p 0 +.itrace.blocks_p 0 +.itrace.bpred_size_p 5 +.itrace.cache_size_p 0 +.itrace.call_counter_size_p 1 +.itrace.ctype_width_p 0 +.itrace.context_width_p 0 +.itrace.time_width_p 0 +.itrace.ecause_width_p 6 +.itrace.f0s_width_p 1 +.itrace.filter_context_p 0 +.itrace.filter_time_p 0 +.itrace.filter_excint_p 0 +.itrace.filter_privilege_p 0 +.itrace.filter_tval_p 0 +.itrace.iaddress_lsb_p 0 +.itrace.iaddress_width_p 64 +.itrace.iretire_width_p 0 +.itrace.ilastsize_width_p 1 +.itrace.itype_width_p 0 +.itrace.nocontext_p 1 +.itrace.notime_p 1 +.itrace.privilege_width_p 3 +.itrace.retires_p 1 +.itrace.return_stack_size_p 1 +.itrace.sijump_p 0 +.itrace.impdef_width_p 0 +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + +.. _etrace spec: https://github.com/riscv-non-isa/riscv-trace-spec/release= s/download/v2.0-20250616/riscv-trace-spec-asciidoc.pdf +.. _trace control spec: https://github.com/riscv-non-isa/tg-nexus-trace/re= leases/download/1.0_Ratified/RISC-V-Trace-Control-Interface.pdf --=20 2.43.0