hw/riscv: describe only the PLIC contexts that exist

[PATCH v2 0/4] hw/riscv: describe only the PLIC contexts that exist

Ralf Ramsauer posted 4 patches 1 day, 7 hours ago

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hw/riscv/fdt-common.c         | 20 ++++++++++++++++++++
hw/riscv/sifive_u.c           | 17 ++++++-----------
hw/riscv/virt.c               | 26 ++++++++------------------
include/hw/riscv/fdt-common.h |  3 +++
target/riscv/cpu.c            | 14 ++++++++++++++
target/riscv/cpu.h            |  1 +
6 files changed, 52 insertions(+), 29 deletions(-)

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[PATCH v2 0/4] hw/riscv: describe only the PLIC contexts that exist

Posted by Ralf Ramsauer 1 day, 7 hours ago

A PLIC context is addressed by its position in the 'interrupts-extended'
property, so the device tree and the device have to agree on which harts
contribute a context and in which order.  On the virt machine they do
not: the device is built from riscv_plic_hart_config_string(), which
gives a hart a supervisor context only if it has supervisor mode, while
the device tree lists a machine and a supervisor context for every hart,
unconditionally.  Boot with

    -cpu rv64,h=false,s=false,u=false -smp 4

and the PLIC implements four contexts while the device tree advertises
eight.  A guest that takes its context number from the property then gets
it wrong for every hart but the first.  This is what an M-mode kernel on
virt runs into.  sifive_u hardcodes the fu540 topology instead and has
the same latent problem, reachable with -cpu since the board restricts
neither the CPU type nor its extensions.

1 to 3 are the fix, 4 is cleanup and can be dropped, the rest does not
depend on it.

Tested by comparing the PLIC's 'interrupts-extended' against the
hart-config string of the PLIC device over 14 configurations of both
boards: 7 disagree before the series, all agree after, and the device
tree is unchanged wherever the default CPU is used.  The KVM paths could
not be exercised, for lack of hardware.

v1: https://lore.kernel.org/qemu-devel/20260927231838.236616-1-ralf@vmexit.de/

Ralf Ramsauer (4):
  target/riscv: add riscv_cpu_has_supervisor_mode()
  hw/riscv/virt: only describe PLIC contexts that exist
  hw/riscv/sifive_u: derive PLIC contexts from the harts
  hw/riscv: share the PLIC interrupt cells between boards

 hw/riscv/fdt-common.c         | 20 ++++++++++++++++++++
 hw/riscv/sifive_u.c           | 17 ++++++-----------
 hw/riscv/virt.c               | 26 ++++++++------------------
 include/hw/riscv/fdt-common.h |  3 +++
 target/riscv/cpu.c            | 14 ++++++++++++++
 target/riscv/cpu.h            |  1 +
 6 files changed, 52 insertions(+), 29 deletions(-)


base-commit: 81ce3a87737aa50716c42db8886082d12783e0a1
-- 
2.54.0