From nobody Fri Oct 23 20:51:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=vmexit.de ARC-Seal: i=1; a=rsa-sha256; t=1792581019; cv=none; d=zohomail.com; s=zohoarc; b=ZA8MjSKHY/NNWy5QAYTtmJuMR2raIofhNc66znI4O8ohpx6qI9gtnHJ/Ot+Ysaaq9Hom3CO4tBK7Mw08Wu1BRbN8Unqg8lLgf54UgKENUT8weT929GpntK22JFGE3inzoe9+MjDZN/tuahKP4Jj4SRVvdUD7iTbJd6ZLJaBPj8Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792581019; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bR2ZhImHfOF56oOFdy6N0wfpJwiu43eCacXEXee9zp4=; b=IdbGc4lVfh7STz3Sy4W9Vi/6017dZUda5Sc5bw0fw5UhZgQe27B05TlkXlGWwB0rOKUmwxALQTVthDvJhd6MxXOE1Lop2m+m2NANeesKigHg3EWQPCbMVIqxf34J0v4xwHmQPrB5+wZCyCMF8o7VJtCS7R/EMB4hllDzRjcbI9Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179258101951253.59380794464482; Wed, 21 Oct 2026 04:10:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJUBn-000751-Qu; Wed, 21 Oct 2026 07:08:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJUBh-00073i-AW; Wed, 21 Oct 2026 07:08:54 -0400 Received: from vmexit.de ([159.195.53.62] helo=gizmo.vmexit.de) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJUBe-0007cR-4G; Wed, 21 Oct 2026 07:08:53 -0400 From: Ralf Ramsauer DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vmexit.de; s=mail; t=1792580925; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bR2ZhImHfOF56oOFdy6N0wfpJwiu43eCacXEXee9zp4=; b=OLpa/aNp5RqRLdlhm6uctuoZzArD1N7zW/ElwBXh+PILNHfxbbuFRcfYdNL8PglhqJAGHc yYhIrYltcU2shsJXYUp9zMoENteCvGWj7oLiYAJ7kSeCqhIdo9i5KCZpXm4gDQF0kiYazQ KIbgsJqRI/Py30gIPSUtfhlcfkdpG3I= To: qemu-devel@nongnu.org, Daniel Henrique Barboza Cc: Ralf Ramsauer , Ralf Ramsauer , qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , Chao Liu , Bin Meng , Lukas Landgraf Subject: [PATCH v2 1/4] target/riscv: add riscv_cpu_has_supervisor_mode() Date: Wed, 21 Oct 2026 13:08:34 +0200 Message-ID: <20261021110838.3097959-2-ralf@vmexit.de> In-Reply-To: <20261021110838.3097959-1-ralf@vmexit.de> References: <20261021110838.3097959-1-ralf@vmexit.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=159.195.53.62; envelope-from=ralf@vmexit.de; helo=gizmo.vmexit.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vmexit.de) X-ZM-MESSAGEID: 1792581021982158500 Content-Type: text/plain; charset="utf-8" From: Ralf Ramsauer Whether a hart has supervisor mode is decided in two places: KVM harts always have it, and for TCG it follows from RVS in the ISA string. riscv_plic_hart_config_string() already spells out both cases. Board code needs the same answer to describe the interrupt controller, but it should not have to reach into CPURISCVState for it. Add a helper next to riscv_cpu_is_vendor() so the next patches can ask the CPU instead of inspecting its internals. Suggested-by: Daniel Henrique Barboza Signed-off-by: Ralf Ramsauer Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 14 ++++++++++++++ target/riscv/cpu.h | 1 + 2 files changed, 15 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da4c1a090b..19b6553e04 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -334,6 +334,20 @@ bool riscv_cpu_is_vendor(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) !=3D NULL; } =20 +bool riscv_cpu_has_supervisor_mode(RISCVCPU *cpu) +{ +#ifndef CONFIG_USER_ONLY + /* KVM always provides supervisor mode, regardless of the ISA string */ + if (kvm_enabled()) { + return true; + } + + return riscv_has_ext(&cpu->env, RVS); +#else + return false; +#endif +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8c8ffe94cd..535e56345f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -964,6 +964,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext= _offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); bool riscv_cpu_is_vendor(Object *cpu_obj); +bool riscv_cpu_has_supervisor_mode(RISCVCPU *cpu); =20 typedef struct isa_ext_data { const char *name; --=20 2.54.0 From nobody Fri Oct 23 20:51:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=vmexit.de ARC-Seal: i=1; a=rsa-sha256; t=1792581020; cv=none; d=zohomail.com; s=zohoarc; b=Fk7i2Rzt7JUnjFo9Erq54D8ky2iXqabglp5ZcJYDRixs1GW8NjY1bPK/80jSJiaa330QEDtRYjK59Sbf78OwTwc+GOuG9I5DcWEyNgynash+NwZ9BaAs/gOyy2krCWrehslLeY6/ROjl5ZRrqxw8yjU5veGijc+ryr8/+q08rx0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792581020; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 21 Oct 2026 07:08:52 -0400 Received: from vmexit.de ([2a0a:4cc0:c1:d4ba::2] helo=gizmo.vmexit.de) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJUBe-0007cZ-4h; Wed, 21 Oct 2026 07:08:51 -0400 From: Ralf Ramsauer DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vmexit.de; s=mail; t=1792580925; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wPeNl4UCxUj5StMAx3q5p/uDeM72iAQcAzJ3eFplrOg=; b=XgRvX+B7hIStQ6xUiFaTLV0TQEXi9QwAhmW1LF8ElpEZnKV8ITC8VXVDDAM2Rmd0PaLcTb MKshc8PcziPX9sWW89eiQCJbzzG/+EBHUVZ32nfBa0b8cudNkypchkoqLTpee/lw5AMUzQ HvBo1N6aWIcqrUH825bjhixQl+k/Jwc= To: qemu-devel@nongnu.org, Daniel Henrique Barboza Cc: Ralf Ramsauer , Ralf Ramsauer , qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , Chao Liu , Bin Meng , Lukas Landgraf Subject: [PATCH v2 2/4] hw/riscv/virt: only describe PLIC contexts that exist Date: Wed, 21 Oct 2026 13:08:35 +0200 Message-ID: <20261021110838.3097959-3-ralf@vmexit.de> In-Reply-To: <20261021110838.3097959-1-ralf@vmexit.de> References: <20261021110838.3097959-1-ralf@vmexit.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a0a:4cc0:c1:d4ba::2; envelope-from=ralf@vmexit.de; helo=gizmo.vmexit.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vmexit.de) X-ZM-MESSAGEID: 1792581021990158500 Content-Type: text/plain; charset="utf-8" From: Ralf Ramsauer The PLIC device is created from the topology string built by riscv_plic_hart_config_string(), which gives a hart a supervisor context only if that hart actually has supervisor mode. The device tree, in contrast, lists a machine and a supervisor context for every hart, unconditionally. The two have disagreed since commit 7d10ff8a4d ("hw/riscv: virt: Use the PLIC config helper function") taught the device about harts without S-mode and left the device tree behind. Boot with -cpu rv64,s=3Dfalse,u=3Dfalse -smp 4 and the PLIC implements four contexts while the device tree advertises eight. Contexts are numbered by their position in 'interrupts-extended', so a guest that takes its context number from the property gets it wrong for every hart but the first: hart 1 drives the context of hart 2, and the upper harts address contexts the PLIC never created. This is what an M-mode kernel on the virt machine runs into. Emit the supervisor entry only for the harts that have supervisor mode. The KVM case then becomes the same rule, not a separate one: its harts have no M-mode and always have supervisor mode, so the common loop describes the single supervisor context per hart that it used to spell out on its own. Fixes: 7d10ff8a4d ("hw/riscv: virt: Use the PLIC config helper function") Signed-off-by: Ralf Ramsauer Reviewed-by: Daniel Henrique Barboza --- v2: - ask riscv_cpu_has_supervisor_mode() instead of reading RVS out of the hart's CPURISCVState (Daniel) - fold the KVM branch into the common loop, it describes the same rule - drop the claim about sifive_u from the commit message, patch 3 fixes that board rather than leaving it as the good example hw/riscv/virt.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d4b501802f..a2851b506d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -156,23 +156,19 @@ static void create_fdt_socket_plic(RISCVVirtState *s, =20 plic_name =3D g_strdup_printf("/soc/interrupt-controller@%lx", plic_ad= dr); =20 - if (kvm_enabled()) { - cells_length =3D s->soc[socket].num_harts * 2; - plic_cells =3D g_new0(uint32_t, cells_length); - - for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { - plic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - plic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_EXT); + plic_cells =3D g_new0(uint32_t, + s->soc[socket].num_harts * (kvm_enabled() ? 2 : 4)= ); + cells_length =3D 0; + + for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { + if (!kvm_enabled()) { + plic_cells[cells_length++] =3D cpu_to_be32(intc_phandles[cpu]); + plic_cells[cells_length++] =3D cpu_to_be32(IRQ_M_EXT); } - } else { - cells_length =3D s->soc[socket].num_harts * 4; - plic_cells =3D g_new0(uint32_t, cells_length); - - for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { - plic_cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - plic_cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_M_EXT); - plic_cells[cpu * 4 + 2] =3D cpu_to_be32(intc_phandles[cpu]); - plic_cells[cpu * 4 + 3] =3D cpu_to_be32(IRQ_S_EXT); + + if (riscv_cpu_has_supervisor_mode(&s->soc[socket].harts[cpu])) { + plic_cells[cells_length++] =3D cpu_to_be32(intc_phandles[cpu]); + plic_cells[cells_length++] =3D cpu_to_be32(IRQ_S_EXT); } } =20 --=20 2.54.0 From nobody Fri Oct 23 20:51:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=vmexit.de ARC-Seal: i=1; a=rsa-sha256; t=1792581019; cv=none; d=zohomail.com; s=zohoarc; b=oGuUOFdSRqiGh1q8Y+zfQQj0iHwpESo9XH0SfUcZgSAgIqT5TixX288fMiOXbxIm4OqeyIcqARro6ezae2etLwf+CM19mwT60rWD4p6QhMbr/D/yK19leuDt7+/DGCFjny+QToo4DyDCy7P2T/KIarfmyXW45Nq1L2SBYvg6mms= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792581019; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LtnTDPEG4tfxXS2qkhC/MNKyFxWJkXsW4ewYaMKPGhI=; b=V5fTBU30+nYBEwpL0Y1HHjCYS7IeuUW968wH4z7IWIIrGIIQJttJDc/prqmlQGMxFLUDbR6aq6TKGlHobPg4DAFsBp7xThKks8C4V/fsrZ/32Ji5e12Bva080k88ZGv04e+WvbznVoB2yOF14F03eekqDw7OC3HOuDeZbJAFzjw= ARC-Authentication-Results: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=vmexit.de; s=mail; t=1792580926; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LtnTDPEG4tfxXS2qkhC/MNKyFxWJkXsW4ewYaMKPGhI=; b=FW3DNRZAn00r9nwXWA53yPY5HGvTcncP3ngyVt4IJyI/6fhf7CQrA3/i/KA8n2xdJTkHy/ 3uBaeVT7OJAtVLU7lIfM76FlpnJ4Z+K9USM1vKy3Nhe+Dlg9lPGLBs4NJ2wOSqh6PtyCfr 2o1btbiu3LlBydJvKK3F8Kiekbp8cJM= To: qemu-devel@nongnu.org, Daniel Henrique Barboza Cc: Ralf Ramsauer , Ralf Ramsauer , qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , Chao Liu , Bin Meng , Lukas Landgraf Subject: [PATCH v2 3/4] hw/riscv/sifive_u: derive PLIC contexts from the harts Date: Wed, 21 Oct 2026 13:08:36 +0200 Message-ID: <20261021110838.3097959-4-ralf@vmexit.de> In-Reply-To: <20261021110838.3097959-1-ralf@vmexit.de> References: <20261021110838.3097959-1-ralf@vmexit.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2a0a:4cc0:c1:d4ba::2; envelope-from=ralf@vmexit.de; helo=gizmo.vmexit.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vmexit.de) X-ZM-MESSAGEID: 1792581021985158500 Content-Type: text/plain; charset="utf-8" From: Ralf Ramsauer The PLIC device is created from riscv_plic_hart_config_string(), which gives a hart a supervisor context only if that hart has supervisor mode. The device tree instead hardcodes the fu540 topology: no supervisor context for the management hart, one for every other hart. Both agree as long as the application harts keep the default CPU type. The board sets no valid_cpu_types, though, and passes machine->cpu_type on to the U cluster, so -cpu rv64,s=3Dfalse,u=3Dfalse builds a PLIC without any supervisor context while the device tree still advertises one per application hart. Contexts are numbered by their position in 'interrupts-extended', so from the second hart on the numbering drifts apart, as it does on the virt machine. Ask the harts instead of assuming, like create_fdt_socket_plic() does. No change for the default CPU type: the E51 management hart has no RVS, the U54 application harts have. Signed-off-by: Ralf Ramsauer Reviewed-by: Daniel Henrique Barboza --- hw/riscv/sifive_u.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b7d5e7b4da..8f50c67a14 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -99,6 +99,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry= *memmap, MachineState *ms =3D MACHINE(s); void *fdt; int cpu; + RISCVCPU *hart; uint32_t *cells, cells_length; char *nodename; uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle =3D 1; @@ -195,18 +196,18 @@ static void create_fdt(SiFiveUState *s, const MemMapE= ntry *memmap, g_free(nodename); =20 plic_phandle =3D phandle++; - cells_length =3D ms->smp.cpus * 4 - 2; - cells =3D g_new0(uint32_t, cells_length); + cells =3D g_new0(uint32_t, ms->smp.cpus * 4 - 2); + cells_length =3D 0; for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { /* cpu 0 is the management hart that does not have S-mode */ - if (cpu =3D=3D 0) { - cells[0] =3D cpu_to_be32(intc_phandles[cpu]); - cells[1] =3D cpu_to_be32(IRQ_M_EXT); - } else { - cells[cpu * 4 - 2] =3D cpu_to_be32(intc_phandles[cpu]); - cells[cpu * 4 - 1] =3D cpu_to_be32(IRQ_M_EXT); - cells[cpu * 4 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - cells[cpu * 4 + 1] =3D cpu_to_be32(IRQ_S_EXT); + hart =3D cpu ? &s->soc.u_cpus.harts[cpu - 1] : &s->soc.e_cpus.hart= s[0]; + + cells[cells_length++] =3D cpu_to_be32(intc_phandles[cpu]); + cells[cells_length++] =3D cpu_to_be32(IRQ_M_EXT); + + if (riscv_cpu_has_supervisor_mode(hart)) { + cells[cells_length++] =3D cpu_to_be32(intc_phandles[cpu]); + cells[cells_length++] =3D cpu_to_be32(IRQ_S_EXT); } } =20 --=20 2.54.0 From nobody Fri Oct 23 20:51:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=vmexit.de ARC-Seal: i=1; a=rsa-sha256; t=1792581037; cv=none; d=zohomail.com; s=zohoarc; b=DlvWW5Xy8QS42nrTX3FdECh4cudTcBBIe+Mc5l3QxPx3SGG6QJyU2cwv7euTcYH4e+BtTwRogUhY76Qds1+KYPmRwVWOps6r7zshLYhUvzXSvLrHAFKwzF/jzo6M7nC+WrIdEQynVakvi7atpVWsCxAWio/AqykoxWic6nFZQaM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1792581037; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=K1l4nYcXAeWLbE73aMbHM9TuvfOoPk3yIINihG66vy4=; b=cwlKUvDOp7k0j5xyvx7jmE74fH3rJAHv6O00XJWvV+CKiiBZhhtH0HaQc3drZCMpZCfFwLQWHDFAX4iGAP1gBy+b+xRsaWU2lBiWudroZaicKqCjM0CU+kUEvDrsS7ObSd++QZIoWVsvNPBeMmxu/FSmHzJsDPv77CgDh3vSBx8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1792581036674751.7247976285381; Wed, 21 Oct 2026 04:10:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1xJUBn-000750-Rl; Wed, 21 Oct 2026 07:09:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJUBh-00073r-Fc; Wed, 21 Oct 2026 07:08:54 -0400 Received: from vmexit.de ([159.195.53.62] helo=gizmo.vmexit.de) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1xJUBe-0007cf-5F; Wed, 21 Oct 2026 07:08:53 -0400 From: Ralf Ramsauer DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vmexit.de; s=mail; t=1792580926; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=K1l4nYcXAeWLbE73aMbHM9TuvfOoPk3yIINihG66vy4=; b=RpGZRjlJ3evskJ71gXNjqgj5CAXi5dehLbm4tW7AxjV3Vu+oTHI+yw7cAFy2PhLERwRAXv i8F5RLEA77hjkH2/20DDEl5Ns8QQgqL5o232deKDtPSJ8X22J/v7a6uvWMcVw1JL7k8/4w 0bfqXfsaXDaQvnHQATpOqXsGnYWRXVE= To: qemu-devel@nongnu.org, Daniel Henrique Barboza Cc: Ralf Ramsauer , Ralf Ramsauer , qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei , Chao Liu , Bin Meng , Lukas Landgraf Subject: [PATCH v2 4/4] hw/riscv: share the PLIC interrupt cells between boards Date: Wed, 21 Oct 2026 13:08:37 +0200 Message-ID: <20261021110838.3097959-5-ralf@vmexit.de> In-Reply-To: <20261021110838.3097959-1-ralf@vmexit.de> References: <20261021110838.3097959-1-ralf@vmexit.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=159.195.53.62; envelope-from=ralf@vmexit.de; helo=gizmo.vmexit.de X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vmexit.de) X-ZM-MESSAGEID: 1792581038594158500 Content-Type: text/plain; charset="utf-8" From: Ralf Ramsauer virt and sifive_u now describe a hart's PLIC contexts with the same rule: a machine context unless the hart runs under KVM, where there is no M-mode, and a supervisor context if the hart has supervisor mode. Writing that rule down twice is what let the virt device tree drift away from riscv_plic_hart_config_string(). This makes the sifive_u device tree ask whether KVM is in use, which it did not do before. Its PLIC device already does, so the two now agree. Signed-off-by: Ralf Ramsauer --- Cleanup, not a fix. Can be dropped, the rest does not depend on it. hw/riscv/fdt-common.c | 20 ++++++++++++++++++++ hw/riscv/sifive_u.c | 10 ++-------- hw/riscv/virt.c | 12 +++--------- include/hw/riscv/fdt-common.h | 3 +++ 4 files changed, 28 insertions(+), 17 deletions(-) diff --git a/hw/riscv/fdt-common.c b/hw/riscv/fdt-common.c index ce2dcb43b4..70f96734b4 100644 --- a/hw/riscv/fdt-common.c +++ b/hw/riscv/fdt-common.c @@ -10,6 +10,7 @@ =20 #include "qemu/error-report.h" #include "system/device_tree.h" +#include "system/kvm.h" #include "hw/core/boards.h" #include "hw/core/sysbus-fdt.h" #include "hw/riscv/fdt-common.h" @@ -212,6 +213,25 @@ riscv_create_fdt_socket_cpu_sifive(void *fdt, char *cl= ust_name, phandle, intc_phandles, false, false); } =20 +uint32_t riscv_plic_hart_fdt_cells(uint32_t *cells, RISCVCPU *hart, + uint32_t intc_phandle) +{ + uint32_t len =3D 0; + + /* harts running under KVM have no M-mode */ + if (!kvm_enabled()) { + cells[len++] =3D cpu_to_be32(intc_phandle); + cells[len++] =3D cpu_to_be32(IRQ_M_EXT); + } + + if (riscv_cpu_has_supervisor_mode(hart)) { + cells[len++] =3D cpu_to_be32(intc_phandle); + cells[len++] =3D cpu_to_be32(IRQ_S_EXT); + } + + return len; +} + void riscv_create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, uint32_t plic_phandle, uint32_t int_cells, uint32_t addr_cells, uint32_t *plic_cells, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 8f50c67a14..456b6da3e6 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -201,14 +201,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEn= try *memmap, for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { /* cpu 0 is the management hart that does not have S-mode */ hart =3D cpu ? &s->soc.u_cpus.harts[cpu - 1] : &s->soc.e_cpus.hart= s[0]; - - cells[cells_length++] =3D cpu_to_be32(intc_phandles[cpu]); - cells[cells_length++] =3D cpu_to_be32(IRQ_M_EXT); - - if (riscv_cpu_has_supervisor_mode(hart)) { - cells[cells_length++] =3D cpu_to_be32(intc_phandles[cpu]); - cells[cells_length++] =3D cpu_to_be32(IRQ_S_EXT); - } + cells_length +=3D riscv_plic_hart_fdt_cells(&cells[cells_length], = hart, + intc_phandles[cpu]); } =20 riscv_create_fdt_plic(fdt, memmap[SIFIVE_U_DEV_PLIC].base, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a2851b506d..a325891dca 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -161,15 +161,9 @@ static void create_fdt_socket_plic(RISCVVirtState *s, cells_length =3D 0; =20 for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { - if (!kvm_enabled()) { - plic_cells[cells_length++] =3D cpu_to_be32(intc_phandles[cpu]); - plic_cells[cells_length++] =3D cpu_to_be32(IRQ_M_EXT); - } - - if (riscv_cpu_has_supervisor_mode(&s->soc[socket].harts[cpu])) { - plic_cells[cells_length++] =3D cpu_to_be32(intc_phandles[cpu]); - plic_cells[cells_length++] =3D cpu_to_be32(IRQ_S_EXT); - } + cells_length +=3D riscv_plic_hart_fdt_cells(&plic_cells[cells_leng= th], + &s->soc[socket].harts[cp= u], + intc_phandles[cpu]); } =20 plic_phandles[socket] =3D (*phandle)++; diff --git a/include/hw/riscv/fdt-common.h b/include/hw/riscv/fdt-common.h index eb9db8278d..14116a95cf 100644 --- a/include/hw/riscv/fdt-common.h +++ b/include/hw/riscv/fdt-common.h @@ -93,6 +93,9 @@ void riscv_create_fdt_socket_cpu_sifive(void *fdt, char *= clust_name, int socket_hartid_base, uint32_t *phandle, uint32_t *intc_phandles); +/* Describe one hart's PLIC contexts, returns the number of cells written = */ +uint32_t riscv_plic_hart_fdt_cells(uint32_t *cells, RISCVCPU *hart, + uint32_t intc_phandle); void riscv_create_fdt_plic(void *fdt, hwaddr addr, uint64_t size, uint32_t plic_phandle, uint32_t int_cells, uint32_t addr_cells, uint32_t *plic_cells, --=20 2.54.0