[v2] Hexagon: performance improvements - tlb, l2vic

[PATCH v2 0/3] Hexagon: performance improvements - tlb, l2vic

Brian Cain posted 3 patches 1 day, 15 hours ago

Diff against v1
Download series mbox

include/hw/hexagon/hexagon_tlb.h |  2 ++
target/hexagon/cpu.h             |  8 ++++++++
target/hexagon/gen_tcg_sys.h     |  3 +++
target/hexagon/helper.h          |  1 +
target/hexagon/hex_mmu.h         |  3 ++-
hw/hexagon/hexagon_tlb.c         | 18 ++++++++++++++++++
hw/intc/hex-l2vic.c              | 17 ++++++++++++++---
target/hexagon/cpu_helper.c      | 17 +++--------------
target/hexagon/hex_mmu.c         | 28 +++++++++++++++++++++++-----
target/hexagon/op_helper.c       |  6 ++++++
10 files changed, 80 insertions(+), 23 deletions(-)

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[PATCH v2 0/3] Hexagon: performance improvements - tlb, l2vic

Posted by Brian Cain 1 day, 15 hours ago

In this series we have significant performance improvements for use cases
like booting linux.  The gains come from avoiding redundant TLB flushes and
optimizing the critical path of the interrupt controller scan loop.

In v2:
- clarified the comment in l2vic_update_all()

v1: https://lore.kernel.org/qemu-devel/20261020151720.728888-1-brian.cain@oss.qualcomm.com/

Brian Cain (3):
  target/hexagon: flush the softtlb once per tlbinvasid
  target/hexagon: only flush the softtlb when SSR.ASID changes
  hw/intc/hex-l2vic: find the next pending irq a word at a time

 include/hw/hexagon/hexagon_tlb.h |  2 ++
 target/hexagon/cpu.h             |  8 ++++++++
 target/hexagon/gen_tcg_sys.h     |  3 +++
 target/hexagon/helper.h          |  1 +
 target/hexagon/hex_mmu.h         |  3 ++-
 hw/hexagon/hexagon_tlb.c         | 18 ++++++++++++++++++
 hw/intc/hex-l2vic.c              | 17 ++++++++++++++---
 target/hexagon/cpu_helper.c      | 17 +++--------------
 target/hexagon/hex_mmu.c         | 28 +++++++++++++++++++++++-----
 target/hexagon/op_helper.c       |  6 ++++++
 10 files changed, 80 insertions(+), 23 deletions(-)

-- 
2.34.1

Re: [PATCH v2 0/3] Hexagon: performance improvements - tlb, l2vic

Posted by Brian Cain 1 day, 5 hours ago

On 10/20/2026 10:15 PM, Brian Cain wrote:
> In this series we have significant performance improvements for use cases
> like booting linux.  The gains come from avoiding redundant TLB flushes and
> optimizing the critical path of the interrupt controller scan loop.
>
> In v2:
> - clarified the comment in l2vic_update_all()

Whoops - forgot to update the trailers before sending v2.  I'll update 
these for v3 or the pull req.


The only one without a R-b is #3.


>
> v1: https://lore.kernel.org/qemu-devel/20261020151720.728888-1-brian.cain@oss.qualcomm.com/
>
> Brian Cain (3):
>    target/hexagon: flush the softtlb once per tlbinvasid
>    target/hexagon: only flush the softtlb when SSR.ASID changes
>    hw/intc/hex-l2vic: find the next pending irq a word at a time
>
>   include/hw/hexagon/hexagon_tlb.h |  2 ++
>   target/hexagon/cpu.h             |  8 ++++++++
>   target/hexagon/gen_tcg_sys.h     |  3 +++
>   target/hexagon/helper.h          |  1 +
>   target/hexagon/hex_mmu.h         |  3 ++-
>   hw/hexagon/hexagon_tlb.c         | 18 ++++++++++++++++++
>   hw/intc/hex-l2vic.c              | 17 ++++++++++++++---
>   target/hexagon/cpu_helper.c      | 17 +++--------------
>   target/hexagon/hex_mmu.c         | 28 +++++++++++++++++++++++-----
>   target/hexagon/op_helper.c       |  6 ++++++
>   10 files changed, 80 insertions(+), 23 deletions(-)
>