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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792552673162158500 tlbinvasid cleared each matching JTLB entry via fTLBW(), and these would hit hex_tlbw()'s flush. tlbinvasid could trigger several full flushes. Since the softtlb isn't ASID-tagged, clear all matching valid bits first and flush once. The hardware threads share one JTLB but have their own softtlb, so the flush has to be broadcast to every CPU rather than just the one running the invalidation. Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon_tlb.h | 2 ++ target/hexagon/cpu.h | 8 ++++++++ target/hexagon/gen_tcg_sys.h | 3 +++ target/hexagon/helper.h | 1 + target/hexagon/hex_mmu.h | 1 + hw/hexagon/hexagon_tlb.c | 18 ++++++++++++++++++ target/hexagon/hex_mmu.c | 21 +++++++++++++++++++-- target/hexagon/op_helper.c | 6 ++++++ 8 files changed, 58 insertions(+), 2 deletions(-) diff --git a/include/hw/hexagon/hexagon_tlb.h b/include/hw/hexagon/hexagon_= tlb.h index 56aa0b2beed..355ba3888c0 100644 --- a/include/hw/hexagon/hexagon_tlb.h +++ b/include/hw/hexagon/hexagon_tlb.h @@ -30,6 +30,8 @@ uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t = index); uint64_t hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t value); =20 +uint32_t hexagon_tlb_invalidate_asid(HexagonTLBState *tlb, uint32_t asid); + bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid, uint32_t VA, MMUAccessType access_type, hwaddr *PA, int *prot, uint64_t *size, diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c1a944920e8..a0162faa9dc 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -76,6 +76,14 @@ typedef struct HexagonHVXContextState HexagonHVXContextS= tate; #define MMU_GUEST_IDX 1 #define MMU_KERNEL_IDX 2 =20 +/* + * TLB entry match is by ASID and global bit, neither of which is encoded = in + * mmu_idx, so a JTLB change has to be flushed out of every mmu_idx. + */ +#define MMU_IDX_ALL ((1 << MMU_USER_IDX) | \ + (1 << MMU_GUEST_IDX) | \ + (1 << MMU_KERNEL_IDX)) + typedef enum { HEX_LOCK_UNLOCKED =3D 0, HEX_LOCK_WAITING =3D 1, diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h index 3760b671adf..3a850973800 100644 --- a/target/hexagon/gen_tcg_sys.h +++ b/target/hexagon/gen_tcg_sys.h @@ -20,6 +20,9 @@ #define fGEN_TCG_Y4_siad(SHORTCODE) \ gen_helper_siad(tcg_env, RsV) =20 +#define fGEN_TCG_Y5_tlbasidi(SHORTCODE) \ + gen_helper_tlbinvasid(tcg_env, RsV) + #define fGEN_TCG_Y2_iassignw(SHORTCODE) \ gen_helper_iassignw(tcg_env, RsV) =20 diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 28591417040..d354d49f72e 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -143,4 +143,5 @@ DEF_HELPER_2(resume, void, env, i32) DEF_HELPER_1(resched, void, env) DEF_HELPER_3(modify_ssr, void, env, i32, i32) DEF_HELPER_1(pending_interrupt, void, env) +DEF_HELPER_2(tlbinvasid, void, env, i32) #endif diff --git a/target/hexagon/hex_mmu.h b/target/hexagon/hex_mmu.h index 2cfcd10949a..0c49404448c 100644 --- a/target/hexagon/hex_mmu.h +++ b/target/hexagon/hex_mmu.h @@ -13,6 +13,7 @@ #include "monitor/hmp.h" =20 extern void hex_tlbw(CPUHexagonState *env, uint32_t index, uint64_t value); +extern void hex_tlb_invalidate_asid(CPUHexagonState *env, uint32_t asid); extern uint32_t hex_tlb_lookup(CPUHexagonState *env, uint32_t ssr, uint32_= t VA); extern void hex_mmu_on(CPUHexagonState *env); extern void hex_mmu_off(CPUHexagonState *env); diff --git a/hw/hexagon/hexagon_tlb.c b/hw/hexagon/hexagon_tlb.c index 28601b78a6f..3e72026d62a 100644 --- a/hw/hexagon/hexagon_tlb.c +++ b/hw/hexagon/hexagon_tlb.c @@ -321,6 +321,24 @@ uint64_t hexagon_tlb_write(HexagonTLBState *tlb, uint3= 2_t index, return old; } =20 +uint32_t hexagon_tlb_invalidate_asid(HexagonTLBState *tlb, uint32_t asid) +{ + uint32_t invalidated =3D 0; + + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + uint64_t entry =3D tlb->entries[i]; + + if (!GET_PTE_V(entry) || GET_PTE_G(entry) || + GET_PTE_ASID(entry) !=3D asid) { + continue; + } + tlb->entries[i] =3D deposit64(entry, 63, 1, 0); + invalidated++; + } + + return invalidated; +} + bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid, uint32_t VA, MMUAccessType access_type, hwaddr *PA, int *prot, uint64_t *size, diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index f93dd3d82d4..2e0e4ab705b 100644 --- a/target/hexagon/hex_mmu.c +++ b/target/hexagon/hex_mmu.c @@ -29,6 +29,11 @@ static inline void hex_log_tlbw(uint32_t index, uint64_t= entry) index, entry); } =20 +static void hex_tlb_flush_all(CPUState *cs) +{ + tlb_flush_by_mmuidx_all_cpus_synced(cs, MMU_IDX_ALL); +} + void hex_tlbw(CPUHexagonState *env, uint32_t index, uint64_t value) { uint32_t myidx =3D fTLB_NONPOW2WRAP(fTLB_IDXMASK(index)); @@ -36,12 +41,24 @@ void hex_tlbw(CPUHexagonState *env, uint32_t index, uin= t64_t value) uint64_t old_entry =3D hexagon_tlb_write(tlb, myidx, value); bool old_entry_valid =3D extract64(old_entry, 63, 1); if (old_entry_valid && hexagon_cpu_mmu_enabled(env)) { - CPUState *cs =3D env_cpu(env); - tlb_flush_all_cpus_synced(cs); + hex_tlb_flush_all(env_cpu(env)); } hex_log_tlbw(myidx, value); } =20 +void hex_tlb_invalidate_asid(CPUHexagonState *env, uint32_t asid) +{ + HexagonTLBState *tlb =3D env_archcpu(env)->tlb; + uint32_t invalidated =3D hexagon_tlb_invalidate_asid(tlb, asid); + + qemu_log_mask(CPU_LOG_MMU, + "tlbinvasid: asid 0x%02" PRIx32 ", %" PRIu32 " entries\n= ", + asid, invalidated); + if (invalidated && hexagon_cpu_mmu_enabled(env)) { + hex_tlb_flush_all(env_cpu(env)); + } +} + void hex_mmu_on(CPUHexagonState *env) { CPUState *cs =3D env_cpu(env); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 9850dc07289..a7a63de57cf 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1663,6 +1663,12 @@ void HELPER(siad)(CPUHexagonState *env, uint32_t mas= k) hex_interrupt_update(env); } =20 +void HELPER(tlbinvasid)(CPUHexagonState *env, uint32_t RsV) +{ + BQL_LOCK_GUARD(); + hex_tlb_invalidate_asid(env, extract32(RsV, 20, 7)); +} + void HELPER(swi)(CPUHexagonState *env, uint32_t mask) { BQL_LOCK_GUARD(); --=20 2.34.1 From nobody Fri Oct 23 21:07:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1792552959; cv=none; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792552960765158500 hexagon_modify_ssr() flushed the softtlb on any change to SSR.EX, UM, GM, or ASID, but only ASID affects translation. EX/UM/GM just pick the mode, which is already captured in mmu_idx. EX toggles on every exception entry/rte, so the flush created a feedback loop where a TLB miss wiped the softtlb and guaranteed the next accesses missed too. Rename hex_mmu_mode_change() to hex_mmu_asid_change() to match what now triggers it, and narrow it to this thread's mmu indices: the ASID lives in the thread's private SSR, so other CPUs are unaffected. Signed-off-by: Brian Cain --- target/hexagon/hex_mmu.h | 2 +- target/hexagon/cpu_helper.c | 17 +++-------------- target/hexagon/hex_mmu.c | 7 ++++--- 3 files changed, 8 insertions(+), 18 deletions(-) diff --git a/target/hexagon/hex_mmu.h b/target/hexagon/hex_mmu.h index 0c49404448c..9b6ea5b967b 100644 --- a/target/hexagon/hex_mmu.h +++ b/target/hexagon/hex_mmu.h @@ -17,7 +17,7 @@ extern void hex_tlb_invalidate_asid(CPUHexagonState *env,= uint32_t asid); extern uint32_t hex_tlb_lookup(CPUHexagonState *env, uint32_t ssr, uint32_= t VA); extern void hex_mmu_on(CPUHexagonState *env); extern void hex_mmu_off(CPUHexagonState *env); -extern void hex_mmu_mode_change(CPUHexagonState *env); +extern void hex_mmu_asid_change(CPUHexagonState *env); extern bool hex_tlb_find_match(CPUHexagonState *env, uint32_t VA, MMUAccessType access_type, hwaddr *PA, int = *prot, uint64_t *size, int32_t *excp, int mmu_idx); diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 6dc06401ad5..64d8a2cad78 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -231,27 +231,17 @@ unsigned hexagon_hvx_select_context(CPUHexagonState *= env, uint32_t ssr) =20 void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old) { - bool old_EX, old_UM, old_GM, old_IE; - bool new_EX, new_UM, new_GM, new_IE; + bool old_EX, old_IE; + bool new_EX, new_IE; uint8_t old_asid, new_asid; =20 g_assert(bql_locked()); =20 old_EX =3D GET_SSR_FIELD(SSR_EX, old); - old_UM =3D GET_SSR_FIELD(SSR_UM, old); - old_GM =3D GET_SSR_FIELD(SSR_GM, old); old_IE =3D GET_SSR_FIELD(SSR_IE, old); new_EX =3D GET_SSR_FIELD(SSR_EX, new); - new_UM =3D GET_SSR_FIELD(SSR_UM, new); - new_GM =3D GET_SSR_FIELD(SSR_GM, new); new_IE =3D GET_SSR_FIELD(SSR_IE, new); =20 - if ((old_EX !=3D new_EX) || - (old_UM !=3D new_UM) || - (old_GM !=3D new_GM)) { - hex_mmu_mode_change(env); - } - bool xa_changed =3D GET_SSR_FIELD(SSR_XA, new) !=3D GET_SSR_FIELD(SSR_= XA, old); bool xe_changed =3D GET_SSR_FIELD(SSR_XE, new) !=3D GET_SSR_FIELD(SSR_= XE, old); =20 @@ -267,8 +257,7 @@ void hexagon_modify_ssr(CPUHexagonState *env, uint32_t = new, uint32_t old) old_asid =3D GET_SSR_FIELD(SSR_ASID, old); new_asid =3D GET_SSR_FIELD(SSR_ASID, new); if (new_asid !=3D old_asid) { - CPUState *cs =3D env_cpu(env); - tlb_flush(cs); + hex_mmu_asid_change(env); } =20 /* See if the interrupts have been enabled or we have exited EX mode */ diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c index 2e0e4ab705b..9a0e29ae212 100644 --- a/target/hexagon/hex_mmu.c +++ b/target/hexagon/hex_mmu.c @@ -73,11 +73,12 @@ void hex_mmu_off(CPUHexagonState *env) tlb_flush(cs); } =20 -void hex_mmu_mode_change(CPUHexagonState *env) +void hex_mmu_asid_change(CPUHexagonState *env) { - qemu_log_mask(CPU_LOG_MMU, "Hexagon mode change!\n"); CPUState *cs =3D env_cpu(env); - tlb_flush(cs); + + qemu_log_mask(CPU_LOG_MMU, "Hexagon ASID change!\n"); + tlb_flush_by_mmuidx(cs, MMU_IDX_ALL); } =20 bool hex_tlb_find_match(CPUHexagonState *env, uint32_t VA, --=20 2.34.1 From nobody Fri Oct 23 21:07:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1792552683399158500 l2vic_update_all() called l2vic_update() for each of the 1024 irqs, and every call rescanned all of int_status for an active vid. ciad runs it on each interrupt return, so this was a hot function for an OS boot. Check once whether a vid is active, then deliver the lowest irq that is both pending and enabled by scanning int_pending & int_enable a word at a time. The delivered irq is unchanged. Signed-off-by: Brian Cain Reviewed-by: Pierrick Bouvier --- hw/intc/hex-l2vic.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/intc/hex-l2vic.c b/hw/intc/hex-l2vic.c index 736f1be3b1d..d92ff5eec21 100644 --- a/hw/intc/hex-l2vic.c +++ b/hw/intc/hex-l2vic.c @@ -290,9 +290,20 @@ static bool l2vic_update(HexL2VICState *s, int irq) =20 static void l2vic_update_all(HexL2VICState *s) { - for (int i =3D 0; i < L2VIC_INTERRUPT_MAX; i++) { - if (l2vic_update(s, i)) { - /* once vid is active, no-one else can set it until ciad */ + /* once vid is active, no-one else can set it until ciad */ + if (vid_active(s)) { + return; + } + + /* + * Quickly find lowest-numbered irq ready by scanning their statuses + * range by range instead of one by one. + */ + for (int slice =3D 0; slice < SLICE_MAX; slice++) { + uint32_t ready =3D s->int_pending[slice] & s->int_enable[slice]; + + if (ready) { + l2vic_update(s, slice * 32 + ctz32(ready)); return; } } --=20 2.34.1