The following changes since commit a97f90fcf8029af253a2ba274b9bda9acabc5b23:
Merge tag 'pull-tcg-20260924' of https://gitlab.com/rth7680/qemu into staging (2026-09-24 08:24:59 -0700)
are available in the Git repository at:
https://github.com/qualcomm/qemu tags/pull-hex-20260924
for you to fetch changes up to 443fe4436feb05b4b55ad0fa77d199da39b7f13c:
target/hexagon: rename LEN to OFFS_REG_END in VTCM macros (2026-09-24 17:22:46 -0700)
----------------------------------------------------------------
Hexagon: HVX sysemu, tests, fixes
Added HVX support for system emulation: bind SSR.XA to the associated
HVX context.
Endian bugfixes for HVX.
Add tests for improved coverage.
Improvements in the simple packet short-circuit logic - for handling
multiple reg-writes to GPRs, System, Guest, Vector, Vec-Pred registers.
----------------------------------------------------------------
Brian Cain (30):
tests/tcg/hexagon: fix undefined signed left shift in circ.c
tests/tcg/hexagon: fix undefined signed left shift in brev.c
tests/tcg/hexagon: fix undefined signed integer overflow in hvx_misc
tests/tcg/hexagon: fix undefined integer overflow in v69_hvx.c
tests/tcg/multiarch: suppress UBSan for float-to-int conversions
tests/tcg/hexagon: add FP classification, conversion, and fixup tests
tests/tcg/hexagon: add bit interleave and convergent rounding tests
tests/tcg/hexagon: add cond call, tstbit-jump, and endloop01 tests
tests/tcg/hexagon: add dczeroa cache line zero test
tests/tcg/hexagon: add HVX vwhist tests
tests/tcg/hexagon: add sfrecipa edge case tests
tests/tcg/hexagon: add dfmpyhh
tests/tcg/hexagon: add unconditional store-immediate tests
tests/tcg/hexagon: add predicate register transfer test
tests/tcg/hexagon: add rounding conv, sffma:lib, and sfinvsqrta
tests/tcg/hexagon: add scalar+HVX and masked store tests
tests/tcg/hexagon: add decbin MPS test case
tcg: split out _var forms of gvec logical, abs and min/max ops
tcg: add base arguments to the gvec 2s, dup_i32 and cmp expanders
tcg: split out _var forms of gvec saturating/mul/shift-immediate ops
target/hexagon: raise an exception for HVX with SSR:XE clear
target/hexagon: prepare for separate HVX contexts
target/hexagon: share HVX contexts among CPUs
tests/functional/hexagon: add HVX tests
target/hexagon: fix HVX big-endian byte access
target/hexagon: fix HVX scatter/gather region-length check
tests/tcg/hexagon: add vgather/vscatter region-length tests
target/hexagon: fix HVX predicate save size for histogram ops
tests/tcg/hexagon: check the two HVX predicate build paths agree
target/hexagon: rename LEN to OFFS_REG_END in VTCM macros
Taylor Simpson (10):
Hexagon (target/hexagon) Move code out of gen_start_packet
Hexagon (target/hexagon) Check for GPR multiwrite in analyze_packet
Hexagon (tests/tcg/hexagon) Add tests for multi-destination instructions
Hexagon (target/hexagon) Check for vreg multiwrite in analyze_packet
Hexagon (tests/tcg/hexagon) Add tests for vreg multiple writes
Hexagon (target/hexagon) Check for qreg multiwrite in analyze_packet
Hexagon (tests/tcg/hexagon) Add tests for qreg multiple writes
Hexagon (target/hexagon) Check for greg multiwrite in analyze_packet
Hexagon (target/hexagon) Check for sreg multiwrite in analyze_packet
Hexagon (target/hexagon) Remove old way of detecting register multiwrites
include/hw/hexagon/hexagon.h | 1 +
include/hw/hexagon/hexagon_hvx_context.h | 27 ++
include/tcg/tcg-op-gvec-common.h | 97 +++++
target/hexagon/cpu.h | 26 +-
target/hexagon/cpu_helper.h | 1 +
target/hexagon/gen_tcg_hvx.h | 608 +++++++++++++++------------
target/hexagon/genptr.h | 8 +
target/hexagon/insn.h | 4 -
target/hexagon/mmvec/macros.h | 130 +++---
target/hexagon/mmvec/mmvec.h | 18 +
target/hexagon/translate.h | 60 ++-
tests/tcg/hexagon/hex_test.h | 10 +
tests/tcg/hexagon/hvx_misc.h | 1 +
hw/hexagon/hex-subsys.c | 29 ++
hw/hexagon/hexagon_hvx_context.c | 84 ++++
target/hexagon/cpu.c | 35 +-
target/hexagon/cpu_helper.c | 82 ++++
target/hexagon/decode.c | 54 ---
target/hexagon/gdbstub.c | 16 +-
target/hexagon/genptr.c | 103 +++--
target/hexagon/machine.c | 12 +
target/hexagon/mmvec/system_ext_mmvec.c | 2 +-
target/hexagon/op_helper.c | 54 +--
target/hexagon/translate.c | 161 ++++++--
tcg/tcg-op-gvec.c | 617 ++++++++++++++++++++--------
tests/tcg/hexagon/brev.c | 2 +-
tests/tcg/hexagon/circ.c | 6 +-
tests/tcg/hexagon/fpstuff.c | 412 +++++++++++++++++++
tests/tcg/hexagon/hvx_misc.c | 129 +++++-
tests/tcg/hexagon/misc.c | 79 ++++
tests/tcg/hexagon/multiple-writes.c | 149 +++++++
tests/tcg/hexagon/scatter_gather.c | 137 +++++-
tests/tcg/hexagon/test_bitops.c | 98 +++++
tests/tcg/hexagon/test_cond_branch.c | 162 ++++++++
tests/tcg/hexagon/test_dczeroa.c | 88 ++++
tests/tcg/hexagon/test_vwhist.c | 345 ++++++++++++++++
tests/tcg/hexagon/v69_hvx.c | 3 +-
tests/tcg/multiarch/float_convd.c | 1 +
tests/tcg/multiarch/float_convs.c | 1 +
hw/hexagon/meson.build | 1 +
target/hexagon/gen_trans_funcs.py | 10 -
target/hexagon/hex_common.py | 179 ++++----
tests/functional/hexagon/test_arch_tests.py | 7 +
tests/functional/hexagon/test_systests.py | 6 +
tests/tcg/hexagon/meson.build | 6 +-
45 files changed, 3275 insertions(+), 786 deletions(-)
create mode 100644 include/hw/hexagon/hexagon_hvx_context.h
create mode 100644 hw/hexagon/hexagon_hvx_context.c
create mode 100644 tests/tcg/hexagon/test_bitops.c
create mode 100644 tests/tcg/hexagon/test_cond_branch.c
create mode 100644 tests/tcg/hexagon/test_dczeroa.c
create mode 100644 tests/tcg/hexagon/test_vwhist.c