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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301381523158500 From: Taylor Simpson Move clear_pkt_ctx and analyze_packet out of gen_start_packet Precursor to adding packet validity checks to analyze_packet Reviewed-by: Brian Cain Reviewed-by: Marco Liebel Signed-off-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/translate.c | 45 ++++++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index fd1de87405c..29e02d8cc9e 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -564,28 +564,13 @@ static void mark_implicit_writes(DisasContext *ctx) mark_implicit_pred_writes(ctx); } =20 -static void analyze_packet(DisasContext *ctx) -{ - ctx->read_after_write =3D false; - ctx->has_hvx_overlap =3D false; - for (int i =3D 0; i < ctx->pkt.num_insns; i++) { - Insn *insn =3D &ctx->pkt.insn[i]; - ctx->insn =3D insn; - if (opcode_analyze[insn->opcode]) { - opcode_analyze[insn->opcode](ctx); - } - } - - ctx->need_commit =3D need_commit(ctx); -} - -static void gen_start_packet(DisasContext *ctx) +/* Clear out the disassembly context */ +static void clear_pkt_ctx(DisasContext *ctx) { Packet *pkt =3D &ctx->pkt; target_ulong next_PC =3D ctx->base.pc_next + pkt->encod_pkt_size_in_by= tes; int i; =20 - /* Clear out the disassembly context */ ctx->next_PC =3D next_PC; ctx->reg_log_idx =3D 0; bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); @@ -618,8 +603,26 @@ static void gen_start_packet(DisasContext *ctx) for (i =3D 0; i < NUM_PREGS; i++) { ctx->new_pred_value[i] =3D NULL; } +} =20 - analyze_packet(ctx); +static void analyze_packet(DisasContext *ctx) +{ + ctx->read_after_write =3D false; + ctx->has_hvx_overlap =3D false; + for (int i =3D 0; i < ctx->pkt.num_insns; i++) { + Insn *insn =3D &ctx->pkt.insn[i]; + ctx->insn =3D insn; + if (opcode_analyze[insn->opcode]) { + opcode_analyze[insn->opcode](ctx); + } + } + + ctx->need_commit =3D need_commit(ctx); +} + +static void gen_start_packet(DisasContext *ctx) +{ + int i; =20 /* * pregs_written is used both in the analyze phase as well as the code @@ -661,7 +664,7 @@ static void gen_start_packet(DisasContext *ctx) ctx->pkt_ends_tb =3D pkt_ends_tb(&ctx->pkt); ctx->need_next_pc =3D need_next_PC(ctx); if (ctx->need_next_pc) { - tcg_gen_movi_tl(hex_next_PC, next_PC); + tcg_gen_movi_tl(hex_next_PC, ctx->next_PC); } =20 /* Preload the predicated registers into get_result_gpr(ctx, i) */ @@ -1203,6 +1206,10 @@ static void decode_and_translate_packet(CPUHexagonSt= ate *env, DisasContext *ctx) words_read =3D decode_packet(ctx, nwords, words, &ctx->pkt, false); if (words_read > 0) { ctx->pkt.pc =3D ctx->base.pc_next; + + clear_pkt_ctx(ctx); + analyze_packet(ctx); + if (ctx->pkt.pkt_has_write_conflict) { gen_exception_decode_fail(ctx, words_read, HEX_CAUSE_REG_WRITE_CONFLICT); --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301334; cv=none; d=zohomail.com; s=zohoarc; b=ZCRj8rsz1iEvBPV479pbazIm60/er71lcV5RBPnPibCKXTtdmR8T5pBSHibMuqhweNFCWr9GOqD0ZHFSYp2YPyLPcoNlLI/gNGFPNsd1G+LJbqf6PwKOVxjyzYX2a9NakoGzBi212oA8wlWJ4hlw5Rau4VEr1UIaOzhwqd88OB0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301334; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301336060158500 From: Taylor Simpson For now, assert the new method is a superset of the old method We'll remove the old method in a subsequent patch Reviewed-by: Marco Liebel Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 6 ++++++ target/hexagon/translate.c | 23 ++++++++++++++++++++++- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index d8628383f1d..964e6ce0b78 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -41,6 +41,8 @@ typedef struct DisasContext { DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS); bool pkt_ends_tb; + DECLARE_BITMAP(gpr_multi_write, TOTAL_PER_THREAD_REGS); + DECLARE_BITMAP(gpr_uncond, TOTAL_PER_THREAD_REGS); bool implicit_usr_write; #ifndef CONFIG_USER_ONLY int greg_log[GREG_WRITES_MAX]; @@ -157,9 +159,13 @@ static inline void ctx_log_reg_write(DisasContext *ctx= , int rnum, ctx->reg_log[ctx->reg_log_idx] =3D rnum; ctx->reg_log_idx++; set_bit(rnum, ctx->regs_written); + } else { + set_bit(rnum, ctx->gpr_multi_write); } if (is_predicated) { set_bit(rnum, ctx->predicated_regs); + } else { + set_bit(rnum, ctx->gpr_uncond); } } } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 29e02d8cc9e..0a7224a8e0f 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -579,6 +579,8 @@ static void clear_pkt_ctx(DisasContext *ctx) ctx->greg_log_idx =3D 0; ctx->sreg_log_idx =3D 0; #endif + bitmap_zero(ctx->gpr_multi_write, TOTAL_PER_THREAD_REGS); + bitmap_zero(ctx->gpr_uncond, TOTAL_PER_THREAD_REGS); ctx->preg_log_idx =3D 0; bitmap_zero(ctx->pregs_written, NUM_PREGS); ctx->future_vregs_idx =3D 0; @@ -605,6 +607,19 @@ static void clear_pkt_ctx(DisasContext *ctx) } } =20 +static bool pkt_has_write_conflict(DisasContext *ctx) +{ + DECLARE_BITMAP(gpr_conflict, TOTAL_PER_THREAD_REGS); + + bitmap_and(gpr_conflict, ctx->gpr_multi_write, ctx->gpr_uncond, + TOTAL_PER_THREAD_REGS); + if (!bitmap_empty(gpr_conflict, TOTAL_PER_THREAD_REGS)) { + return true; + } + + return false; +} + static void analyze_packet(DisasContext *ctx) { ctx->read_after_write =3D false; @@ -1210,7 +1225,13 @@ static void decode_and_translate_packet(CPUHexagonSt= ate *env, DisasContext *ctx) clear_pkt_ctx(ctx); analyze_packet(ctx); =20 - if (ctx->pkt.pkt_has_write_conflict) { + /* + * Check that the new method is a superset of the old methond + * Remove in a later patch + */ + g_assert(!ctx->pkt.pkt_has_write_conflict || + pkt_has_write_conflict(ctx)); + if (pkt_has_write_conflict(ctx)) { gen_exception_decode_fail(ctx, words_read, HEX_CAUSE_REG_WRITE_CONFLICT); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301533895158500 From: Taylor Simpson Instructions such as post-increment loads define multiple destinations These make it harder to detect multi-write conflicts Reviewed-by: Brian Cain Reviewed-by: Marco Liebel Signed-off-by: Taylor Simpson Signed-off-by: Brian Cain --- tests/tcg/hexagon/multiple-writes.c | 60 +++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/tests/tcg/hexagon/multiple-writes.c b/tests/tcg/hexagon/multip= le-writes.c index 8686317fdcc..4305903547d 100644 --- a/tests/tcg/hexagon/multiple-writes.c +++ b/tests/tcg/hexagon/multiple-writes.c @@ -143,6 +143,62 @@ static int test_zero(void) return sig; } =20 +/* Test multiple post-increment writes to the same GPR */ +static int test_post_increment1(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + ".word 0x9b004021 /* { r1 =3D memb(r0++#1) */\n" + ".word 0x9b00c022 /* r2 =3D memb(r0++#1) } */\n" + "1:\n" + "%0 =3D r0\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "memory"); + + return sig; +} + +static int test_post_increment2(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + ".word 0x9b00c020 /* r0 =3D memb(r0++#1) */\n" + "1:\n" + "%0 =3D r0\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "memory"); + + return sig; +} + +static int test_post_increment3(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + ".word 0x9bc1c020 /* r1:0 =3D memd(r1++#8) */\n" + "1:\n" + "%0 =3D r0\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "memory"); + + return sig; +} + int main() { struct sigaction act; @@ -164,6 +220,10 @@ int main() /* Illegal: zero encoding =3D duplex with duplicate dest R0 */ assert(test_zero() =3D=3D SIGILL); =20 + assert(test_post_increment1() =3D=3D SIGILL); + assert(test_post_increment2() =3D=3D SIGILL); + assert(test_post_increment3() =3D=3D SIGILL); + puts("PASS"); return EXIT_SUCCESS; } --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301473; cv=none; d=zohomail.com; s=zohoarc; b=I5AhNo+6XW95j5HkA4ioTlU8OSl8Ydn8trUsT4r2jT4sn3+/YCxwqrg9Tgkmiqy+r4hhdwdgcHB1v2d4gZM6Z87S9f5AOFsiod5JH6Eg9bare6N9MRC82RDNMOx3hRgOLWsCEl9Tjxxzz7tKDbKBsrYkCxFXUT+NOnpli2ZRT6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301473694158500 From: Taylor Simpson Reviewed-by: Marco Liebel Signed-off-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/translate.h | 12 +++++++++++- target/hexagon/translate.c | 9 +++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 964e6ce0b78..9ee5f253651 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -70,6 +70,8 @@ typedef struct DisasContext { DECLARE_BITMAP(vregs_select, NUM_VREGS); DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS); DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS); + DECLARE_BITMAP(vregs_multi_write, NUM_VREGS); + DECLARE_BITMAP(vregs_uncond, NUM_VREGS); DECLARE_BITMAP(insn_vregs_read, NUM_VREGS); int qreg_log[NUM_QREGS]; int qreg_log_idx; @@ -218,7 +220,11 @@ static inline void ctx_log_vreg_write(DisasContext *ct= x, ctx->has_hvx_overlap =3D true; } } - set_bit(rnum, ctx->vregs_written); + if (!test_bit(rnum, ctx->vregs_written)) { + set_bit(rnum, ctx->vregs_written); + } else { + set_bit(rnum, ctx->vregs_multi_write); + } if (type !=3D EXT_TMP) { if (!test_bit(rnum, ctx->vregs_updated)) { ctx->vreg_log[ctx->vreg_log_idx] =3D rnum; @@ -229,6 +235,8 @@ static inline void ctx_log_vreg_write(DisasContext *ctx, set_bit(rnum, ctx->vregs_updated); if (is_predicated) { set_bit(rnum, ctx->predicated_future_vregs); + } else { + set_bit(rnum, ctx->vregs_uncond); } } if (type =3D=3D EXT_NEW) { @@ -238,6 +246,8 @@ static inline void ctx_log_vreg_write(DisasContext *ctx, set_bit(rnum, ctx->vregs_updated_tmp); if (is_predicated) { set_bit(rnum, ctx->predicated_tmp_vregs); + } else { + set_bit(rnum, ctx->vregs_uncond); } } } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 0a7224a8e0f..85b5404fcc4 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -591,6 +591,8 @@ static void clear_pkt_ctx(DisasContext *ctx) bitmap_zero(ctx->vregs_updated, NUM_VREGS); bitmap_zero(ctx->vregs_select, NUM_VREGS); bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS); + bitmap_zero(ctx->vregs_multi_write, NUM_VREGS); + bitmap_zero(ctx->vregs_uncond, NUM_VREGS); bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS); bitmap_zero(ctx->qregs_written, NUM_QREGS); ctx->qreg_log_idx =3D 0; @@ -610,6 +612,7 @@ static void clear_pkt_ctx(DisasContext *ctx) static bool pkt_has_write_conflict(DisasContext *ctx) { DECLARE_BITMAP(gpr_conflict, TOTAL_PER_THREAD_REGS); + DECLARE_BITMAP(vregs_conflict, NUM_VREGS); =20 bitmap_and(gpr_conflict, ctx->gpr_multi_write, ctx->gpr_uncond, TOTAL_PER_THREAD_REGS); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301451625158500 From: Taylor Simpson Signed-off-by: Taylor Simpson Reviewed-by: Marco Liebel Reviewed-by: Brian Cain Signed-off-by: Brian Cain --- tests/tcg/hexagon/multiple-writes.c | 66 +++++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 2 +- 2 files changed, 67 insertions(+), 1 deletion(-) diff --git a/tests/tcg/hexagon/multiple-writes.c b/tests/tcg/hexagon/multip= le-writes.c index 4305903547d..62e5828a0af 100644 --- a/tests/tcg/hexagon/multiple-writes.c +++ b/tests/tcg/hexagon/multiple-writes.c @@ -199,6 +199,68 @@ static int test_post_increment3(void) return sig; } =20 +static int test_vreg_legal_predicated(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + "r2 =3D #7\n" + "r3 =3D #13\n" + "p0 =3D cmp.eq(r2, r3)\n" + "{\n" + " if (p0) v0 =3D v1\n" + " if (!p0) v0 =3D v2\n" + "}\n" + "1:\n" + "%0 =3D #23\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "r2", "r3", "p0", "v0", "v1", "memory"); + + return sig; +} + +static int test_vreg_illegal_mixed(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + ".word 0x1a004100 /* { if (p0) v0 =3D v1 */\n" + ".word 0x1e03e2e0 /* v0 =3D v2 } */\n" + "1:\n" + "%0 =3D r0\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "memory"); + + return sig; +} + +static int test_vreg_illegal_uncond(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + ".word 0x1e0361e0 /* { v0 =3D v1 */\n" + ".word 0x1e03e2e0 /* v0 =3D v2 } */\n" + "1:\n" + "%0 =3D r0\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "memory"); + + return sig; +} + int main() { struct sigaction act; @@ -224,6 +286,10 @@ int main() assert(test_post_increment2() =3D=3D SIGILL); assert(test_post_increment3() =3D=3D SIGILL); =20 + assert(test_vreg_legal_predicated() =3D=3D 23); + assert(test_vreg_illegal_mixed() =3D=3D SIGILL); + assert(test_vreg_illegal_uncond() =3D=3D SIGILL); + puts("PASS"); return EXIT_SUCCESS; } diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index 6e36a9a1220..e3017db24f6 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -54,7 +54,7 @@ tests +=3D { 'load_unpack.c': {'cflags': cflags}, # Build this test with -mv71 to exercise the CABAC instruction 'misc.c': {'cflags': [cflags, '-mv71', '-O2']}, - 'multiple-writes.c': {'cflags': cflags}, + 'multiple-writes.c': {'cflags': [cflags, '-mhvx']}, 'overflow.c': {'cflags': cflags, 'exe_name': 'hex-overflow'}, 'preg_alias.c': {'cflags': cflags}, 'dual_stores.c': {'cflags': cflags}, --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301511788158500 From: Taylor Simpson Reviewed-by: Marco Liebel Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 7 ++++++- target/hexagon/translate.c | 5 +++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 9ee5f253651..b6cdf51c205 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -76,6 +76,7 @@ typedef struct DisasContext { int qreg_log[NUM_QREGS]; int qreg_log_idx; DECLARE_BITMAP(qregs_written, NUM_QREGS); + DECLARE_BITMAP(qregs_multi_write, NUM_QREGS); DECLARE_BITMAP(insn_qregs_written, NUM_QREGS); DECLARE_BITMAP(insn_qregs_read, NUM_QREGS); bool pre_commit; @@ -308,7 +309,11 @@ static inline void ctx_log_qreg_write(DisasContext *ct= x, ctx->has_hvx_overlap =3D true; } } - set_bit(rnum, ctx->qregs_written); + if (!test_bit(rnum, ctx->qregs_written)) { + set_bit(rnum, ctx->qregs_written); + } else { + set_bit(rnum, ctx->qregs_multi_write); + } ctx->qreg_log[ctx->qreg_log_idx] =3D rnum; ctx->qreg_log_idx++; } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 85b5404fcc4..9ad47b1838a 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -595,6 +595,7 @@ static void clear_pkt_ctx(DisasContext *ctx) bitmap_zero(ctx->vregs_uncond, NUM_VREGS); bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS); bitmap_zero(ctx->qregs_written, NUM_QREGS); + bitmap_zero(ctx->qregs_multi_write, NUM_QREGS); ctx->qreg_log_idx =3D 0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301463647158500 From: Taylor Simpson Reviewed-by: Marco Liebel Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Signed-off-by: Brian Cain --- tests/tcg/hexagon/multiple-writes.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/tests/tcg/hexagon/multiple-writes.c b/tests/tcg/hexagon/multip= le-writes.c index 62e5828a0af..bd2b1384dd9 100644 --- a/tests/tcg/hexagon/multiple-writes.c +++ b/tests/tcg/hexagon/multiple-writes.c @@ -261,6 +261,27 @@ static int test_vreg_illegal_uncond(void) return sig; } =20 +static int test_qreg_illegal(void) +{ + int sig; + + asm volatile( + "r0 =3D #0\n" + "r1 =3D ##1f\n" + "memw(%1) =3D r1\n" + "{\n" + ".word 0x19a14048 /* { q0 =3D vand(v0, r1) */\n" + ".word 0x19a0c044 /* q0 =3D vsetq(r0) } */\n" + "}\n" + "1:\n" + "%0 =3D r0\n" + : "=3Dr"(sig) + : "r"(&resume_pc) + : "r0", "r1", "memory"); + + return sig; +} + int main() { struct sigaction act; @@ -290,6 +311,8 @@ int main() assert(test_vreg_illegal_mixed() =3D=3D SIGILL); assert(test_vreg_illegal_uncond() =3D=3D SIGILL); =20 + assert(test_qreg_illegal() =3D=3D SIGILL); + puts("PASS"); return EXIT_SUCCESS; } --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301516; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301517857158500 From: Taylor Simpson Signed-off-by: Taylor Simpson Reviewed-by: Marco Liebel Reviewed-by: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 11 +++++++++-- target/hexagon/translate.c | 8 ++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index b6cdf51c205..eb0d10d686c 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -47,6 +47,8 @@ typedef struct DisasContext { #ifndef CONFIG_USER_ONLY int greg_log[GREG_WRITES_MAX]; int greg_log_idx; + DECLARE_BITMAP(gregs_written, NUM_GREGS); + DECLARE_BITMAP(gregs_multi_write, NUM_GREGS); int sreg_log[SREG_WRITES_MAX]; int sreg_log_idx; TCGv_i32 t_sreg_new_value[HEX_SREG_GLB_START]; @@ -105,8 +107,13 @@ static inline void ctx_log_greg_write(DisasContext *ct= x, int rnum) if (rnum > HEX_GREG_G3) { return; } - ctx->greg_log[ctx->greg_log_idx] =3D rnum; - ctx->greg_log_idx++; + if (!test_bit(rnum, ctx->gregs_written)) { + set_bit(rnum, ctx->gregs_written); + ctx->greg_log[ctx->greg_log_idx] =3D rnum; + ctx->greg_log_idx++; + } else { + set_bit(rnum, ctx->gregs_multi_write); + } } =20 static inline void ctx_log_greg_write_pair(DisasContext *ctx, int rnum) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 9ad47b1838a..bcc4a6e6eff 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -577,6 +577,8 @@ static void clear_pkt_ctx(DisasContext *ctx) bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); #ifndef CONFIG_USER_ONLY ctx->greg_log_idx =3D 0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301483741158500 From: Taylor Simpson Signed-off-by: Taylor Simpson Reviewed-by: Marco Liebel Reviewed-by: Brian Cain Signed-off-by: Brian Cain --- target/hexagon/translate.h | 11 +++++++++-- target/hexagon/translate.c | 6 ++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index eb0d10d686c..b90f7fff1c1 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -51,6 +51,8 @@ typedef struct DisasContext { DECLARE_BITMAP(gregs_multi_write, NUM_GREGS); int sreg_log[SREG_WRITES_MAX]; int sreg_log_idx; + DECLARE_BITMAP(sregs_written, NUM_SREGS); + DECLARE_BITMAP(sregs_multi_write, NUM_SREGS); TCGv_i32 t_sreg_new_value[HEX_SREG_GLB_START]; TCGv_i32 greg_new_value[NUM_GREGS]; #endif @@ -125,8 +127,13 @@ static inline void ctx_log_greg_write_pair(DisasContex= t *ctx, int rnum) =20 static inline void ctx_log_sreg_write(DisasContext *ctx, int rnum) { - ctx->sreg_log[ctx->sreg_log_idx] =3D rnum; - ctx->sreg_log_idx++; + if (!test_bit(rnum, ctx->sregs_written)) { + set_bit(rnum, ctx->sregs_written); + ctx->sreg_log[ctx->sreg_log_idx] =3D rnum; + ctx->sreg_log_idx++; + } else { + set_bit(rnum, ctx->sregs_multi_write); + } } =20 static inline void ctx_log_sreg_write_pair(DisasContext *ctx, int rnum) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index bcc4a6e6eff..81f8895e47b 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -580,6 +580,8 @@ static void clear_pkt_ctx(DisasContext *ctx) bitmap_zero(ctx->gregs_written, NUM_GREGS); bitmap_zero(ctx->gregs_multi_write, NUM_GREGS); ctx->sreg_log_idx =3D 0; + bitmap_zero(ctx->sregs_written, NUM_SREGS); + bitmap_zero(ctx->sregs_multi_write, NUM_SREGS); #endif bitmap_zero(ctx->gpr_multi_write, TOTAL_PER_THREAD_REGS); bitmap_zero(ctx->gpr_uncond, TOTAL_PER_THREAD_REGS); @@ -637,6 +639,10 @@ static bool pkt_has_write_conflict(DisasContext *ctx) if (!bitmap_empty(ctx->gregs_multi_write, NUM_GREGS)) { return true; } + + if (!bitmap_empty(ctx->sregs_multi_write, NUM_SREGS)) { + return true; + } #endif =20 return false; --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301472; cv=none; d=zohomail.com; s=zohoarc; b=QMXGgEMZv2PjCCSch7BAaqLuPUg4JKTi66O08NFU6m0yvIYjhGUDf+Tet2cU4uqbm5RG03d0jc3k3Xkb7PuspEuhqCmMqOtLDGccFu1PME++1Vh2BNWjdkISj8pcHZ98Jp6RJybYkvy2JP5f9MEy0tarX+/N8uMg9nhstPfrKOk= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301473743158500 From: Taylor Simpson We now detect register multiwrites in packet analysis instead of packet decoding Reviewed-by: Brian Cain Reviewed-by: Marco Liebel Signed-off-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/insn.h | 4 --- target/hexagon/decode.c | 54 ------------------------------- target/hexagon/translate.c | 6 ---- target/hexagon/gen_trans_funcs.py | 10 ------ 4 files changed, 74 deletions(-) diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h index 835b1c954ed..5d59430da9e 100644 --- a/target/hexagon/insn.h +++ b/target/hexagon/insn.h @@ -41,8 +41,6 @@ struct Instruction { uint32_t new_value_producer_slot:4; int32_t new_read_idx; int32_t dest_idx; - bool dest_is_pair; - bool dest_is_gpr; bool has_pred_dest; =20 bool part1; /* @@ -74,8 +72,6 @@ struct Packet { bool pkt_has_hvx; Insn *vhist_insn; =20 - bool pkt_has_write_conflict; - Insn insn[INSTRUCTIONS_MAX]; }; =20 diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index b12e91fe6a6..89e961331ff 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -691,55 +691,6 @@ bool opcode_supported(uint16_t opcode, const HexagonCP= UDef *hex_def) return true; } =20 -/* - * Check for GPR write conflicts in the packet. - * A conflict exists when a register is written by more than one instructi= on - * and at least one of those writes is unconditional. - * - * TODO: handle the more general case of any - * packet w/multiple-register-write operands. - */ -static bool pkt_has_write_conflict(Packet *pkt) -{ - DECLARE_BITMAP(all_dest_gprs, 32) =3D { 0 }; - DECLARE_BITMAP(wreg_mult_gprs, 32) =3D { 0 }; - DECLARE_BITMAP(uncond_wreg_gprs, 32) =3D { 0 }; - DECLARE_BITMAP(conflict, 32); - - for (int i =3D 0; i < pkt->num_insns; i++) { - Insn *insn =3D &pkt->insn[i]; - int dest =3D insn->dest_idx; - - if (dest < 0 || !insn->dest_is_gpr) { - continue; - } - - int rnum =3D insn->regno[dest]; - bool is_uncond =3D !GET_ATTRIB(insn->opcode, A_CONDEXEC); - - if (test_bit(rnum, all_dest_gprs)) { - set_bit(rnum, wreg_mult_gprs); - } - set_bit(rnum, all_dest_gprs); - if (is_uncond) { - set_bit(rnum, uncond_wreg_gprs); - } - - if (insn->dest_is_pair) { - if (test_bit(rnum + 1, all_dest_gprs)) { - set_bit(rnum + 1, wreg_mult_gprs); - } - set_bit(rnum + 1, all_dest_gprs); - if (is_uncond) { - set_bit(rnum + 1, uncond_wreg_gprs); - } - } - } - - bitmap_and(conflict, wreg_mult_gprs, uncond_wreg_gprs, 32); - return !bitmap_empty(conflict, 32); -} - /* * decode_packet * Decodes packet with given words @@ -759,10 +710,6 @@ int decode_packet(DisasContext *ctx, int max_words, co= nst uint32_t *words, =20 /* Initialize */ memset(pkt, 0, sizeof(*pkt)); - for (i =3D 0; i < INSTRUCTIONS_MAX; i++) { - pkt->insn[i].dest_idx =3D -1; - pkt->insn[i].new_read_idx =3D -1; - } /* Try to build packet */ while (!end_of_packet && (words_read < max_words)) { Insn *insn =3D &pkt->insn[num_insns]; @@ -837,7 +784,6 @@ int decode_packet(DisasContext *ctx, int max_words, con= st uint32_t *words, /* Invalid packet */ return 0; } - pkt->pkt_has_write_conflict =3D pkt_has_write_conflict(pkt); } decode_fill_newvalue_regno(pkt); =20 diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 81f8895e47b..8561cec4e41 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -1253,12 +1253,6 @@ static void decode_and_translate_packet(CPUHexagonSt= ate *env, DisasContext *ctx) clear_pkt_ctx(ctx); analyze_packet(ctx); =20 - /* - * Check that the new method is a superset of the old methond - * Remove in a later patch - */ - g_assert(!ctx->pkt.pkt_has_write_conflict || - pkt_has_write_conflict(ctx)); if (pkt_has_write_conflict(ctx)) { gen_exception_decode_fail(ctx, words_read, HEX_CAUSE_REG_WRITE_CONFLICT); diff --git a/target/hexagon/gen_trans_funcs.py b/target/hexagon/gen_trans_f= uncs.py index 19c1f9fdea5..45da1b7b5df 100755 --- a/target/hexagon/gen_trans_funcs.py +++ b/target/hexagon/gen_trans_funcs.py @@ -91,8 +91,6 @@ def gen_trans_funcs(f): new_read_idx =3D -1 dest_idx =3D -1 dest_idx_reg_id =3D None - dest_is_pair =3D "false" - dest_is_gpr =3D "false" has_pred_dest =3D "false" for regno, (reg_type, reg_id, *_) in enumerate(regs): reg =3D hex_common.get_register(tag, reg_type, reg_id) @@ -106,12 +104,6 @@ def gen_trans_funcs(f): if dest_idx_reg_id is None or reg_id < dest_idx_reg_id: dest_idx =3D regno dest_idx_reg_id =3D reg_id - dest_is_pair =3D ("true" - if isinstance(reg, hex_common.Pair) - else "false") - dest_is_gpr =3D ("true" - if reg_type =3D=3D "R" - else "false") if reg_type =3D=3D "P" and reg.is_written() and not reg.is_rea= d(): has_pred_dest =3D "true" =20 @@ -137,8 +129,6 @@ def gen_trans_funcs(f): f.write(code_fmt(f"""\ insn->new_read_idx =3D {new_read_idx}; insn->dest_idx =3D {dest_idx}; - insn->dest_is_pair =3D {dest_is_pair}; - insn->dest_is_gpr =3D {dest_is_gpr}; insn->has_pred_dest =3D {has_pred_dest}; """)) f.write(textwrap.dedent(f"""\ --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301375; cv=none; d=zohomail.com; s=zohoarc; b=kw2nswFjVdUBnJOknynlRerNY/znCJZZN9UTFPe6irM+bMMDaNOpQKfz19/1rsU6yThy+sbzk3iarOdIs5Hg2KOw8Fe9SfNXn2yWCqG8kyQCx6GuKphBImaEAwfA3UCpZNv3FWNS62JHKoACBECCEVfEA+wbA1Jyms6BIdVLfR4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301375; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301377340158500 Cast operands to uint32_t before left-shifting in build_mreg() to avoid undefined behavior when the shift result overflows int32_t. Found with UBSan. Reviewed-by: Sid Manning Signed-off-by: Brian Cain --- tests/tcg/hexagon/circ.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/tcg/hexagon/circ.c b/tests/tcg/hexagon/circ.c index ab949ebef1c..2a15c324242 100644 --- a/tests/tcg/hexagon/circ.c +++ b/tests/tcg/hexagon/circ.c @@ -97,9 +97,9 @@ INIT(dbuf, NDOBLS) */ static int32_t build_mreg(int32_t inc, int32_t K, int32_t len) { - return ((inc & 0x780) << 21) | - ((K & 0xf) << 24) | - ((inc & 0x7f) << 17) | + return ((uint32_t)(inc & 0x780) << 21) | + ((uint32_t)(K & 0xf) << 24) | + ((uint32_t)(inc & 0x7f) << 17) | (len & 0x1ffff); } =20 --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301436; cv=none; d=zohomail.com; s=zohoarc; b=e1EAu/M2+kvHy5SEBWm0SuadDeJ5UPozROvkMRf8opP72h1iERZq9JdSNW5wgtp++dSnqsECvBigetzrkQaVukqgbqtEbr8lp0I9g/EztDurcYqr1ORGiJ1sy7hZ0TaRyEG6UghPq6w7tE3VFVrhEltVVXFdEPUFW8FtTanB75I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301436; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zF7wNM0uK32PaFnM0cjYMMOMVW+Srqc+PhvZl4ELL8A=; b=I9k7/fx2u2Ez/VH0uWyBhaEiLBGp+1ucC2z1/4i6FoPL3M2W62ADUzw4j23HM8Gf665nQxWcWOtGaQx/Jd4xxJRQ2T+q9QLF5XP2GO2TqcnNnGW2Y89L/UclaJDdqveNHVC2eHRgcBKbRjx+tav3wWyrCKOq+gsI3rnZrx+JkjM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 179030143634015.15021379783559; Thu, 24 Sep 2026 18:57:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9v9b-0005A9-2s; Thu, 24 Sep 2026 21:55:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9O-0004xB-3X for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:54:58 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9M-0005t8-Fu for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:54:57 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1kn573181623 for ; Fri, 25 Sep 2026 01:54:54 GMT Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw94k99ej-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 01:54:54 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-331b2ec616fso1392831eec.1 for ; Thu, 24 Sep 2026 18:54:54 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301438044158500 Cast to uint32_t before left-shifting in sext8() to avoid undefined behavior when shifting a negative value. The subsequent arithmetic right shift on the int32_t cast correctly sign-extends the result. Found with UBSan. Reviewed-by: Sid Manning Signed-off-by: Brian Cain --- tests/tcg/hexagon/brev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tcg/hexagon/brev.c b/tests/tcg/hexagon/brev.c index 6c7b1340849..1473e309ee0 100644 --- a/tests/tcg/hexagon/brev.c +++ b/tests/tcg/hexagon/brev.c @@ -106,7 +106,7 @@ uint32_t bitreverse(uint32_t x) =20 int32_t sext8(int32_t x) { - return (x << 24) >> 24; + return (int32_t)((uint32_t)x << 24) >> 24; } =20 #define TEST_BREV_LOAD(SZ, TYPE, BUF, SHIFT, EXP) \ --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301360; cv=none; d=zohomail.com; s=zohoarc; b=UtZHUgK4KjSwsqNnNImwNge8c7xeIpeIu/tVxrCvjcNt/N/5IzTSbsqxZPgmU/K/CxFMEukek0BaIMhICNS2xRW7Su6PB6HlBwg2SQidAr3l5zpQ72lHr+V3TkqdfECDmbT5SQvCjiSzPnjewmFmLezJHJYC2gE102aY0qLNjwY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301360; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IcJNdY4hlB5wuvciSxp0uXAgBsXsEcVgYAWPzivXFtc=; b=fRVZ1HgOt0CA/6IdzbMtUsVo2jUFz5OzcACVUVKCZe+x6hmZW2S0gFpb4LSKe7faOANKyFn0WIIPOnbJXYLbJjl5BjEc1j9a79x3fFb2oBopVF28ZbaPVrFBreSibiwlO+j4vZuudg0qJmf2DnpG67advoiU+PiiRJw7XbowUnc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790301360348288.93373766677905; Thu, 24 Sep 2026 18:56:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9v9X-00050a-0R; Thu, 24 Sep 2026 21:55:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9P-0004xv-Gz for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:54:59 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9N-0005tT-RA for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:54:59 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1lOBO3885763 for ; Fri, 25 Sep 2026 01:54:57 GMT Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw4652s20-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 01:54:56 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-33310847fcaso651445eec.1 for ; Thu, 24 Sep 2026 18:54:56 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301363295158500 Use unsigned (.uw) instead of signed (.w) array members for vector addition and subtraction reference calculations to avoid signed integer overflow. Wrapping arithmetic is well-defined for unsigned types. Add CHECK_OUTPUT_FUNC(uw, 4) to support unsigned word comparisons in the TEST_VEC_OP2 macro. Found with UBSan. Reviewed-by: Sid Manning Signed-off-by: Brian Cain --- tests/tcg/hexagon/hvx_misc.h | 1 + tests/tcg/hexagon/hvx_misc.c | 18 +++++++++--------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/tests/tcg/hexagon/hvx_misc.h b/tests/tcg/hexagon/hvx_misc.h index c21ea975c16..e32715ed11d 100644 --- a/tests/tcg/hexagon/hvx_misc.h +++ b/tests/tcg/hexagon/hvx_misc.h @@ -69,6 +69,7 @@ static inline void check_output_##FIELD(int line, size_t = num_vectors) \ CHECK_OUTPUT_FUNC(d, 8) CHECK_OUTPUT_FUNC(w, 4) CHECK_OUTPUT_FUNC(sf, 4) +CHECK_OUTPUT_FUNC(uw, 4) CHECK_OUTPUT_FUNC(h, 2) CHECK_OUTPUT_FUNC(uh, 2) CHECK_OUTPUT_FUNC(hf, 2) diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c index 32a3661a86f..f20afc8e670 100644 --- a/tests/tcg/hexagon/hvx_misc.c +++ b/tests/tcg/hexagon/hvx_misc.c @@ -55,7 +55,7 @@ static void test_load_tmp(void) pout +=3D sizeof(MMVector); =20 for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { - expect[i].w[j] =3D buffer0[i].w[j] + buffer1[i].w[j] + 1; + expect[i].uw[j] =3D buffer0[i].uw[j] + buffer1[i].uw[j] + 1; } } =20 @@ -285,8 +285,8 @@ static void test_max_temps() =20 /* The first two vectors come from the vadd-pair instruction */ for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { - expect[0].w[i] =3D buffer0[0].w[i] + buffer0[2].w[i]; - expect[1].w[i] =3D buffer0[1].w[i] + buffer0[3].w[i]; + expect[0].uw[i] =3D buffer0[0].uw[i] + buffer0[2].uw[i]; + expect[1].uw[i] =3D buffer0[1].uw[i] + buffer0[3].uw[i]; } /* The third vector comes from the vshuffe instruction */ for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { @@ -295,7 +295,7 @@ static void test_max_temps() } /* The fourth vector comes from the vadd-single instruction */ for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { - expect[3].w[i] =3D buffer0[1].w[i] + buffer0[5].w[i]; + expect[3].uw[i] =3D buffer0[1].uw[i] + buffer0[5].uw[i]; } /* * The fifth vector comes from the load to v4 @@ -306,10 +306,10 @@ static void test_max_temps() check_output_b(__LINE__, 5); } =20 -TEST_VEC_OP2(vadd_w, vadd, .w, w, 4, +) +TEST_VEC_OP2(vadd_w, vadd, .w, uw, 4, +) TEST_VEC_OP2(vadd_h, vadd, .h, h, 2, +) TEST_VEC_OP2(vadd_b, vadd, .b, b, 1, +) -TEST_VEC_OP2(vsub_w, vsub, .w, w, 4, -) +TEST_VEC_OP2(vsub_w, vsub, .w, uw, 4, -) TEST_VEC_OP2(vsub_h, vsub, .h, h, 2, -) TEST_VEC_OP2(vsub_b, vsub, .b, b, 1, -) TEST_VEC_OP2(vxor, vxor, , d, 8, ^) @@ -489,9 +489,9 @@ static void test_load_tmp_predicated(void) pout +=3D sizeof(MMVector); =20 for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 4; j++) { - expect[i].w[j] =3D - pred ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301336041158500 Cast to uint32_t before multiplying uint16_t values to prevent signed integer overflow. Without the cast, the uint16_t operands are promoted to int, and the product can overflow the int range. Found with UBSan. Reviewed-by: Sid Manning Signed-off-by: Brian Cain --- tests/tcg/hexagon/v69_hvx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/tcg/hexagon/v69_hvx.c b/tests/tcg/hexagon/v69_hvx.c index a0d567d142f..eff936064a0 100644 --- a/tests/tcg/hexagon/v69_hvx.c +++ b/tests/tcg/hexagon/v69_hvx.c @@ -292,7 +292,8 @@ static void test_vmpyuhvs(void) pout +=3D sizeof(MMVector); =20 for (int j =3D 0; j < MAX_VEC_SIZE_BYTES / 2; j++) { - expect[i].uh[j] =3D (buffer0[i].uh[j] * buffer1[i].uh[j]) >> 1= 6; + expect[i].uh[j] =3D + ((uint32_t)buffer0[i].uh[j] * buffer1[i].uh[j]) >> 16; } } =20 --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301610; cv=none; d=zohomail.com; s=zohoarc; b=MnX1Armzemdh3+ChOm5osRxELkCaCIz8D3lqAzCbsx0EQnlGlTquNACtMWEUReRPBSmVaP9ouJKgHoSSOA6J6yN58snITFKJmeLfHW5Mpo59DpetejUfX5+OXG5ub+Sbuvwdb6NHPmIKuNbItpTZX/7nzTWwpX6B/4cplA2bjvE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301610; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mSFZtLAuVFymlxGuE/xeSBNBNcWYKAtnUcskIIJlCHU=; b=RorBQOflxULQjv58ZoQ4V3wu4cI9UrzT+jfk+2RSG71XXaT7VNJlTgFP9xLRRP27J+hugnYaT/g8XvKgBCrks8XNj3FYsEAS7Cj0TL07xUvFg+JqfLoMN5mRHnFA3VB97gKWnNk/quZkc2zd+rJLSQY9+ygdsA93LolixdIz76M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790301610224760.795720646577; Thu, 24 Sep 2026 19:00:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9v9Z-00055u-JJ; Thu, 24 Sep 2026 21:55:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9S-0004zM-5M for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:03 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9P-0005tr-Vh for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:01 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1kpRG155525 for ; Fri, 25 Sep 2026 01:54:59 GMT Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw1tjkd7v-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 01:54:58 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-33310847fcaso651484eec.1 for ; Thu, 24 Sep 2026 18:54:58 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301612207158500 Add __attribute__((no_sanitize("undefined"))) to the float/double to integer conversion functions. C17 6.3.1.4p1 only defines float-to-integer conversion for finite values whose integral part fits in the destination type; it discards the fractional part and explicitly makes it UB if the integral part doesn't fit. These tests intentionally exercise both of those UB cases, so we'll suppress it to get a clean ubsan run on the TCG test suite. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/multiarch/float_convd.c | 1 + tests/tcg/multiarch/float_convs.c | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/tcg/multiarch/float_convd.c b/tests/tcg/multiarch/float_= convd.c index 58d7f8b4c58..cb3884df974 100644 --- a/tests/tcg/multiarch/float_convd.c +++ b/tests/tcg/multiarch/float_convd.c @@ -62,6 +62,7 @@ static void convert_double_to_single(double input) #define str(a) #a =20 #define CONVERT_DOUBLE_TO_INT(TYPE, FMT) \ + __attribute__((no_sanitize("undefined"))) \ static void convert_double_to_ ## TYPE(double input) \ { \ TYPE ## _t output; \ diff --git a/tests/tcg/multiarch/float_convs.c b/tests/tcg/multiarch/float_= convs.c index cb1fdd439e3..584ce89aa17 100644 --- a/tests/tcg/multiarch/float_convs.c +++ b/tests/tcg/multiarch/float_convs.c @@ -62,6 +62,7 @@ static void convert_single_to_double(float input) #define str(a) #a =20 #define CONVERT_SINGLE_TO_INT(TYPE, FMT) \ + __attribute__((no_sanitize("undefined"))) \ static void convert_single_to_ ## TYPE(float input) \ { \ TYPE ## _t output; \ --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301588; cv=none; d=zohomail.com; s=zohoarc; b=Lbdcm32CoZPcr4oBTH5xK/2xMygMgd2YEXhLo62lGtSz+bZ05aNzVmVb67EJt0vx/Mu4ZCnBtu8EidjMUh9RR8XPwYK+4PoQjwDA5qwvu8+L2yvvVmsEva4uQG+H9Nu5Kg4M7670ww14f2FZh/E2tPZKRN4DG3R+2NAColdztVo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301588; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=d+11tnix2V/bt8ArMEcPhg4E6n1O2gIEaiQ5iZ3BXXI=; b=NKXa009CTfljw6JnLlyCp5muu3KnO5n6EnB2uOFVEOqvYj2TQz6oZBGCBI0Cy4MMpWppoc0s85PxbPPqjNDEjEozVFRJmN9p4QzWeGLqdXKh1hxDi/qx5P/1wYl54QBF+hLSa1KbbqhZi3+CEpufVmKzf8TXxwR1KVJPj/Cmt3Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790301588386309.0108785270287; Thu, 24 Sep 2026 18:59:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9v9Z-000557-1H; Thu, 24 Sep 2026 21:55:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9U-00050C-SF for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:05 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9R-0005u5-UZ for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:04 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1kld0313548 for ; Fri, 25 Sep 2026 01:55:00 GMT Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw1s93d81-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 01:55:00 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-3412efc2661so500095eec.1 for ; Thu, 24 Sep 2026 18:55:00 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301590156158500 Add sfclass/dfclass FP classification tests, unsigned-to-double conversions, and dfmpyfix denormal fixup tests. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/fpstuff.c | 175 ++++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index 6aadaccabdf..7561f31cdc3 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -711,6 +711,176 @@ static void check_dfmpyxx(void) check64(res64, 0x7fefffffffffffffULL); } =20 +/* + * sfclass mask bits: + * bit 0: positive/negative zero + * bit 1: positive/negative normal + * bit 2: positive/negative denormal + * bit 3: positive/negative infinity + * bit 4: positive/negative NaN + */ +#define TEST_SFCLASS(VAL, MASK, EXPECT) \ + do { \ + uint32_t res; \ + asm("%[res] =3D #0\n\t" \ + "p0 =3D sfclass(%[val], #" #MASK ")\n\t" \ + "if (p0) %[res] =3D #1\n\t" \ + : [res] "=3D&r"(res) \ + : [val] "r"(VAL) \ + : "p0"); \ + check32(res, EXPECT); \ + } while (0) + +static void check_sfclass(void) +{ + /* Zero: mask bit 0 */ + TEST_SFCLASS(SF_zero, 0x01, 1); + TEST_SFCLASS(SF_zero_neg, 0x01, 1); + TEST_SFCLASS(SF_zero, 0x02, 0); + + /* Normal: mask bit 1 */ + TEST_SFCLASS(SF_one, 0x02, 1); + TEST_SFCLASS(SF_one, 0x01, 0); + + /* Denormal: mask bit 2 */ + TEST_SFCLASS(SF_denorm, 0x04, 1); + TEST_SFCLASS(SF_denorm, 0x01, 0); + + /* Infinity: mask bit 3 */ + TEST_SFCLASS(SF_INF, 0x08, 1); + TEST_SFCLASS(SF_INF, 0x01, 0); + + /* NaN: mask bit 4 */ + TEST_SFCLASS(SF_QNaN, 0x10, 1); + TEST_SFCLASS(SF_SNaN, 0x10, 1); + TEST_SFCLASS(SF_QNaN, 0x01, 0); + + /* Combined: any class (all bits set) */ + TEST_SFCLASS(SF_one, 0x1f, 1); +} + +/* + * dfclass mask bits are the same as sfclass. + */ +static const uint64_t DF_INF =3D 0x7ff0000000000000ULL; +static const uint64_t DF_denorm =3D 0x0000000000000001ULL; +static const uint64_t DF_neg_one =3D 0xbff0000000000000ULL; + +#define TEST_DFCLASS(VAL, MASK, EXPECT) \ + do { \ + uint32_t res; \ + asm("%[res] =3D #0\n\t" \ + "p0 =3D dfclass(%[val], #" #MASK ")\n\t" \ + "if (p0) %[res] =3D #1\n\t" \ + : [res] "=3D&r"(res) \ + : [val] "r"(VAL) \ + : "p0"); \ + check32(res, EXPECT); \ + } while (0) + +static void check_dfclass(void) +{ + /* Zero: mask bit 0 */ + TEST_DFCLASS(DF_zero, 0x01, 1); + TEST_DFCLASS(DF_zero_neg, 0x01, 1); + TEST_DFCLASS(DF_zero, 0x02, 0); + + /* Normal: mask bit 1 */ + TEST_DFCLASS(DF_one, 0x02, 1); + TEST_DFCLASS(DF_neg_one, 0x02, 1); + TEST_DFCLASS(DF_one, 0x01, 0); + + /* Denormal: mask bit 2 */ + TEST_DFCLASS(DF_denorm, 0x04, 1); + TEST_DFCLASS(DF_denorm, 0x01, 0); + + /* Infinity: mask bit 3 */ + TEST_DFCLASS(DF_INF, 0x08, 1); + TEST_DFCLASS(DF_INF, 0x01, 0); + + /* NaN: mask bit 4 */ + TEST_DFCLASS(DF_QNaN, 0x10, 1); + TEST_DFCLASS(DF_SNaN, 0x10, 1); + TEST_DFCLASS(DF_QNaN, 0x01, 0); +} + +/* Rdd =3D convert_uw2df(Rs) */ +static uint64_t conv_uw2df(uint32_t val) +{ + uint64_t result; + + asm("%[res] =3D convert_uw2df(%[val])\n\t" + : [res] "=3Dr"(result) + : [val] "r"(val)); + return result; +} + +static void check_conv_uw2df(void) +{ + check64(conv_uw2df(0), DF_zero); + check64(conv_uw2df(1), DF_one); + /* 100 -> 0x4059000000000000 */ + check64(conv_uw2df(100), 0x4059000000000000ULL); + /* 0xFFFFFFFF -> 4294967295.0 =3D 0x41EFFFFFFFE00000 */ + check64(conv_uw2df(0xFFFFFFFF), 0x41EFFFFFFFE00000ULL); +} + +/* Rdd =3D convert_ud2df(Rss) */ +static uint64_t conv_ud2df(uint64_t val) +{ + uint64_t result; + + asm("%[res] =3D convert_ud2df(%[val])\n\t" + : [res] "=3Dr"(result) + : [val] "r"(val)); + return result; +} + +static void check_conv_ud2df(void) +{ + check64(conv_ud2df(0ULL), DF_zero); + check64(conv_ud2df(1ULL), DF_one); + /* 1000000 -> 0x412E848000000000 */ + check64(conv_ud2df(1000000ULL), 0x412E848000000000ULL); +} + +/* Rdd =3D dfmpyfix(Rss,Rtt) -- DF multiply denormal fixup */ +static uint64_t do_dfmpyfix(uint64_t a, uint64_t b) +{ + uint64_t result; + + asm("%[res] =3D dfmpyfix(%[a], %[b])\n\t" + : [res] "=3Dr"(result) + : [a] "r"(a), [b] "r"(b)); + return result; +} + +static void check_dfmpyfix(void) +{ + /* + * With two normal values (neither denormal, exps < 512), + * the result should be the first operand unchanged. + */ + check64(do_dfmpyfix(DF_one, DF_one), DF_one); + + /* + * Case: b is denormal AND a is normal with exp >=3D 512. + * a gets multiplied by 2^-52 (0x3cb0000000000000). + * a =3D 1.0, result =3D 1.0 * 2^-52 =3D 0x3cb0000000000000 + */ + check64(do_dfmpyfix(DF_one, DF_denorm), 0x3CB0000000000000ULL); + + /* + * Case: a is denormal AND b is normal with exp >=3D 512. + * a gets multiplied by 2^52 (0x4330000000000000). + * a =3D smallest denorm =3D 2^-1074, b =3D 2^512 (biased exp 0x5ff). + * Result =3D 2^-1074 * 2^52 =3D 2^-1022 =3D smallest normal + * =3D 0x0010000000000000 + */ + check64(do_dfmpyfix(DF_denorm, 0x5FF0000000000000ULL), + 0x0010000000000000ULL); +} + int main() { check_compare_exception(); @@ -725,6 +895,11 @@ int main() check_float2int_convs(); check_float_consts(); check_dfmpyxx(); + check_sfclass(); + check_dfclass(); + check_conv_uw2df(); + check_conv_ud2df(); + check_dfmpyfix(); =20 puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301431598158500 Test the interleave/deinterleave 64-bit bit-manipulation instructions and the cround instruction. Reviewed-by: Sid Manning Signed-off-by: Brian Cain --- tests/tcg/hexagon/test_bitops.c | 98 +++++++++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 1 + 2 files changed, 99 insertions(+) create mode 100644 tests/tcg/hexagon/test_bitops.c diff --git a/tests/tcg/hexagon/test_bitops.c b/tests/tcg/hexagon/test_bitop= s.c new file mode 100644 index 00000000000..3e9274ddddd --- /dev/null +++ b/tests/tcg/hexagon/test_bitops.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * Test bit interleave/deinterleave and convergent rounding. + */ + +#include +#include +#include + +int err; + +#include "hex_test.h" + +static void check_interleave(void) +{ + uint64_t input; + uint64_t inter; + uint64_t deinter; + + /* + * interleave takes the 32 even bits and 32 odd bits of Rss and + * interleaves them: even[0] goes to bit 0, odd[0] to bit 1, + * even[1] to bit 2, odd[1] to bit 3, etc. + * + * Input: low 32 bits (even half), high 32 bits (odd half) + * If low =3D 0xFFFFFFFF, high =3D 0x00000000: + * result has every even bit set, every odd bit clear + * =3D 0x5555555555555555 + */ + input =3D 0x00000000FFFFFFFFULL; + inter =3D Q6_P_interleave_P(input); + check64(inter, 0x5555555555555555ULL); + + /* All ones should stay all ones */ + input =3D 0xFFFFFFFFFFFFFFFFULL; + inter =3D Q6_P_interleave_P(input); + check64(inter, 0xFFFFFFFFFFFFFFFFULL); + + /* All zeros should stay all zeros */ + input =3D 0x0000000000000000ULL; + inter =3D Q6_P_interleave_P(input); + check64(inter, 0x0000000000000000ULL); + + /* + * deinterleave is the inverse of interleave. + * deinterleave(interleave(x)) should equal x. + */ + input =3D 0xDEADBEEFCAFEBABEULL; + inter =3D Q6_P_interleave_P(input); + deinter =3D Q6_P_deinterleave_P(inter); + check64(deinter, input); + + /* deinterleave of 0x5555...5555 -> low half all 1s, high half all 0s = */ + deinter =3D Q6_P_deinterleave_P(0x5555555555555555ULL); + check64(deinter, 0x00000000FFFFFFFFULL); +} + +static void check_cround(void) +{ + /* + * cround(0x300, #8) -> 3 (exact shift, no rounding needed). + * 0x300 >> 8 =3D 3 + */ + check32(Q6_R_cround_RI(0x300, 8), 3); + + /* + * cround(0x380, #8) -> 4 (0x380 >> 8 =3D 3.5, rounds to even =3D 4) + */ + check32(Q6_R_cround_RI(0x380, 8), 4); + + /* + * cround(0x280, #8) -> 2 (0x280 >> 8 =3D 2.5, rounds to even =3D 2) + */ + check32(Q6_R_cround_RI(0x280, 8), 2); + + /* + * cround(0x3C0, #8) -> 4 (0x3C0 >> 8 =3D 3.75, rounds up to 4) + */ + check32(Q6_R_cround_RI(0x3C0, 8), 4); + + /* + * Shift by 0 -> return the input unchanged. + */ + check32(Q6_R_cround_RI(42, 0), 42); +} + +int main(void) +{ + check_interleave(); + check_cround(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index e3017db24f6..6935d02802b 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -69,6 +69,7 @@ tests +=3D { 'test_abs.S': {'cflags': asmflags}, 'test_bitcnt.S': {'cflags': asmflags}, 'test_bitsplit.S': {'cflags': asmflags}, + 'test_bitops.c': {'cflags': cflags}, 'test_call.S': {'cflags': asmflags}, 'test_clobber.S': {'cflags': asmflags}, 'test_cmp.S': {'cflags': asmflags}, --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301503; cv=none; d=zohomail.com; s=zohoarc; b=n4798i1GMe0GfoDWwi1VKZaa2Cxn5d9UvQr+Kk55b5mWVNChxP6q0pWONQvxORZ5+KZ61Fv8u/cfHc1yNRgD7MtNR2SN5rlj7q63Iqh1wLDJWlNycHiOJTphrx6D9++vvRTou7WBdOxgEqJ3DSyzjb/RC16UX4mfkArQzOijNH0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301503; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZmTWwZziOYKDbt2ajhZeMa2nbLon8EGk5fjBjl75l0Q=; b=IAyLCVgvtwP+rpt5J4SqQlAtVZKjIn9H/8oPdf+Zer4GHPsS5blL/tVOJ99+1zOa6y560HwuT5WZgY6aMAlv0b0ZK5/sK9EC8CkymDIHc6y9k+PjpEF3BN3TeXY0OL9p2bkOCROjX8okFFuXOiYJqjvCc9hZG50Eu7eC1Fe9WEA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790301503893895.505941764537; Thu, 24 Sep 2026 18:58:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9v9a-00059m-M4; Thu, 24 Sep 2026 21:55:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9W-00050p-Kk for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:06 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9U-00065G-KR for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:06 -0400 Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1lQCP3753101 for ; Fri, 25 Sep 2026 01:55:03 GMT Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw5q8tcnj-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 01:55:03 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-33310847fcaso651620eec.1 for ; Thu, 24 Sep 2026 18:55:03 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301505850158500 Test conditional callr, compound tstbit0-and-jump instructions and endloop01. These exercise previously uncovered branch paths in translate.c. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/test_cond_branch.c | 162 +++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 1 + 2 files changed, 163 insertions(+) create mode 100644 tests/tcg/hexagon/test_cond_branch.c diff --git a/tests/tcg/hexagon/test_cond_branch.c b/tests/tcg/hexagon/test_= cond_branch.c new file mode 100644 index 00000000000..73be8fbb43c --- /dev/null +++ b/tests/tcg/hexagon/test_cond_branch.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * Test conditional calls, compound testbit0-and-jump instructions, + * and endloop01 (dual hardware loop end). + */ + +#include +#include + +int err; + +#include "hex_test.h" + +/* Target function for conditional calls */ +static int call_target_val; + +__attribute__((noinline)) +static void call_target(void) +{ + call_target_val =3D 42; +} + +/* + * Test conditional call: if (Pu) callr Rs / if (!Pu) callr Rs + */ +static void check_cond_call(void) +{ + void (*fn)(void) =3D call_target; + + /* + * callr clobbers all caller-saved registers. + * Hexagon caller-saved: r0-r5, r14-r15, r28, p0-p3. + */ + + /* if (p0) callr Rs -- predicate true */ + call_target_val =3D 0; + asm volatile("p0 =3D cmp.eq(%[one], %[one])\n\t" /* p0 =3D true */ + "if (p0) callr %[fn]\n\t" + : + : [one] "r"(1), [fn] "r"(fn) + : "r0", "r1", "r2", "r3", "r4", "r5", + "r14", "r15", "r28", "r31", + "p0", "p1", "p2", "p3", "memory"); + check32(call_target_val, 42); + + /* if (!p0) callr Rs -- predicate true, so !p0 is false */ + call_target_val =3D 0; + asm volatile("p0 =3D cmp.eq(%[one], %[one])\n\t" /* p0 =3D true */ + "if (!p0) callr %[fn]\n\t" + : + : [one] "r"(1), [fn] "r"(fn) + : "r0", "r1", "r2", "r3", "r4", "r5", + "r14", "r15", "r28", "r31", + "p0", "p1", "p2", "p3", "memory"); + check32(call_target_val, 0); + + /* if (!p0) callr Rs -- predicate false, so !p0 is true */ + call_target_val =3D 0; + asm volatile("p0 =3D cmp.eq(%[a], %[b])\n\t" /* p0 =3D false (1 !=3D = 2) */ + "if (!p0) callr %[fn]\n\t" + : + : [a] "r"(1), [b] "r"(2), [fn] "r"(fn) + : "r0", "r1", "r2", "r3", "r4", "r5", + "r14", "r15", "r28", "r31", + "p0", "p1", "p2", "p3", "memory"); + check32(call_target_val, 42); +} + +/* + * Test compound testbit0-and-jump. + * p0 =3D tstbit(Rs, #0); if ([!]p0.new) jump:t/nt target + */ +static void check_tstbit0_jump(void) +{ + uint32_t result; + + /* Rs has bit0 =3D 1, test "if (p0.new) jump" -> should jump */ + result =3D 0; + asm volatile( + "{\n\t" + " p0 =3D tstbit(%[val], #0)\n\t" + " if (p0.new) jump:t 1f\n\t" + "}\n\t" + "%[res] =3D #0\n\t" + "jump 2f\n\t" + "1:\n\t" + "%[res] =3D #1\n\t" + "2:\n\t" + : [res] "=3Dr"(result) + : [val] "r"(0x5) /* bit 0 is set */ + : "p0"); + check32(result, 1); + + /* Rs has bit0 =3D 0, test "if (p0.new) jump" -> should NOT jump */ + result =3D 0; + asm volatile( + "{\n\t" + " p0 =3D tstbit(%[val], #0)\n\t" + " if (p0.new) jump:t 1f\n\t" + "}\n\t" + "%[res] =3D #0\n\t" + "jump 2f\n\t" + "1:\n\t" + "%[res] =3D #1\n\t" + "2:\n\t" + : [res] "=3Dr"(result) + : [val] "r"(0x4) /* bit 0 is clear */ + : "p0"); + check32(result, 0); + + /* Rs has bit0 =3D 0, test "if (!p0.new) jump" -> should jump */ + result =3D 0; + asm volatile( + "{\n\t" + " p0 =3D tstbit(%[val], #0)\n\t" + " if (!p0.new) jump:t 1f\n\t" + "}\n\t" + "%[res] =3D #0\n\t" + "jump 2f\n\t" + "1:\n\t" + "%[res] =3D #1\n\t" + "2:\n\t" + : [res] "=3Dr"(result) + : [val] "r"(0x4) /* bit 0 is clear */ + : "p0"); + check32(result, 1); +} + +/* + * Test endloop01: a packet that terminates both loop0 and loop1. + * Outer loop runs 3 iterations, inner loop runs 4. + */ +static void check_endloop01(void) +{ + uint32_t count; + + asm volatile( + "%[cnt] =3D #0\n\t" + "loop1(1f, #3)\n\t" /* outer loop: 3 iterations */ + "1:\n\t" + "loop0(2f, #4)\n\t" /* inner loop: 4 iterations */ + "2:\n\t" + "{ %[cnt] =3D add(%[cnt], #1) }:endloop01\n\t" + : [cnt] "=3Dr"(count)); + + /* 3 outer * 4 inner =3D 12 total iterations */ + check32(count, 12); +} + +int main(void) +{ + check_cond_call(); + check_tstbit0_jump(); + check_endloop01(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index 6935d02802b..6074e56f6d6 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -73,6 +73,7 @@ tests +=3D { 'test_call.S': {'cflags': asmflags}, 'test_clobber.S': {'cflags': asmflags}, 'test_cmp.S': {'cflags': asmflags}, + 'test_cond_branch.c': {'cflags': cflags}, 'test_dotnew.S': {'cflags': asmflags}, 'test_ext.S': {'cflags': asmflags}, 'test_fibonacci.S': {'cflags': asmflags}, --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301334; cv=none; d=zohomail.com; s=zohoarc; b=FtijF9QNiRyK5Yk6OMjlqUfgAVsWqctgGHJN/lVIa7oC/owFUcv8OdCSOskGbaU7xi0BuEPI6qq5Xa3NcLt8amSV5CY/1HvL04THdNoMo1QcJN1IIMPvwcQgOcSJ6qXHzu0tO2kYKUoJX2TuXIUziWWY32VWyd7yGHQdsiGGpv8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301334; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aV+mAcO8jRn0u+WfEX2FJKrucWSrrnbTCO2zRkrEfqQ=; b=NFpnTZpf8EsXED/Iq+FU2JiPAI4Thm3i1e/towCHw2ex6FlS+VTRbGj7U23YvfAX6LJrzMF/5IAOKGJRm1yR8DeHOC65uyprVDkPJVxQRtTEjWfOsCNcWwn/3eF6ZQI+FdLCDdwNALP9dbSVX1dKFPLXFj1I4GF2j7Nj4PTFF64= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790301334326731.2212474194272; Thu, 24 Sep 2026 18:55:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9v9b-0005AA-40; Thu, 24 Sep 2026 21:55:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9Y-00053x-C8 for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:08 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9W-00065Q-5R for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:07 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1kVVt4051919 for ; Fri, 25 Sep 2026 01:55:04 GMT Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw898skgk-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 01:55:04 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-32861f5448cso1379729eec.0 for ; Thu, 24 Sep 2026 18:55:04 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301336064158500 Test the dczeroa instruction which zeroes a cache line. Verifies aligned, unaligned, and buffer-start addresses. Reviewed-by: Sid Manning Signed-off-by: Brian Cain --- tests/tcg/hexagon/test_dczeroa.c | 88 ++++++++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 1 + 2 files changed, 89 insertions(+) create mode 100644 tests/tcg/hexagon/test_dczeroa.c diff --git a/tests/tcg/hexagon/test_dczeroa.c b/tests/tcg/hexagon/test_dcze= roa.c new file mode 100644 index 00000000000..8cdcdd6a3b5 --- /dev/null +++ b/tests/tcg/hexagon/test_dczeroa.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * Test the dczeroa instruction, which zeroes a 32-byte cache line. + * The address is rounded down to a 32-byte boundary: (addr & ~0x1f). + */ + +#include +#include +#include +#include + +int err; + +#include "hex_test.h" + +static uint8_t buf[128] __attribute__((aligned(32))); + +/* dczeroa with an aligned address */ +static void test_dczeroa_aligned(void) +{ + int i; + + memset(buf, 0xff, sizeof(buf)); + + Q6_dczeroa_A(&buf[32]); + + for (i =3D 0; i < 32; i++) { + check32(buf[i], 0xff); + } + for (i =3D 32; i < 64; i++) { + check32(buf[i], 0x00); + } + for (i =3D 64; i < 96; i++) { + check32(buf[i], 0xff); + } +} + +/* dczeroa with an unaligned address (should round down) */ +static void test_dczeroa_unaligned(void) +{ + int i; + + memset(buf, 0xff, sizeof(buf)); + + /* Address buf+40 rounds down to buf+32 */ + Q6_dczeroa_A(&buf[40]); + + for (i =3D 0; i < 32; i++) { + check32(buf[i], 0xff); + } + for (i =3D 32; i < 64; i++) { + check32(buf[i], 0x00); + } + for (i =3D 64; i < 96; i++) { + check32(buf[i], 0xff); + } +} + +/* dczeroa at the start of the buffer */ +static void test_dczeroa_start(void) +{ + int i; + + memset(buf, 0xff, sizeof(buf)); + + Q6_dczeroa_A(&buf[0]); + + for (i =3D 0; i < 32; i++) { + check32(buf[i], 0x00); + } + for (i =3D 32; i < 64; i++) { + check32(buf[i], 0xff); + } +} + +int main(void) +{ + test_dczeroa_aligned(); + test_dczeroa_unaligned(); + test_dczeroa_start(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index 6074e56f6d6..ff3c095d9cb 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -74,6 +74,7 @@ tests +=3D { 'test_clobber.S': {'cflags': asmflags}, 'test_cmp.S': {'cflags': asmflags}, 'test_cond_branch.c': {'cflags': cflags}, + 'test_dczeroa.c': {'cflags': cflags}, 'test_dotnew.S': {'cflags': asmflags}, 'test_ext.S': {'cflags': asmflags}, 'test_fibonacci.S': {'cflags': asmflags}, --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301532; cv=none; d=zohomail.com; s=zohoarc; b=EGawtQEAU/bDEXBMI243UnLaJ9EMUrtV+4CBDjstQ927MiOokJ9RFX7g1Q51vfud0L+8xnoPYUq4pOJDFb3U0KUifZisbTtOA/KhYBKOy2k/Ts0q+qTHQBGgXFuVDZ2mD9avkwTYc0UceGJEU7Vl86hdkJxdAs1dgkOlItSAHXU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301532; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=naYdC83VyBWhzB6bL8+5hMjuy6+3mjCFqYt+5UPPSi0=; b=nMueF0AW6N8F9qht8ky9c4jMUKsUhxO+yWWilygTzP6XScJhJgOTu0K6jTsuCasLoZxGJKzYU3wux9g43WGRMHMP/qzWIo+9KKDzjNmyv4k9Yy6JhiDBSoZPVu3F3yXoioZs8FV2p3+C7f65qQCmHRFQFVTzeRZvcb+MfjoPFOI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17903015324701022.1262473551309; Thu, 24 Sep 2026 18:58:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9v9r-0005CC-AH; Thu, 24 Sep 2026 21:55:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9a-00059i-J6 for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:10 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9Y-00065f-8F for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:10 -0400 Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1l34m3186961 for ; Fri, 25 Sep 2026 01:55:07 GMT Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw1t7ucpm-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 01:55:06 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-3412efc2661so500175eec.1 for ; Thu, 24 Sep 2026 18:55:06 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301533948158500 Test all eight vwhist instruction variants and the four Q-masked forms. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/hex_test.h | 10 + tests/tcg/hexagon/test_vwhist.c | 345 ++++++++++++++++++++++++++++++++ tests/tcg/hexagon/meson.build | 1 + 3 files changed, 356 insertions(+) create mode 100644 tests/tcg/hexagon/test_vwhist.c diff --git a/tests/tcg/hexagon/hex_test.h b/tests/tcg/hexagon/hex_test.h index f86e6e1a69e..9315fe463a1 100644 --- a/tests/tcg/hexagon/hex_test.h +++ b/tests/tcg/hexagon/hex_test.h @@ -21,6 +21,16 @@ =20 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) =20 +static inline void __check16(int line, uint16_t val, uint16_t expect) +{ + if (val !=3D expect) { + printf("ERROR at line %d: 0x%04x !=3D 0x%04x\n", line, val, expect= ); + err++; + } +} + +#define check16(RES, EXP) __check16(__LINE__, RES, EXP) + static inline void __check32(int line, uint32_t val, uint32_t expect) { if (val !=3D expect) { diff --git a/tests/tcg/hexagon/test_vwhist.c b/tests/tcg/hexagon/test_vwhis= t.c new file mode 100644 index 00000000000..32dedb0a8b9 --- /dev/null +++ b/tests/tcg/hexagon/test_vwhist.c @@ -0,0 +1,345 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * Test HVX weighted histogram instructions (vwhist128/vwhist256 variants). + * + * Each halfword in the input vector (loaded via Vx.tmp) contains a bucket + * index (low byte) and a weight (high byte). The instruction accumulates + * the weight into the appropriate element of the destination vector. + */ + +#include +#include +#include + +int err; + +#include "hex_test.h" + +#define MAX_VEC_SIZE_BYTES 128 + +typedef union { + uint32_t uw[MAX_VEC_SIZE_BYTES / 4]; + uint16_t uh[MAX_VEC_SIZE_BYTES / 2]; + uint8_t ub[MAX_VEC_SIZE_BYTES]; +} MMVector; + +/* + * Build input vector for vwhist256: each halfword is (weight << 8 | bucke= t). + * We put bucket=3D0, weight=3D1 in every slot so that v0.uh[0] gets incre= mented + * by 1 for each of the 64 halfwords -> v0.uh[0] should equal 64. + */ +static MMVector input __attribute__((aligned(MAX_VEC_SIZE_BYTES))); +static MMVector zero_vec __attribute__((aligned(MAX_VEC_SIZE_BYTES))); +static MMVector result __attribute__((aligned(MAX_VEC_SIZE_BYTES))); + +/* + * Test vwhist256: 256-bin histogram with 16-bit accumulation. + * Each halfword of the input: low byte =3D bucket, high byte =3D weight. + * bucket bits [7:3] -> vindex (which vector register), [2:0] + lane -> el= ement. + * All entries have bucket=3D0 weight=3D1, so v0.uh[0..7] get incremented. + */ +static void test_vwhist256(void) +{ + int i; + + /* Set all input halfwords to bucket=3D0, weight=3D1 */ + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + /* Zero out v0 (the target for bucket 0) */ + "v0 =3D vmem(%[zero] + #0)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist256\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result) + : "v0", "v12", "memory"); + + /* + * 64 input halfwords all targeting bucket 0. + * elindex =3D (i & ~7) | (bucket & 7) =3D i & ~7 (since bucket=3D0). + * So elements 0,8,16,24,32,40,48,56 each get 8 increments. + */ + for (i =3D 0; i < 64; i++) { + uint16_t expected =3D ((i & 7) =3D=3D 0) ? 8 : 0; + check16(result.uh[i], expected); + } +} + +/* + * Test vwhist256:sat -- saturating variant. + * Use weight=3D0xFF to test that saturation to 0xFFFF works. + */ +static void test_vwhist256_sat(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0xFF00; /* weight=3D0xFF, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist256:sat\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result) + : "v0", "v12", "memory"); + + /* + * Same distribution as vwhist256: elements 0,8,16,...,56. + * Each gets 8 * 0xFF =3D 2040 =3D 0x7F8 (within uint16 range). + */ + for (i =3D 0; i < 64; i++) { + uint16_t expected =3D ((i & 7) =3D=3D 0) ? 8 * 0xFF : 0; + check16(result.uh[i], expected); + } +} + +/* + * Test vwhist128: 128-bin histogram with 32-bit accumulation. + * bucket bits [7:3] -> vindex, [2:1] + lane -> element (word granularity). + */ +static void test_vwhist128(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist128\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result) + : "v0", "v12", "memory"); + + /* + * 128-bin: 64 halfwords all targeting bucket 0. + * bucket 0 -> vindex=3D0, elindex based on (i>>1)&(~3) | (bucket>>1)&= 3. + * With bucket=3D0, elindex =3D (i>>1)&(~3). + * For i=3D0,1: elindex=3D0; i=3D2,3: elindex=3D0; ... up to i=3D6,7: = elindex=3D0 + * i ranges 0..63. (i>>1) ranges 0..31. + * (i>>1)&(~3) =3D 0,0,0,0,4,4,4,4,8,... + * So elements 0,4,8,12,16,20,24,28 each get 8 increments. + */ + for (i =3D 0; i < 32; i++) { + uint32_t expected =3D ((i & 3) =3D=3D 0) ? 8 : 0; + check32(result.uw[i], expected); + } +} + +/* + * Test vwhist128(#0) -- masked variant. + * Only processes elements where (bucket & 1) =3D=3D mode. + */ +static void test_vwhist128m(void) +{ + int i; + + /* All bucket=3D0, weight=3D1. bucket&1=3D=3D0, so mode=3D0 matches a= ll. */ + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist128(#0)\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result) + : "v0", "v12", "memory"); + + /* Same distribution as vwhist128 since all buckets have bit0=3D0 */ + for (i =3D 0; i < 32; i++) { + uint32_t expected =3D ((i & 3) =3D=3D 0) ? 8 : 0; + check32(result.uw[i], expected); + } + + /* Now test with mode=3D1: bucket=3D0 has bit0=3D0, so nothing should = match */ + memset(&result, 0, sizeof(result)); + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist128(#1)\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result) + : "v0", "v12", "memory"); + + for (i =3D 0; i < 32; i++) { + check32(result.uw[i], 0); + } +} + +static MMVector ones_vec __attribute__((aligned(MAX_VEC_SIZE_BYTES))); + +/* + * Test vwhist256(Qv4) -- Q-masked vwhist256. + * Set Q0 to all-ones so all elements pass the mask -> same as vwhist256. + */ +static void test_vwhist256q(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "v1 =3D vmem(%[ones] + #0)\n\t" + "q0 =3D vcmp.eq(v1.b, v1.b)\n\t" /* all-ones Q0 */ + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist256(q0)\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result), [ones] "r"(&ones_vec) + : "v0", "v1", "v12", "q0", "memory"); + + for (i =3D 0; i < 64; i++) { + uint16_t expected =3D ((i & 7) =3D=3D 0) ? 8 : 0; + check16(result.uh[i], expected); + } +} + +/* + * Test vwhist256(Qv4):sat -- Q-masked saturating vwhist256. + */ +static void test_vwhist256q_sat(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0xFF00; /* weight=3D0xFF, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "v1 =3D vmem(%[ones] + #0)\n\t" + "q0 =3D vcmp.eq(v1.b, v1.b)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist256(q0):sat\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result), [ones] "r"(&ones_vec) + : "v0", "v1", "v12", "q0", "memory"); + + for (i =3D 0; i < 64; i++) { + uint16_t expected =3D ((i & 7) =3D=3D 0) ? 8 * 0xFF : 0; + check16(result.uh[i], expected); + } +} + +/* + * Test vwhist128(Qv4) -- Q-masked vwhist128. + */ +static void test_vwhist128q(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "v1 =3D vmem(%[ones] + #0)\n\t" + "q0 =3D vcmp.eq(v1.b, v1.b)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist128(q0)\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result), [ones] "r"(&ones_vec) + : "v0", "v1", "v12", "q0", "memory"); + + for (i =3D 0; i < 32; i++) { + uint32_t expected =3D ((i & 3) =3D=3D 0) ? 8 : 0; + check32(result.uw[i], expected); + } +} + +/* + * Test vwhist128(Qv4,#0) -- Q-masked mode vwhist128. + */ +static void test_vwhist128qm(void) +{ + int i; + + for (i =3D 0; i < MAX_VEC_SIZE_BYTES / 2; i++) { + input.uh[i] =3D 0x0100; /* weight=3D1, bucket=3D0 */ + } + + asm volatile( + "v0 =3D vmem(%[zero] + #0)\n\t" + "v1 =3D vmem(%[ones] + #0)\n\t" + "q0 =3D vcmp.eq(v1.b, v1.b)\n\t" + "{\n\t" + " v12.tmp =3D vmem(%[inp] + #0)\n\t" + " vwhist128(q0,#0)\n\t" + "}\n\t" + "vmem(%[out] + #0) =3D v0\n\t" + : + : [inp] "r"(&input), [zero] "r"(&zero_vec), + [out] "r"(&result), [ones] "r"(&ones_vec) + : "v0", "v1", "v12", "q0", "memory"); + + /* bucket=3D0, bit0=3D0, mode=3D0 matches -> same as vwhist128 */ + for (i =3D 0; i < 32; i++) { + uint32_t expected =3D ((i & 3) =3D=3D 0) ? 8 : 0; + check32(result.uw[i], expected); + } +} + +int main(void) +{ + memset(&zero_vec, 0, sizeof(zero_vec)); + memset(&ones_vec, 0xff, sizeof(ones_vec)); + + test_vwhist256(); + test_vwhist256_sat(); + test_vwhist128(); + test_vwhist128m(); + test_vwhist256q(); + test_vwhist256q_sat(); + test_vwhist128q(); + test_vwhist128qm(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/meson.build b/tests/tcg/hexagon/meson.build index ff3c095d9cb..1cffc63e091 100644 --- a/tests/tcg/hexagon/meson.build +++ b/tests/tcg/hexagon/meson.build @@ -94,6 +94,7 @@ tests +=3D { 'test_vminh.S': {'cflags': asmflags}, 'test_vpmpyh.S': {'cflags': asmflags}, 'test_vspliceb.S': {'cflags': asmflags}, + 'test_vwhist.c': {'cflags': [cflags, '-mhvx']}, 'unaligned_pc.c': {'cflags': cflags}, 'unaligned_data.c': {'cflags': cflags}, 'usr.c': { --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301383; cv=none; d=zohomail.com; s=zohoarc; b=fixJpmfawmJLhqMgtsOtAiur6tBga8rX8RX0JVqMHT/mVUgeVfIogRN3I/PhjhcJqbHCa+eAy9zZaauH02641fUXvm0wfmEpDqM+SBIMREWagoTz6rW8iLiuqMsGiOxBku3WKzo+gPc9VcOiYfTo4ceVrMww66WX5hGi6xF5bfY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301383; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hqfVicHy6v894bNbcDZGGKOJEk5tlT9bKuiAy6xrO9Q=; b=HyEc7FTH7kCryxqx+C25Z98y6F96A1yx6IE+tRJR0T0EkcGI2ZRXheFNyzQjHL7BZCgnRbbB2SK5Q1tFXvQ4nMShDdLr1/dsRRC55haVn73ql8BfNxDodKNRgydkp3eXmrgBY9Rni2Iqo3cVxqEBduMgnAijofDbiZTQAmaEVR4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790301383811490.5035069605111; Thu, 24 Sep 2026 18:56:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9v9z-0005Ea-12; Thu, 24 Sep 2026 21:55:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9l-0005BU-Ir for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:23 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9v9i-00065l-8l for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:20 -0400 Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1keH54132626 for ; Fri, 25 Sep 2026 01:55:07 GMT Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw881sjvx-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 01:55:07 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-334f782d1abso1523821eec.0 for ; Thu, 24 Sep 2026 18:55:07 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301385657158500 Add edge case tests for the sfrecipa instruction Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/fpstuff.c | 81 +++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index 7561f31cdc3..f82262ab4ac 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -345,6 +345,86 @@ static void check_sfrecipa(void) check32(pred, 0x80); } =20 +/* + * Helper to run sfrecipa and capture result + USR. + */ +static void do_sfrecipa(uint32_t Rs, uint32_t Rt, + uint32_t *Rd, uint32_t *usr_out) +{ + uint32_t rd, usr; + + asm volatile(CLEAR_FPSTATUS + "%[rd],p0 =3D sfrecipa(%[Rs], %[Rt])\n\t" + "%[usr] =3D usr\n\t" + : [rd] "=3Dr"(rd), [usr] "=3Dr"(usr) + : [Rs] "r"(Rs), [Rt] "r"(Rt) + : "p0", "r2", "usr"); + *Rd =3D rd; + *usr_out =3D usr; +} + +/* + * Additional sfrecipa edge cases: + * - inf/inf, 0/0 -> NaN + invalid + * - normal/inf, 0/normal, inf/normal + * - denominator with extreme biased exponents + */ +static void check_sfrecipa_edges(void) +{ + uint32_t rd, usr; + + /* inf / inf -> invalid */ + do_sfrecipa(SF_INF, SF_INF, &rd, &usr); + check_fpstatus(usr, USR_FPINVF); + + /* -inf / +inf -> invalid */ + do_sfrecipa(0xff800000, SF_INF, &rd, &usr); + check_fpstatus(usr, USR_FPINVF); + + /* 0 / 0 -> invalid */ + do_sfrecipa(SF_zero, SF_zero, &rd, &usr); + check_fpstatus(usr, USR_FPINVF); + + /* -0 / +0 -> invalid */ + do_sfrecipa(SF_zero_neg, SF_zero, &rd, &usr); + check_fpstatus(usr, USR_FPINVF); + + /* normal / inf -> fixup (Rd =3D 1.0) */ + do_sfrecipa(SF_one, SF_INF, &rd, &usr); + check32(rd, SF_one); + + do_sfrecipa(SF_two, SF_INF, &rd, &usr); + check32(rd, SF_one); + + /* 0 / normal -> fixup (Rd =3D 1.0) */ + do_sfrecipa(SF_zero, SF_one, &rd, &usr); + check32(rd, SF_one); + + do_sfrecipa(SF_zero_neg, SF_two, &rd, &usr); + check32(rd, SF_one); + + /* inf / normal -> fixup (Rd =3D 1.0) */ + do_sfrecipa(SF_INF, SF_one, &rd, &usr); + check32(rd, SF_one); + + do_sfrecipa(0xff800000, SF_two, &rd, &usr); + check32(rd, SF_one); + + /* + * Denominator with biased exponent <=3D 1. + * Rs: biased exp 26, Rt: biased exp 1. + */ + do_sfrecipa(26U << 23, 1U << 23, &rd, &usr); + check32_ne(rd, 0); + + /* + * Denominator with biased exponent > 252. + * Both: biased exp 253. + */ + do_sfrecipa(253U << 23, 253U << 23, &rd, &usr); + check32_ne(rd, 0); +} + static void check_canonical_NaN(void) { uint32_t sf_result; @@ -887,6 +967,7 @@ int main() check_sfminmax(); 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Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/fpstuff.c | 57 +++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index f82262ab4ac..0f28a218d84 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -935,6 +935,16 @@ static uint64_t do_dfmpyfix(uint64_t a, uint64_t b) return result; } =20 +static uint64_t do_dfmpyhh(uint64_t a, uint64_t b, uint64_t acc) +{ + uint64_t result =3D acc; + + asm("%[res] +=3D dfmpyhh(%[a], %[b])\n\t" + : [res] "+r"(result) + : [a] "r"(a), [b] "r"(b)); + return result; +} + static void check_dfmpyfix(void) { /* @@ -961,6 +971,52 @@ static void check_dfmpyfix(void) 0x0010000000000000ULL); } =20 +/* + * Test dfmpyhh (double-precision FP multiply high*high and accumulate): + * - normal inputs + * - denormal inputs (crushed to inexact zero) + * - zero/NaN/infinity inputs + * - nonzero accumulator + */ +static inline uint64_t df_abs(uint64_t v) { return v & 0x7FFFFFFFFFFFFFFFU= LL; } +static inline uint64_t df_exp(uint64_t v) { return v & 0x7FF0000000000000U= LL; } +static inline uint64_t df_mant(uint64_t v) { return v & 0x000FFFFFFFFFFFFF= ULL; } + +static void check_dfmpyhh(void) +{ + uint64_t result; + + /* Normal * normal: 1.0 * 1.0 + 0 -> nonzero finite */ + result =3D do_dfmpyhh(DF_one, DF_one, 0ULL); + check64_ne(df_abs(result), 0ULL); + + /* Denormal input a: crushed to zero */ + result =3D do_dfmpyhh(0x0008000000000000ULL, DF_one, 0ULL); + check64(df_abs(result), 0ULL); + + /* Denormal input b: crushed to zero */ + result =3D do_dfmpyhh(DF_one, 0x0008000000000000ULL, 0ULL); + check64(df_abs(result), 0ULL); + + /* Zero input: early exit */ + result =3D do_dfmpyhh(DF_zero, DF_one, 0ULL); + check64(df_abs(result), 0ULL); + + /* Infinity input: early exit, result contains inf */ + result =3D do_dfmpyhh(0x7FF0000000000000ULL, DF_one, 0ULL); + check64(df_exp(result), 0x7FF0000000000000ULL); + + /* NaN input: early exit, result is NaN */ + result =3D do_dfmpyhh(DF_QNaN, DF_one, 0ULL); + check64(df_exp(result), 0x7FF0000000000000ULL); + check64_ne(df_mant(result), 0ULL); + + /* Nonzero accumulator: nonzero finite result */ + result =3D do_dfmpyhh(DF_one, DF_one, DF_one); + check64_ne(df_abs(result), 0ULL); + check64_ne(df_exp(result), 0x7FF0000000000000ULL); +} + int main() { check_compare_exception(); @@ -981,6 +1037,7 @@ int main() check_conv_uw2df(); check_conv_ud2df(); check_dfmpyfix(); + check_dfmpyhh(); =20 puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301628321158500 Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/misc.c | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index ca22bb79f7b..c07547b6f68 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -404,6 +404,48 @@ void test_dpmpyss_rnd_s0(void) check32(dpmpyss_rnd_s0(0x7fffffff, 0x7fffffff), 0x3fffffff); } =20 +static uint8_t storeimm_byte_array[16]; +static uint16_t storeimm_half_array[16]; +static uint32_t storeimm_word_array[16]; + +/* + * Unconditional store-immediate instructions (S4_storeir*_io). + * The predicated forms are tested above; these exercise the base encoding + * with positive and negative #S8 immediate values. + */ +static void check_store_imm(void) +{ + /* memb(Rs+#u6:0) =3D #S8 */ + memset(storeimm_byte_array, 0, sizeof(storeimm_byte_array)); + asm volatile("memb(%[ptr] + #0) =3D #0x12\n\t" + : : [ptr] "r"(storeimm_byte_array) : "memory"); + check32(storeimm_byte_array[0], 0x12); + + asm volatile("memb(%[ptr] + #3) =3D #-1\n\t" + : : [ptr] "r"(storeimm_byte_array) : "memory"); + check32(storeimm_byte_array[3], 0xff); + + /* memh(Rs+#u6:1) =3D #S8 */ + memset(storeimm_half_array, 0, sizeof(storeimm_half_array)); + asm volatile("memh(%[ptr] + #0) =3D #0x34\n\t" + : : [ptr] "r"(storeimm_half_array) : "memory"); + check32(storeimm_half_array[0], 0x34); + + asm volatile("memh(%[ptr] + #4) =3D #-1\n\t" + : : [ptr] "r"(storeimm_half_array) : "memory"); + check32(storeimm_half_array[2], 0xffff); + + /* memw(Rs+#u6:2) =3D #S8 */ + memset(storeimm_word_array, 0, sizeof(storeimm_word_array)); + asm volatile("memw(%[ptr] + #0) =3D #0x56\n\t" + : : [ptr] "r"(storeimm_word_array) : "memory"); + check32(storeimm_word_array[0], 0x56); + + asm volatile("memw(%[ptr] + #8) =3D #-1\n\t" + : : [ptr] "r"(storeimm_word_array) : "memory"); + check32(storeimm_word_array[2], 0xffffffff); +} + int main() { int32_t res; @@ -547,6 +589,8 @@ int main() =20 test_dpmpyss_rnd_s0(); =20 + check_store_imm(); + puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301431563158500 Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/misc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index c07547b6f68..abb34ab6a65 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -446,6 +446,31 @@ static void check_store_imm(void) check32(storeimm_word_array[2], 0xffffffff); } =20 +/* + * Rd =3D Ps -- transfer predicate register to general register. + * The result is 0x00 or 0xff depending on the predicate value. + */ +static void check_preg_transfer(void) +{ + uint32_t result; + + /* Set p0 =3D true, then Rd =3D p0 should give 0xff */ + asm volatile("p0 =3D cmp.eq(%[val], %[val])\n\t" + "%[res] =3D p0\n\t" + : [res] "=3Dr"(result) + : [val] "r"(1) + : "p0"); + check32(result, 0xff); + + /* Set p0 =3D false, then Rd =3D p0 should give 0x00 */ + asm volatile("p0 =3D cmp.eq(%[a], %[b])\n\t" + "%[res] =3D p0\n\t" + : [res] "=3Dr"(result) + : [a] "r"(1), [b] "r"(2) + : "p0"); + check32(result, 0x00); +} + int main() { int32_t res; @@ -590,6 +615,7 @@ int main() test_dpmpyss_rnd_s0(); =20 check_store_imm(); + check_preg_transfer(); =20 puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301449621158500 Add round-to-nearest float-to-int conversion tests for the non-:chop varian= ts, sfmpy:lib with Inf-Inf to verify exception suppression, and sfinvsqrta with a denormal input. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/fpstuff.c | 99 +++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index 0f28a218d84..9ea79c617d9 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -1017,6 +1017,102 @@ static void check_dfmpyhh(void) check64_ne(df_exp(result), 0x7FF0000000000000ULL); } =20 +/* + * Round-to-nearest float-to-int conversions with normal values. + * These test the non-:chop variants which use the USR rounding mode. + */ +static void check_conv_rnd(void) +{ + uint32_t res32; + uint64_t res64; + + /* convert_sf2w(1.5) rounds to nearest-even =3D 2 */ + asm(CLEAR_FPSTATUS + "%[res] =3D convert_sf2w(%[val])\n\t" + : [res] "=3Dr"(res32) + : [val] "r"(0x3fc00000) /* 1.5f */ + : "r2", "usr"); + check32(res32, 2); + + /* convert_sf2d(1.5) =3D 2 */ + asm(CLEAR_FPSTATUS + "%[res] =3D convert_sf2d(%[val])\n\t" + : [res] "=3Dr"(res64) + : [val] "r"(0x3fc00000) /* 1.5f */ + : "r2", "usr"); + check64(res64, 2ULL); + + /* convert_df2w(1.5) =3D 2 */ + asm(CLEAR_FPSTATUS + "%[res] =3D convert_df2w(%[val])\n\t" + : [res] "=3Dr"(res32) + : [val] "r"(0x3FF8000000000000ULL) /* 1.5 */ + : "r2", "usr"); + check32(res32, 2); + + /* convert_df2d(1.5) =3D 2 */ + asm(CLEAR_FPSTATUS + "%[res] =3D convert_df2d(%[val])\n\t" + : [res] "=3Dr"(res64) + : [val] "r"(0x3FF8000000000000ULL) /* 1.5 */ + : "r2", "usr"); + check64(res64, 2ULL); +} + +/* + * Test sfmpy:lib with Inf-Inf. + * + * Rx +=3D sfmpy(Rs, Rt):lib with Rx =3D -Inf, Rs*Rt -> +Inf + * Inf - Inf is invalid, but the :lib variant suppresses the + * exception and returns zero. + */ +static void check_sffma_lib_inf(void) +{ + uint32_t result; + + /* +Inf +=3D sfmpy(+Inf, 1.0):lib -> Inf (no exception, normal) */ + result =3D SF_INF; + asm(CLEAR_FPSTATUS + "%[res] +=3D sfmpy(%[a], %[b]):lib\n\t" + : [res] "+r"(result) + : [a] "r"(SF_INF), [b] "r"(SF_one) + : "r2", "usr"); + check32(result, SF_INF); + + /* + * -Inf +=3D sfmpy(+Inf, 1.0):lib -> Inf - Inf =3D invalid + * The :lib variant should return zero for Inf - Inf. + */ + result =3D SF_INF | (1u << 31); /* -Inf */ + asm(CLEAR_FPSTATUS + "%[res] +=3D sfmpy(%[a], %[b]):lib\n\t" + : [res] "+r"(result) + : [a] "r"(SF_INF), [b] "r"(SF_one) + : "r2", "usr"); + check32(result, 0); +} + +/* + * Test sfinvsqrta with a denormal input. + */ +static void check_invsqrta_denorm(void) +{ + uint32_t result; + uint32_t predval; + uint32_t exp_bits; + + /* Denormal positive float: 0x00400000 (small denorm) */ + asm volatile("%[res],p0 =3D sfinvsqrta(%[val])\n\t" + "%[pred] =3D p0\n\t" + : [res] "=3Dr"(result), [pred] "=3Dr"(predval) + : [val] "r"(SF_denorm) + : "p0"); + /* Result should be a valid float (not NaN/zero) */ + check32_ne(result, 0); + exp_bits =3D (result >> 23) & 0xff; + check32_ne(exp_bits, 0xff); /* not Inf/NaN */ +} + int main() { check_compare_exception(); @@ -1038,6 +1134,9 @@ int main() check_conv_ud2df(); check_dfmpyfix(); check_dfmpyhh(); + check_conv_rnd(); + check_sffma_lib_inf(); + check_invsqrta_denorm(); =20 puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301622278158500 Test a packet with both a scalar store and an HVX store, and test a non-inverted masked store (if (q0) vmem) to verify the invert=3Dfalse path in masked store generation. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/hvx_misc.c | 66 ++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c index f20afc8e670..0285886c2a5 100644 --- a/tests/tcg/hexagon/hvx_misc.c +++ b/tests/tcg/hexagon/hvx_misc.c @@ -566,6 +566,69 @@ void test_store_new() check_output_w(__LINE__, 1); } =20 +/* + * Test a packet with both a scalar store and an HVX store. + */ +static uint32_t scalar_store_dst; + +static void test_scalar_hvx_store(void) +{ + scalar_store_dst =3D 0; + memset(&expect[0], 0, sizeof(MMVector)); + + /* Fill v0 with 0xABCD pattern */ + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D 0xABCDABCD; + } + + asm("r0 =3D #0xABCDABCD\n\t" + "v0 =3D vsplat(r0)\n\t" + "r1 =3D #42\n\t" + "{\n\t" + " memw(%[scalar]) =3D r1\n\t" + " vmem(%[hvx]) =3D v0\n\t" + "}\n\t" + : + : [scalar] "r"(&scalar_store_dst), + [hvx] "r"(&output[0]) + : "r0", "r1", "v0", "memory"); + + check_output_w(__LINE__, 1); + if (scalar_store_dst !=3D 42) { + printf("ERROR at line %d: scalar_store_dst =3D %d, expected 42\n", + __LINE__, scalar_store_dst); + err++; + } +} + +/* + * Test non-inverted masked store: if (Qv) vmem(Rt) =3D Vs. + * Existing tests only cover the inverted form (!Qv). + * Use an all-true Q predicate to unconditionally store. + */ +static void test_masked_store_noninvert(void) +{ + void *p0 =3D buffer0; + void *pout =3D output; + + memset(&output[0], 0xff, sizeof(MMVector)); + + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + expect[0].uw[i] =3D buffer0[0].uw[i]; + } + + asm("v5 =3D vmem(%[src] + #0)\n\t" + "r0 =3D #-1\n\t" + "v6 =3D vsplat(r0)\n\t" + "q0 =3D vand(v6, r0)\n\t" + "if (q0) vmem(%[dst]) =3D v5\n\t" + : + : [src] "r"(p0), [dst] "r"(pout) + : "r0", "v5", "v6", "q0", "memory"); + + check_output_w(__LINE__, 1); +} + int main() { init_buffers(); @@ -615,6 +678,9 @@ int main() =20 test_store_new(); =20 + test_scalar_hvx_store(); + test_masked_store_noninvert(); + puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301614250158500 Add a decbin test vector exercising the MPS case Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/misc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index abb34ab6a65..08845201b59 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -599,6 +599,15 @@ int main() res64 =3D decbin(0xfLL, 0x1bLL, &pred); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301857348158500 target/hexagon is about to address its HVX register file through a runtime base pointer rather than a constant offset from env, in order to share one register file between several vCPUs. The gvec ops it needs have no base-parameterized form yet. Split tcg_gen_gvec_{and,or,xor,andc,orc,not,abs,smin,umin,smax,umax} the same way tcg_gen_gvec_{add,sub,mov,dup_imm} already are: the work moves to a _var function taking a TCGv_ptr base per operand, and the existing entry point becomes a wrapper passing tcg_env. The aofs =3D=3D bofs shortcuts also have to compare the bases, since equal offsets into different objects are not the same operand. Reviewed-by: Marco Liebel Reviewed-by: Richard Henderson Signed-off-by: Brian Cain --- include/tcg/tcg-op-gvec-common.h | 45 ++++++++ tcg/tcg-op-gvec.c | 184 ++++++++++++++++++++++++------- 2 files changed, 189 insertions(+), 40 deletions(-) diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-com= mon.h index ea0c87f4db6..99a6685e8a5 100644 --- a/include/tcg/tcg-op-gvec-common.h +++ b/include/tcg/tcg-op-gvec-common.h @@ -287,6 +287,13 @@ void tcg_gen_gvec_mov_var(unsigned vece, TCGv_ptr dbas= e, uint32_t dofs, TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, uint32_t maxsz); =20 +void tcg_gen_gvec_not_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_abs_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -335,6 +342,23 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, = uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 /* Min/max. */ +void tcg_gen_gvec_smin_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_umin_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_smax_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_umax_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -344,6 +368,27 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, u= int32_t aofs, void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 +void tcg_gen_gvec_and_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_or_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_xor_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_andc_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_orc_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 27f3807b004..191ac0fa864 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1911,8 +1911,9 @@ void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dof= s, uint32_t oprsz, tcg_gen_gvec_dup_imm_var(vece, tcg_env, dofs, oprsz, maxsz, x); } =20 -void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_not_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen2 g =3D { .fni8 =3D tcg_gen_not_i64, @@ -1920,7 +1921,13 @@ void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, = uint32_t aofs, .fno =3D gen_helper_gvec_not, .prefer_i64 =3D true, }; - tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g); + tcg_gen_gvec_2_var(dbase, dofs, abase, aofs, oprsz, maxsz, &g); +} + +void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_not_var(vece, tcg_env, dofs, tcg_env, aofs, oprsz, maxsz); } =20 /* Perform a vector addition using normal addition and a mask. The mask @@ -2427,8 +2434,10 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs= , uint32_t aofs, tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_smin_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_smin_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2452,11 +2461,21 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs= , uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_smin_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + +void tcg_gen_gvec_umin_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_umin_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2480,11 +2499,21 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs= , uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_umin_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + +void tcg_gen_gvec_smax_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_smax_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2508,11 +2537,21 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs= , uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_smax_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + +void tcg_gen_gvec_umax_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_umax_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2536,7 +2575,15 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs,= uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_umax_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); } =20 /* Perform a vector negation using normal negation and a mask. @@ -2645,8 +2692,9 @@ static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i6= 4 b) gen_absv_mask(d, b, MO_16); } =20 -void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_abs_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_abs_vec, 0 }; static const GVecGen2 g[4] =3D { @@ -2674,11 +2722,19 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs,= uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_2_var(dbase, dofs, abase, aofs, oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_abs_var(vece, tcg_env, dofs, tcg_env, aofs, oprsz, maxsz); +} + +void tcg_gen_gvec_and_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g =3D { .fni8 =3D tcg_gen_and_i64, @@ -2687,15 +2743,25 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs,= uint32_t aofs, .prefer_i64 =3D true, }; =20 - if (aofs =3D=3D bofs) { - tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + if (abase =3D=3D bbase && aofs =3D=3D bofs) { + tcg_gen_gvec_mov_var(vece, dbase, dofs, abase, aofs, oprsz, maxsz); } else { - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g); } } =20 -void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_and_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, + oprsz, maxsz); +} + +void tcg_gen_gvec_or_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g =3D { .fni8 =3D tcg_gen_or_i64, @@ -2704,15 +2770,25 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, = uint32_t aofs, .prefer_i64 =3D true, }; =20 - if (aofs =3D=3D bofs) { - tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + if (abase =3D=3D bbase && aofs =3D=3D bofs) { + tcg_gen_gvec_mov_var(vece, dbase, dofs, abase, aofs, oprsz, maxsz); } else { - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g); } } =20 -void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_or_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, + oprsz, maxsz); +} + +void tcg_gen_gvec_xor_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g =3D { .fni8 =3D tcg_gen_xor_i64, @@ -2721,15 +2797,25 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs,= uint32_t aofs, .prefer_i64 =3D true, }; =20 - if (aofs =3D=3D bofs) { - tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0); + if (abase =3D=3D bbase && aofs =3D=3D bofs) { + tcg_gen_gvec_dup_imm_var(MO_64, dbase, dofs, oprsz, maxsz, 0); } else { - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g); } } =20 -void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_xor_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, + oprsz, maxsz); +} + +void tcg_gen_gvec_andc_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g =3D { .fni8 =3D tcg_gen_andc_i64, @@ -2738,15 +2824,25 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs= , uint32_t aofs, .prefer_i64 =3D true, }; =20 - if (aofs =3D=3D bofs) { - tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0); + if (abase =3D=3D bbase && aofs =3D=3D bofs) { + tcg_gen_gvec_dup_imm_var(MO_64, dbase, dofs, oprsz, maxsz, 0); } else { - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g); } } =20 -void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_andc_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bof= s, + oprsz, maxsz); +} + +void tcg_gen_gvec_orc_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g =3D { .fni8 =3D tcg_gen_orc_i64, @@ -2755,13 +2851,21 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs,= uint32_t aofs, .prefer_i64 =3D true, }; =20 - if (aofs =3D=3D bofs) { - tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1); + if (abase =3D=3D bbase && aofs =3D=3D bofs) { + tcg_gen_gvec_dup_imm_var(MO_64, dbase, dofs, oprsz, maxsz, -1); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301381587158500 These three families still name tcg_env directly, so they cannot be reached from a _var entry point. Thread a TCGv_ptr base per operand through expand_2s_{i32,i64,vec}, expand_2sh_vec, expand_cmp_{i32,i64,vec} and do_gvec_shifts, and split expand_2i_ool out of tcg_gen_gvec_2i_ool the way expand_2_ool already is, so the out-of-line fallback is reachable too. Add tcg_gen_gvec_{2s,shls,shrs,sars,dup_i32,cmp}_var; the existing entry points become wrappers passing tcg_env and generate identical code. Note that the operand swap in tcg_gen_gvec_cmp_var, used when a condition has no helper, now has to swap the bases along with the offsets. Reviewed-by: Marco Liebel Reviewed-by: Richard Henderson Signed-off-by: Brian Cain --- include/tcg/tcg-op-gvec-common.h | 21 +++ tcg/tcg-op-gvec.c | 256 +++++++++++++++++++++---------- 2 files changed, 192 insertions(+), 85 deletions(-) diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-com= mon.h index 99a6685e8a5..fa28ebdde0f 100644 --- a/include/tcg/tcg-op-gvec-common.h +++ b/include/tcg/tcg-op-gvec-common.h @@ -237,6 +237,10 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, /* Similarly, expand (env+dofs) =3D op(env+aofs, c). */ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, int64_t c, const GVecGen2i *op); +/* Expand (dbase+dofs) =3D op(abase+aofs, s), length @oprsz. */ +void tcg_gen_gvec_2s_var(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, TCGv_i64 c, const GVecGen2s *op); /* Similarly, expand (env+dofs) =3D op(env+aofs, s). */ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, TCGv_i64 c, const GVecGen2s *op); @@ -433,6 +437,8 @@ void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs,= uint32_t s, =20 void tcg_gen_gvec_dup_imm_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, uint32_t oprsz, uint32_t maxsz, uint64_t imm= ); +void tcg_gen_gvec_dup_i32_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + uint32_t oprsz, uint32_t maxsz, TCGv_i32 in); =20 void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); @@ -445,6 +451,16 @@ void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, = uint32_t aofs, void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); =20 +void tcg_gen_gvec_shls_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrs_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sars_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -471,6 +487,11 @@ void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, = uint32_t aofs, void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 +void tcg_gen_gvec_cmp_var(TCGCond cond, unsigned vece, + TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 191ac0fa864..fc1a70434c5 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -162,23 +162,31 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, =20 /* Generate a call to a gvec-style helper with two vector operands and one scalar operand. */ +static void expand_2i_ool(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, TCGv_i64 c, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_2i *fn) +{ + TCGv_ptr a0, a1; + TCGv_i32 desc =3D tcg_constant_i32(simd_desc(oprsz, maxsz, data)); + + a0 =3D tcg_temp_ebb_new_ptr(); + a1 =3D tcg_temp_ebb_new_ptr(); + + tcg_gen_addi_ptr(a0, dbase, dofs); + tcg_gen_addi_ptr(a1, abase, aofs); + + fn(a0, a1, c, desc); + + tcg_temp_free_ptr(a0); + tcg_temp_free_ptr(a1); +} + void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz, int32_t data, gen_helper_gvec_2i *fn) { - TCGv_ptr a0, a1; - TCGv_i32 desc =3D tcg_constant_i32(simd_desc(oprsz, maxsz, data)); - - a0 =3D tcg_temp_ebb_new_ptr(); - a1 =3D tcg_temp_ebb_new_ptr(); - - tcg_gen_addi_ptr(a0, tcg_env, dofs); - tcg_gen_addi_ptr(a1, tcg_env, aofs); - - fn(a0, a1, c, desc); - - tcg_temp_free_ptr(a0); - tcg_temp_free_ptr(a1); + expand_2i_ool(tcg_env, dofs, tcg_env, aofs, c, oprsz, maxsz, data, fn); } =20 /* Generate a call to a gvec-style helper with three vector operands. */ @@ -783,7 +791,8 @@ static void expand_2i_i32(uint32_t dofs, uint32_t aofs,= uint32_t oprsz, tcg_temp_free_i32(t1); } =20 -static void expand_2s_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, +static void expand_2s_i32(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, TCGv_i32 c, bool scalar_first, void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -792,13 +801,13 @@ static void expand_2s_i32(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, tcg_env, aofs + i); + tcg_gen_ld_i32(t0, abase, aofs + i); if (scalar_first) { fni(t1, c, t0); } else { fni(t1, t0, c); } - tcg_gen_st_i32(t1, tcg_env, dofs + i); + tcg_gen_st_i32(t1, dbase, dofs + i); } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -949,7 +958,8 @@ static void expand_2i_i64(uint32_t dofs, uint32_t aofs,= uint32_t oprsz, tcg_temp_free_i64(t1); } =20 -static void expand_2s_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, +static void expand_2s_i64(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, TCGv_i64 c, bool scalar_first, void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -958,13 +968,13 @@ static void expand_2s_i64(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, tcg_env, aofs + i); + tcg_gen_ld_i64(t0, abase, aofs + i); if (scalar_first) { fni(t1, c, t0); } else { fni(t1, t0, c); } - tcg_gen_st_i64(t1, tcg_env, dofs + i); + tcg_gen_st_i64(t1, dbase, dofs + i); } tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -1114,7 +1124,8 @@ static void expand_2i_vec(unsigned vece, uint32_t dof= s, uint32_t aofs, } } =20 -static void expand_2s_vec(unsigned vece, uint32_t dofs, uint32_t aofs, +static void expand_2s_vec(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, uint32_t tysz, TCGType type, TCGv_vec c, bool scalar_first, void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_v= ec)) @@ -1123,13 +1134,13 @@ static void expand_2s_vec(unsigned vece, uint32_t d= ofs, uint32_t aofs, TCGv_vec t0 =3D tcg_temp_new_vec(type); TCGv_vec t1 =3D tcg_temp_new_vec(type); =20 - tcg_gen_ld_vec(t0, tcg_env, aofs + i); + tcg_gen_ld_vec(t0, abase, aofs + i); if (scalar_first) { fni(vece, t1, c, t0); } else { fni(vece, t1, t0, c); } - tcg_gen_st_vec(t1, tcg_env, dofs + i); + tcg_gen_st_vec(t1, dbase, dofs + i); } } =20 @@ -1375,14 +1386,18 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, } } =20 -/* Expand a vector operation with two vectors and a scalar. */ -void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, - uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g) +/* + * Expand a vector operation with two vectors and a scalar, + * (dbase+dofs) =3D op(abase+aofs, c). + */ +void tcg_gen_gvec_2s_var(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g) { TCGType type; =20 check_size_align(oprsz, maxsz, dofs | aofs); - check_overlap_2(tcg_env, dofs, tcg_env, aofs, maxsz); + check_overlap_2(dbase, dofs, abase, aofs, maxsz); =20 type =3D 0; if (g->fniv) { @@ -1403,7 +1418,8 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. */ some =3D QEMU_ALIGN_DOWN(oprsz, 32); - expand_2s_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, + expand_2s_vec(g->vece, dbase, dofs, abase, aofs, + some, 32, TCG_TYPE_V256, t_vec, g->scalar_first, g->fniv); if (some =3D=3D oprsz) { break; @@ -1415,12 +1431,14 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, /* fallthru */ =20 case TCG_TYPE_V128: - expand_2s_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, + expand_2s_vec(g->vece, dbase, dofs, abase, aofs, + oprsz, 16, TCG_TYPE_V128, t_vec, g->scalar_first, g->fniv); break; =20 case TCG_TYPE_V64: - expand_2s_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, + expand_2s_vec(g->vece, dbase, dofs, abase, aofs, + oprsz, 8, TCG_TYPE_V64, t_vec, g->scalar_first, g->fniv); break; =20 @@ -1433,25 +1451,33 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, TCGv_i64 t64 =3D tcg_temp_new_i64(); =20 tcg_gen_dup_i64(g->vece, t64, c); - expand_2s_i64(dofs, aofs, oprsz, t64, g->scalar_first, g->fni8); + expand_2s_i64(dbase, dofs, abase, aofs, oprsz, t64, + g->scalar_first, g->fni8); tcg_temp_free_i64(t64); } else if (g->fni4 && check_size_impl(oprsz, 4)) { TCGv_i32 t32 =3D tcg_temp_new_i32(); =20 tcg_gen_extrl_i64_i32(t32, c); tcg_gen_dup_i32(g->vece, t32, t32); - expand_2s_i32(dofs, aofs, oprsz, t32, g->scalar_first, g->fni4); + expand_2s_i32(dbase, dofs, abase, aofs, oprsz, t32, + g->scalar_first, g->fni4); tcg_temp_free_i32(t32); } else { - tcg_gen_gvec_2i_ool(dofs, aofs, c, oprsz, maxsz, 0, g->fno); + expand_2i_ool(dbase, dofs, abase, aofs, c, oprsz, maxsz, 0, g->fno= ); return; } =20 if (oprsz < maxsz) { - expand_clr(tcg_env, dofs + oprsz, maxsz - oprsz); + expand_clr(dbase, dofs + oprsz, maxsz - oprsz); } } =20 +void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g) +{ + tcg_gen_gvec_2s_var(tcg_env, dofs, tcg_env, aofs, oprsz, maxsz, c, g); +} + /* Expand a vector three-operand operation. */ void tcg_gen_gvec_3_var(TCGv_ptr dbase, uint32_t dofs, TCGv_ptr abase, uint32_t aofs, @@ -1775,12 +1801,18 @@ void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs,= uint32_t aofs, tcg_gen_gvec_mov_var(vece, tcg_env, dofs, tcg_env, aofs, oprsz, maxsz); } =20 +void tcg_gen_gvec_dup_i32_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + uint32_t oprsz, uint32_t maxsz, TCGv_i32 in) +{ + check_size_align(oprsz, maxsz, dofs); + tcg_debug_assert(vece <=3D MO_32); + do_dup(vece, dbase, dofs, oprsz, maxsz, in, NULL, 0); +} + void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz, uint32_t maxsz, TCGv_i32 in) { - check_size_align(oprsz, maxsz, dofs); - tcg_debug_assert(vece <=3D MO_32); - do_dup(vece, tcg_env, dofs, oprsz, maxsz, in, NULL, 0); + tcg_gen_gvec_dup_i32_var(vece, tcg_env, dofs, oprsz, maxsz, in); } =20 void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz, @@ -3311,7 +3343,8 @@ typedef struct { TCGOpcode v_list[2]; } GVecGen2sh; =20 -static void expand_2sh_vec(unsigned vece, uint32_t dofs, uint32_t aofs, +static void expand_2sh_vec(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, uint32_t tysz, TCGType type, TCGv_i32 shift, void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_= i32)) @@ -3320,21 +3353,22 @@ static void expand_2sh_vec(unsigned vece, uint32_t = dofs, uint32_t aofs, TCGv_vec t0 =3D tcg_temp_new_vec(type); TCGv_vec t1 =3D tcg_temp_new_vec(type); =20 - tcg_gen_ld_vec(t0, tcg_env, aofs + i); + tcg_gen_ld_vec(t0, abase, aofs + i); fni(vece, t1, t0, shift); - tcg_gen_st_vec(t1, tcg_env, dofs + i); + tcg_gen_st_vec(t1, dbase, dofs + i); } } =20 static void -do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, +do_gvec_shifts(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g) { TCGType type; uint32_t some; =20 check_size_align(oprsz, maxsz, dofs | aofs); - check_overlap_2(tcg_env, dofs, tcg_env, aofs, maxsz); + check_overlap_2(dbase, dofs, abase, aofs, maxsz); =20 /* If the backend has a scalar expansion, great. */ type =3D choose_vector_type(g->s_list, vece, oprsz, vece =3D=3D MO_64); @@ -3343,7 +3377,7 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t= aofs, TCGv_i32 shift, switch (type) { case TCG_TYPE_V256: some =3D QEMU_ALIGN_DOWN(oprsz, 32); - expand_2sh_vec(vece, dofs, aofs, some, 32, + expand_2sh_vec(vece, dbase, dofs, abase, aofs, some, 32, TCG_TYPE_V256, shift, g->fniv_s); if (some =3D=3D oprsz) { break; @@ -3354,11 +3388,11 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32= _t aofs, TCGv_i32 shift, maxsz -=3D some; /* fallthru */ case TCG_TYPE_V128: - expand_2sh_vec(vece, dofs, aofs, oprsz, 16, + expand_2sh_vec(vece, dbase, dofs, abase, aofs, oprsz, 16, TCG_TYPE_V128, shift, g->fniv_s); break; case TCG_TYPE_V64: - expand_2sh_vec(vece, dofs, aofs, oprsz, 8, + expand_2sh_vec(vece, dbase, dofs, abase, aofs, oprsz, 8, TCG_TYPE_V64, shift, g->fniv_s); break; default: @@ -3386,7 +3420,8 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t= aofs, TCGv_i32 shift, switch (type) { case TCG_TYPE_V256: some =3D QEMU_ALIGN_DOWN(oprsz, 32); - expand_2s_vec(vece, dofs, aofs, some, 32, TCG_TYPE_V256, + expand_2s_vec(vece, dbase, dofs, abase, aofs, + some, 32, TCG_TYPE_V256, v_shift, false, g->fniv_v); if (some =3D=3D oprsz) { break; @@ -3397,11 +3432,13 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32= _t aofs, TCGv_i32 shift, maxsz -=3D some; /* fallthru */ case TCG_TYPE_V128: - expand_2s_vec(vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, + expand_2s_vec(vece, dbase, dofs, abase, aofs, + oprsz, 16, TCG_TYPE_V128, v_shift, false, g->fniv_v); break; case TCG_TYPE_V64: - expand_2s_vec(vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, + expand_2s_vec(vece, dbase, dofs, abase, aofs, + oprsz, 8, TCG_TYPE_V64, v_shift, false, g->fniv_v); break; default: @@ -3414,11 +3451,13 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32= _t aofs, TCGv_i32 shift, =20 /* Otherwise fall back to integral... */ if (vece =3D=3D MO_32 && check_size_impl(oprsz, 4)) { - expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4); + expand_2s_i32(dbase, dofs, abase, aofs, oprsz, shift, + false, g->fni4); } else if (vece =3D=3D MO_64 && check_size_impl(oprsz, 8)) { TCGv_i64 sh64 =3D tcg_temp_ebb_new_i64(); tcg_gen_extu_i32_i64(sh64, shift); - expand_2s_i64(dofs, aofs, oprsz, sh64, false, g->fni8); + expand_2s_i64(dbase, dofs, abase, aofs, oprsz, sh64, + false, g->fni8); tcg_temp_free_i64(sh64); } else { TCGv_ptr a0 =3D tcg_temp_ebb_new_ptr(); @@ -3427,8 +3466,8 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t= aofs, TCGv_i32 shift, =20 tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT); tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0)); - tcg_gen_addi_ptr(a0, tcg_env, dofs); - tcg_gen_addi_ptr(a1, tcg_env, aofs); + tcg_gen_addi_ptr(a0, dbase, dofs); + tcg_gen_addi_ptr(a1, abase, aofs); =20 g->fno[vece](a0, a1, desc); =20 @@ -3440,12 +3479,13 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32= _t aofs, TCGv_i32 shift, =20 clear_tail: if (oprsz < maxsz) { - expand_clr(tcg_env, dofs + oprsz, maxsz - oprsz); + expand_clr(dbase, dofs + oprsz, maxsz - oprsz); } } =20 -void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_shls_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) { static const GVecGen2sh g =3D { .fni4 =3D tcg_gen_shl_i32, @@ -3463,11 +3503,19 @@ void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs= , uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); + do_gvec_shifts(vece, dbase, dofs, abase, aofs, shift, oprsz, maxsz, &g= ); } =20 -void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_shls_var(vece, tcg_env, dofs, tcg_env, aofs, + shift, oprsz, maxsz); +} + +void tcg_gen_gvec_shrs_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) { static const GVecGen2sh g =3D { .fni4 =3D tcg_gen_shr_i32, @@ -3485,11 +3533,19 @@ void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs= , uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); + do_gvec_shifts(vece, dbase, dofs, abase, aofs, shift, oprsz, maxsz, &g= ); } =20 -void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_shrs_var(vece, tcg_env, dofs, tcg_env, aofs, + shift, oprsz, maxsz); +} + +void tcg_gen_gvec_sars_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) { static const GVecGen2sh g =3D { .fni4 =3D tcg_gen_sar_i32, @@ -3507,7 +3563,14 @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs,= uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); + do_gvec_shifts(vece, dbase, dofs, abase, aofs, shift, oprsz, maxsz, &g= ); +} + +void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_sars_var(vece, tcg_env, dofs, tcg_env, aofs, + shift, oprsz, maxsz); } =20 void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -3529,7 +3592,8 @@ void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs,= uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); + do_gvec_shifts(vece, tcg_env, dofs, tcg_env, aofs, shift, + oprsz, maxsz, &g); } =20 void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -3861,7 +3925,9 @@ void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs,= uint32_t aofs, } =20 /* Expand OPSZ bytes worth of three-operand operations using i32 elements.= */ -static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, +static void expand_cmp_i32(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, uint32_t oprsz, TCGCond cond) { TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); @@ -3869,16 +3935,18 @@ static void expand_cmp_i32(uint32_t dofs, uint32_t = aofs, uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, tcg_env, aofs + i); - tcg_gen_ld_i32(t1, tcg_env, bofs + i); + tcg_gen_ld_i32(t0, abase, aofs + i); + tcg_gen_ld_i32(t1, bbase, bofs + i); tcg_gen_negsetcond_i32(cond, t0, t0, t1); - tcg_gen_st_i32(t0, tcg_env, dofs + i); + tcg_gen_st_i32(t0, dbase, dofs + i); } tcg_temp_free_i32(t1); tcg_temp_free_i32(t0); } =20 -static void expand_cmp_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, +static void expand_cmp_i64(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, uint32_t oprsz, TCGCond cond) { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); @@ -3886,17 +3954,19 @@ static void expand_cmp_i64(uint32_t dofs, uint32_t = aofs, uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, tcg_env, aofs + i); - tcg_gen_ld_i64(t1, tcg_env, bofs + i); + tcg_gen_ld_i64(t0, abase, aofs + i); + tcg_gen_ld_i64(t1, bbase, bofs + i); tcg_gen_negsetcond_i64(cond, t0, t0, t1); - tcg_gen_st_i64(t0, tcg_env, dofs + i); + tcg_gen_st_i64(t0, dbase, dofs + i); } tcg_temp_free_i64(t1); tcg_temp_free_i64(t0); } =20 -static void expand_cmp_vec(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t tysz, +static void expand_cmp_vec(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t tysz, TCGType type, TCGCond cond) { for (uint32_t i =3D 0; i < oprsz; i +=3D tysz) { @@ -3904,16 +3974,18 @@ static void expand_cmp_vec(unsigned vece, uint32_t = dofs, uint32_t aofs, TCGv_vec t1 =3D tcg_temp_new_vec(type); TCGv_vec t2 =3D tcg_temp_new_vec(type); =20 - tcg_gen_ld_vec(t0, tcg_env, aofs + i); - tcg_gen_ld_vec(t1, tcg_env, bofs + i); + tcg_gen_ld_vec(t0, abase, aofs + i); + tcg_gen_ld_vec(t1, bbase, bofs + i); tcg_gen_cmp_vec(cond, vece, t2, t0, t1); - tcg_gen_st_vec(t2, tcg_env, dofs + i); + tcg_gen_st_vec(t2, dbase, dofs + i); } } =20 -void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, - uint32_t aofs, uint32_t bofs, - uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_cmp_var(TCGCond cond, unsigned vece, + TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode cmp_list[] =3D { INDEX_op_cmp_vec, 0 }; static gen_helper_gvec_3 * const eq_fn[4] =3D { @@ -3954,10 +4026,10 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, uint32_t some; =20 check_size_align(oprsz, maxsz, dofs | aofs | bofs); - check_overlap_3(tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, maxsz); + check_overlap_3(dbase, dofs, abase, aofs, bbase, bofs, maxsz); =20 if (cond =3D=3D TCG_COND_NEVER || cond =3D=3D TCG_COND_ALWAYS) { - do_dup(MO_8, tcg_env, dofs, oprsz, maxsz, + do_dup(MO_8, dbase, dofs, oprsz, maxsz, NULL, NULL, -(cond =3D=3D TCG_COND_ALWAYS)); return; } @@ -3975,7 +4047,8 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, ui= nt32_t dofs, * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. */ some =3D QEMU_ALIGN_DOWN(oprsz, 32); - expand_cmp_vec(vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, co= nd); + expand_cmp_vec(vece, dbase, dofs, abase, aofs, bbase, bofs, + some, 32, TCG_TYPE_V256, cond); if (some =3D=3D oprsz) { break; } @@ -3986,28 +4059,33 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, maxsz -=3D some; /* fallthru */ case TCG_TYPE_V128: - expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, c= ond); + expand_cmp_vec(vece, dbase, dofs, abase, aofs, bbase, bofs, + oprsz, 16, TCG_TYPE_V128, cond); break; case TCG_TYPE_V64: - expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, con= d); + expand_cmp_vec(vece, dbase, dofs, abase, aofs, bbase, bofs, + oprsz, 8, TCG_TYPE_V64, cond); break; =20 case 0: if (vece =3D=3D MO_64 && check_size_impl(oprsz, 8)) { - expand_cmp_i64(dofs, aofs, bofs, oprsz, cond); + expand_cmp_i64(dbase, dofs, abase, aofs, bbase, bofs, oprsz, c= ond); } else if (vece =3D=3D MO_32 && check_size_impl(oprsz, 4)) { - expand_cmp_i32(dofs, aofs, bofs, oprsz, cond); + expand_cmp_i32(dbase, dofs, abase, aofs, bbase, bofs, oprsz, c= ond); } else { gen_helper_gvec_3 * const *fn =3D fns[cond]; =20 if (fn =3D=3D NULL) { uint32_t tmp; + TCGv_ptr tmpb; tmp =3D aofs, aofs =3D bofs, bofs =3D tmp; + tmpb =3D abase, abase =3D bbase, bbase =3D tmpb; cond =3D tcg_swap_cond(cond); fn =3D fns[cond]; assert(fn !=3D NULL); } - tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn[vece]= ); + expand_3_ool(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, 0, fn[vece]); oprsz =3D maxsz; } break; @@ -4018,10 +4096,18 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { - expand_clr(tcg_env, dofs + oprsz, maxsz - oprsz); + expand_clr(dbase, dofs + oprsz, maxsz - oprsz); } } =20 +void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, + uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_cmp_var(cond, vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + static void expand_cmps_vec(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t tysz, TCGType type, TCGCond cond, TCGv_vec c) --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, OBFU_UNSUB_UL=1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301447579158500 target/hexagon is about to address its HVX register file through a runtime base pointer rather than a constant offset from env, in order to share one register file between several vCPUs. Split the other gvec op families it needs like tcg_gen_gvec_{add,sub,mov,and,etc}. Add tcg_gen_gvec_{ssadd,sssub,usadd,ussub,mul}_var and tcg_gen_gvec_{shri,sari}_var, plus the tcg_gen_gvec_2i_var plumbing the immediate-shift forms are built on. Reviewed-by: Marco Liebel Reviewed-by: Richard Henderson Signed-off-by: Brian Cain --- include/tcg/tcg-op-gvec-common.h | 31 ++++++ tcg/tcg-op-gvec.c | 177 ++++++++++++++++++++++--------- 2 files changed, 160 insertions(+), 48 deletions(-) diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-com= mon.h index fa28ebdde0f..6d3c2bae57a 100644 --- a/include/tcg/tcg-op-gvec-common.h +++ b/include/tcg/tcg-op-gvec-common.h @@ -234,6 +234,10 @@ void tcg_gen_gvec_2_var(TCGv_ptr dbase, uint32_t dofs, /* Similarly, expand (env+dofs) =3D op(env+aofs). */ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, const GVecGen2 *op); +/* Expand (dbase+dofs) =3D op(abase+aofs, c), clearing @oprsz..@maxsz. */ +void tcg_gen_gvec_2i_var(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, int64_t c, const GVecGen2i *op); /* Similarly, expand (env+dofs) =3D op(env+aofs, c). */ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, int64_t c, const GVecGen2i *op); @@ -315,6 +319,10 @@ void tcg_gen_gvec_sub_var(unsigned vece, TCGv_ptr dbas= e, uint32_t dofs, TCGv_ptr abase, uint32_t aofs, TCGv_ptr bbase, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_mul_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); @@ -336,6 +344,23 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, u= int32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); =20 /* Saturated arithmetic. */ +void tcg_gen_gvec_ssadd_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sssub_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_usadd_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_ussub_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -442,8 +467,14 @@ void tcg_gen_gvec_dup_i32_var(unsigned vece, TCGv_ptr = dbase, uint32_t dofs, =20 void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shri_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sari_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index fc1a70434c5..0d649cc13b2 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -771,7 +771,8 @@ static void expand_2_i32(TCGv_ptr dbase, uint32_t dofs,= TCGv_ptr abase, tcg_temp_free_i32(t1); } =20 -static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, +static void expand_2i_i32(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, int32_t c, bool load_dest, void (*fni)(TCGv_i32, TCGv_i32, int32_t)) { @@ -780,12 +781,12 @@ static void expand_2i_i32(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, tcg_env, aofs + i); + tcg_gen_ld_i32(t0, abase, aofs + i); if (load_dest) { - tcg_gen_ld_i32(t1, tcg_env, dofs + i); + tcg_gen_ld_i32(t1, dbase, dofs + i); } fni(t1, t0, c); - tcg_gen_st_i32(t1, tcg_env, dofs + i); + tcg_gen_st_i32(t1, dbase, dofs + i); } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -938,7 +939,8 @@ static void expand_2_i64(TCGv_ptr dbase, uint32_t dofs,= TCGv_ptr abase, tcg_temp_free_i64(t1); } =20 -static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, +static void expand_2i_i64(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, int64_t c, bool load_dest, void (*fni)(TCGv_i64, TCGv_i64, int64_t)) { @@ -947,12 +949,12 @@ static void expand_2i_i64(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, tcg_env, aofs + i); + tcg_gen_ld_i64(t0, abase, aofs + i); if (load_dest) { - tcg_gen_ld_i64(t1, tcg_env, dofs + i); + tcg_gen_ld_i64(t1, dbase, dofs + i); } fni(t1, t0, c); - tcg_gen_st_i64(t1, tcg_env, dofs + i); + tcg_gen_st_i64(t1, dbase, dofs + i); } tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -1106,7 +1108,8 @@ static void expand_2_vec(unsigned vece, TCGv_ptr dbas= e, uint32_t dofs, =20 /* Expand OPSZ bytes worth of two-vector operands and an immediate operand using host vectors. */ -static void expand_2i_vec(unsigned vece, uint32_t dofs, uint32_t aofs, +static void expand_2i_vec(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, uint32_t tysz, TCGType type, int64_t c, bool load_dest, void (*fni)(unsigned, TCGv_vec, TCGv_vec, int64_= t)) @@ -1115,12 +1118,12 @@ static void expand_2i_vec(unsigned vece, uint32_t d= ofs, uint32_t aofs, TCGv_vec t0 =3D tcg_temp_new_vec(type); TCGv_vec t1 =3D tcg_temp_new_vec(type); =20 - tcg_gen_ld_vec(t0, tcg_env, aofs + i); + tcg_gen_ld_vec(t0, abase, aofs + i); if (load_dest) { - tcg_gen_ld_vec(t1, tcg_env, dofs + i); + tcg_gen_ld_vec(t1, dbase, dofs + i); } fni(vece, t1, t0, c); - tcg_gen_st_vec(t1, tcg_env, dofs + i); + tcg_gen_st_vec(t1, dbase, dofs + i); } } =20 @@ -1318,8 +1321,9 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, } =20 /* Expand a vector operation with two vectors and an immediate. */ -void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, - uint32_t maxsz, int64_t c, const GVecGen2i *g) +void tcg_gen_gvec_2i_var(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, int64_t c, const GVecGen2i *g) { const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); @@ -1327,7 +1331,7 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, uint32_t some; =20 check_size_align(oprsz, maxsz, dofs | aofs); - check_overlap_2(tcg_env, dofs, tcg_env, aofs, maxsz); + check_overlap_2(dbase, dofs, abase, aofs, maxsz); =20 type =3D 0; if (g->fniv) { @@ -1340,8 +1344,8 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. */ some =3D QEMU_ALIGN_DOWN(oprsz, 32); - expand_2i_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, - c, g->load_dest, g->fniv); + expand_2i_vec(g->vece, dbase, dofs, abase, aofs, some, 32, + TCG_TYPE_V256, c, g->load_dest, g->fniv); if (some =3D=3D oprsz) { break; } @@ -1351,26 +1355,29 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, maxsz -=3D some; /* fallthru */ case TCG_TYPE_V128: - expand_2i_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, - c, g->load_dest, g->fniv); + expand_2i_vec(g->vece, dbase, dofs, abase, aofs, oprsz, 16, + TCG_TYPE_V128, c, g->load_dest, g->fniv); break; case TCG_TYPE_V64: - expand_2i_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, - c, g->load_dest, g->fniv); + expand_2i_vec(g->vece, dbase, dofs, abase, aofs, oprsz, 8, + TCG_TYPE_V64, c, g->load_dest, g->fniv); break; =20 case 0: if (g->fni8 && check_size_impl(oprsz, 8)) { - expand_2i_i64(dofs, aofs, oprsz, c, g->load_dest, g->fni8); + expand_2i_i64(dbase, dofs, abase, aofs, oprsz, c, + g->load_dest, g->fni8); } else if (g->fni4 && check_size_impl(oprsz, 4)) { - expand_2i_i32(dofs, aofs, oprsz, c, g->load_dest, g->fni4); + expand_2i_i32(dbase, dofs, abase, aofs, oprsz, c, + g->load_dest, g->fni4); } else { if (g->fno) { - tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno); + expand_2_ool(dbase, dofs, abase, aofs, oprsz, maxsz, + c, g->fno); } else { TCGv_i64 tcg_c =3D tcg_constant_i64(c); - tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz, - maxsz, c, g->fnoi); + expand_2i_ool(dbase, dofs, abase, aofs, tcg_c, oprsz, + maxsz, c, g->fnoi); } oprsz =3D maxsz; } @@ -1382,10 +1389,16 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { - expand_clr(tcg_env, dofs + oprsz, maxsz - oprsz); + expand_clr(dbase, dofs + oprsz, maxsz - oprsz); } } =20 +void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, int64_t c, const GVecGen2i *g) +{ + tcg_gen_gvec_2i_var(tcg_env, dofs, tcg_env, aofs, oprsz, maxsz, c, g); +} + /* * Expand a vector operation with two vectors and a scalar, * (dbase+dofs) =3D op(abase+aofs, c). @@ -2279,8 +2292,10 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, = uint32_t aofs, =20 static const TCGOpcode vecop_list_mul[] =3D { INDEX_op_mul_vec, 0 }; =20 -void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_mul_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_mul_vec, @@ -2305,7 +2320,15 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, = uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_mul_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, + oprsz, maxsz); } =20 void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -2344,8 +2367,10 @@ void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs,= uint32_t aofs, tcg_gen_gvec_muls(vece, dofs, aofs, tmp, oprsz, maxsz); } =20 -void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_ssadd_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_ssadd_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2367,11 +2392,21 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dof= s, uint32_t aofs, .vece =3D MO_64 }, }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_ssadd_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + +void tcg_gen_gvec_sssub_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_sssub_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2393,7 +2428,15 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs= , uint32_t aofs, .vece =3D MO_64 }, }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_sssub_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); } =20 static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) @@ -2410,8 +2453,10 @@ static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a= , TCGv_i64 b) tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d); } =20 -void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_usadd_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_usadd_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2435,11 +2480,21 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dof= s, uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_usadd_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + +void tcg_gen_gvec_ussub_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_ussub_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2463,7 +2518,15 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs= , uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_ussub_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); } =20 void tcg_gen_gvec_smin_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, @@ -3131,8 +3194,9 @@ void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, i= nt32_t c) tcg_gen_andi_i32(d, d, mask); } =20 -void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_shri_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_shri_vec, 0 }; static const GVecGen2i g[4] =3D { @@ -3162,12 +3226,20 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs= , uint32_t aofs, tcg_debug_assert(vece <=3D MO_64); tcg_debug_assert(shift >=3D 0 && shift < (8 << vece)); if (shift =3D=3D 0) { - tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + tcg_gen_gvec_mov_var(vece, dbase, dofs, abase, aofs, oprsz, maxsz); } else { - tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); + tcg_gen_gvec_2i_var(dbase, dofs, abase, aofs, oprsz, maxsz, + shift, &g[vece]); } } =20 +void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_shri_var(vece, tcg_env, dofs, tcg_env, aofs, + shift, oprsz, maxsz); +} + void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) { uint64_t s_mask =3D dup_const(MO_8, 0x80 >> c); @@ -3224,8 +3296,9 @@ void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, i= nt32_t c) tcg_temp_free_i32(s); } =20 -void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_sari_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_sari_vec, 0 }; static const GVecGen2i g[4] =3D { @@ -3255,12 +3328,20 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs= , uint32_t aofs, tcg_debug_assert(vece <=3D MO_64); tcg_debug_assert(shift >=3D 0 && shift < (8 << vece)); if (shift =3D=3D 0) { - tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + tcg_gen_gvec_mov_var(vece, dbase, dofs, abase, aofs, oprsz, maxsz); } else { - tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); + tcg_gen_gvec_2i_var(dbase, dofs, abase, aofs, oprsz, maxsz, + shift, &g[vece]); } } =20 +void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_sari_var(vece, tcg_env, dofs, tcg_env, aofs, + shift, oprsz, maxsz); +} + void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) { uint64_t mask =3D dup_const(MO_8, 0xff << c); --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301539922158500 SSR:XE gates access to the HVX coprocessor: executing an HVX instruction while it is clear must raise a precise exception with cause 0x16, NO_COPROC_ENABLE. Carry SSR:XE in a TB flag and emit the exception for the first HVX packet of a TB when the coprocessor is disabled. Reviewed-by: Marco Liebel Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 1 + target/hexagon/translate.h | 2 ++ target/hexagon/cpu.c | 2 ++ target/hexagon/translate.c | 11 +++++++++++ 4 files changed, 16 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index b1533680bd7..97f689fda22 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -207,6 +207,7 @@ struct ArchCPU { FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) FIELD(TB_FLAGS, MMU_INDEX, 1, 3) FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1) +FIELD(TB_FLAGS, HVX_COPROC_ENABLED, 5, 1) =20 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, uint32_t exception, diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index b90f7fff1c1..b33d5dbdbe8 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -98,6 +98,8 @@ typedef struct DisasContext { TCGv branch_taken; TCGv dczero_addr; bool pcycle_enabled; + bool hvx_coproc_enabled; + bool hvx_check_emitted; uint32_t num_cycles; } DisasContext; =20 diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index fad526ccfb5..19486e0f741 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -340,6 +340,8 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState = *cs) hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, cpu_mmu_index(env_cpu(env), false)); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1); + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED, + GET_SSR_FIELD(SSR_XE, env->t_sreg[HEX_SREG_SSR]= )); #else hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, MMU_USER_IDX); #endif diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 8561cec4e41..bf92166e0fd 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -766,6 +766,14 @@ static void gen_start_packet(DisasContext *ctx) i =3D find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + = 1); } } + +#ifndef CONFIG_USER_ONLY + if (ctx->pkt.pkt_has_hvx && !ctx->hvx_coproc_enabled && + !ctx->hvx_check_emitted) { + gen_precise_exception(HEX_CAUSE_NO_COPROC_ENABLE, ctx->pkt.pc); + ctx->hvx_check_emitted =3D true; + } +#endif } =20 bool is_gather_store_insn(DisasContext *ctx) @@ -1289,6 +1297,9 @@ static void hexagon_tr_init_disas_context(DisasContex= tBase *dcbase, #ifndef CONFIG_USER_ONLY ctx->num_cycles =3D 0; ctx->pcycle_enabled =3D FIELD_EX32(hex_flags, TB_FLAGS, PCYCLE_ENABLED= ); + ctx->hvx_coproc_enabled =3D + FIELD_EX32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED); + ctx->hvx_check_emitted =3D false; #endif } =20 --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301461; cv=none; d=zohomail.com; s=zohoarc; b=mKTgXnv6VeUcEyt6EezOn4vpW3zZ6D1vmLGoiG98yWBS94ZG0RFARX9kzpGIvQ/9oMK4K9DsXcEDVxEAmUcViKHTSUcXoqB3BSskmWcjUeaYKoXX/aA3bqZILcdE8Xxtf8qo00nQU+C34o9nT+SJ0guvE+ceKlcD+N2SOx/E8Jc= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301463802158500 Content-Type: text/plain; charset="utf-8" Prepare for system emulation modeling of HVX contexts, which are remapped at runtime. No functional change is intended, this is just refactoring. Reviewed-by: Richard Henderson Suggested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 5 + target/hexagon/gen_tcg_hvx.h | 608 +++++++++++++++++++--------------- target/hexagon/genptr.h | 8 + target/hexagon/mmvec/macros.h | 14 +- target/hexagon/translate.h | 6 +- target/hexagon/cpu.c | 13 +- target/hexagon/gdbstub.c | 16 +- target/hexagon/genptr.c | 102 +++--- target/hexagon/op_helper.c | 37 ++- target/hexagon/translate.c | 55 +-- target/hexagon/hex_common.py | 179 +++++----- 11 files changed, 597 insertions(+), 446 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 97f689fda22..965abe4f6d4 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -204,6 +204,11 @@ struct ArchCPU { #endif }; =20 +static inline CPUHexagonState *hex_hvx(CPUHexagonState *env) +{ + return env; +} + FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) FIELD(TB_FLAGS, MMU_INDEX, 1, 3) FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1) diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h index 2a342cdee69..f399291dc66 100644 --- a/target/hexagon/gen_tcg_hvx.h +++ b/target/hexagon/gen_tcg_hvx.h @@ -49,8 +49,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vhistq(tcg_env); \ @@ -65,8 +65,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vwhist256q(tcg_env); \ @@ -81,8 +81,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vwhist256q_sat(tcg_env); \ @@ -97,8 +97,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vwhist128q(tcg_env); \ @@ -114,8 +114,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ } else { \ TCGv tcgv_uiV =3D tcg_constant_tl(uiV); \ assert_vhist_tmp(ctx); \ @@ -125,19 +125,20 @@ static inline void assert_vhist_tmp(DisasContext *ctx) =20 =20 #define fGEN_TCG_V6_vassign(SHORTCODE) \ - tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vassign_tmp(SHORTCODE) \ - tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vcombine_tmp(SHORTCODE) \ do { \ - tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), VuV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, VvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off + sizeof(MMVector)= , \ + VuV_base, VuV_off, sizeof(MMVector), \ + sizeof(MMVector)); \ } while (0) =20 /* @@ -148,18 +149,20 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_V6_vcombine(SHORTCODE) \ do { \ if (VddV_off !=3D VuV_off) { \ - tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), VuV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, \ + VvV_off, sizeof(MMVector), sizeof(MMVecto= r)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, \ + VddV_off + sizeof(MMVector), VuV_base, \ + VuV_off, sizeof(MMVector), sizeof(MMVecto= r)); \ } else { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ - tcg_gen_gvec_mov(MO_64, tmpoff, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), tmpoff, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, tmpoff, VuV_base, VuV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, \ + VvV_off, sizeof(MMVector), sizeof(MMVecto= r)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, \ + VddV_off + sizeof(MMVector), tcg_env, tmp= off, \ + sizeof(MMVector), sizeof(MMVector)); \ } \ } while (0) =20 @@ -170,8 +173,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGLabel *false_label =3D gen_new_label(); \ tcg_gen_andi_tl(lsb, PsV, 1); \ tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \ - tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)); \ gen_set_label(false_label); \ } while (0) =20 @@ -186,231 +189,276 @@ static inline void assert_vhist_tmp(DisasContext *c= tx) =20 /* Vector add - various forms */ #define fGEN_TCG_V6_vaddb(SHORTCODE) \ - tcg_gen_gvec_add(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_add_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, VvV_b= ase, \ + VvV_off, sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vaddh(SHORTCYDE) \ - tcg_gen_gvec_add(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_add_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vaddw(SHORTCODE) \ - tcg_gen_gvec_add(MO_32, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_add_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vaddb_dv(SHORTCODE) \ - tcg_gen_gvec_add(MO_8, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_add_var(MO_8, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 #define fGEN_TCG_V6_vaddh_dv(SHORTCYDE) \ - tcg_gen_gvec_add(MO_16, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_add_var(MO_16, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 #define fGEN_TCG_V6_vaddw_dv(SHORTCODE) \ - tcg_gen_gvec_add(MO_32, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_add_var(MO_32, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 /* Vector sub - various forms */ #define fGEN_TCG_V6_vsubb(SHORTCODE) \ - tcg_gen_gvec_sub(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_sub_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, VvV_b= ase, \ + VvV_off, sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vsubh(SHORTCODE) \ - tcg_gen_gvec_sub(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_sub_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vsubw(SHORTCODE) \ - tcg_gen_gvec_sub(MO_32, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_sub_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vsubb_dv(SHORTCODE) \ - tcg_gen_gvec_sub(MO_8, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_sub_var(MO_8, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 #define fGEN_TCG_V6_vsubh_dv(SHORTCODE) \ - tcg_gen_gvec_sub(MO_16, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_sub_var(MO_16, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 #define fGEN_TCG_V6_vsubw_dv(SHORTCODE) \ - tcg_gen_gvec_sub(MO_32, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_sub_var(MO_32, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 #define fGEN_TCG_V6_vaddbsat(SHORTCODE) \ - tcg_gen_gvec_ssadd(MO_8, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ssadd_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddhsat(SHORTCODE) \ - tcg_gen_gvec_ssadd(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ssadd_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddwsat(SHORTCODE) \ - tcg_gen_gvec_ssadd(MO_32, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ssadd_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddubsat(SHORTCODE) \ - tcg_gen_gvec_usadd(MO_8, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_usadd_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vadduhsat(SHORTCODE) \ - tcg_gen_gvec_usadd(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_usadd_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vadduwsat(SHORTCODE) \ - tcg_gen_gvec_usadd(MO_32, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_usadd_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 -#define fGEN_TCG_PAIR_ADDSUB(OP, VECE, DST, SRC_A, SRC_B) \ - tcg_gen_gvec_##OP(VECE, DST, SRC_A, SRC_B, \ - 2 * VECTOR_SIZE_BYTE, 2 * VECTOR_SIZE_BYTE) +#define fGEN_TCG_PAIR_ADDSUB(OP, VECE, DBASE, DST, ABASE, SRC_A, BBASE, SR= C_B) \ + tcg_gen_gvec_##OP##_var(VECE, DBASE, DST, ABASE, SRC_A, BBASE, SRC_B, \ + 2 * VECTOR_SIZE_BYTE, 2 * VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddbsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ssadd, MO_8, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ssadd, MO_8, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vaddhsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ssadd, MO_16, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ssadd, MO_16, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vaddwsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ssadd, MO_32, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ssadd, MO_32, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vaddubsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(usadd, MO_8, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(usadd, MO_8, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vadduhsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(usadd, MO_16, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(usadd, MO_16, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vadduwsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(usadd, MO_32, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(usadd, MO_32, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsubbsat(SHORTCODE) \ - tcg_gen_gvec_sssub(MO_8, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_sssub_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubhsat(SHORTCODE) \ - tcg_gen_gvec_sssub(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_sssub_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubwsat(SHORTCODE) \ - tcg_gen_gvec_sssub(MO_32, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_sssub_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsububsat(SHORTCODE) \ - tcg_gen_gvec_ussub(MO_8, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ussub_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubuhsat(SHORTCODE) \ - tcg_gen_gvec_ussub(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ussub_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubuwsat(SHORTCODE) \ - tcg_gen_gvec_ussub(MO_32, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ussub_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubbsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(sssub, MO_8, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(sssub, MO_8, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsubhsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(sssub, MO_16, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(sssub, MO_16, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsubwsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(sssub, MO_32, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(sssub, MO_32, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsububsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ussub, MO_8, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ussub, MO_8, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsubuhsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ussub, MO_16, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ussub, MO_16, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsubuwsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ussub, MO_32, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ussub, MO_32, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vmpyih(SHORTCODE) \ - tcg_gen_gvec_mul(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_mul_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vabsdiffub(SHORTCODE) \ - gen_gvec_uabsdiff(MO_8, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + gen_gvec_uabsdiff_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vabsdiffuh(SHORTCODE) \ - gen_gvec_uabsdiff(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + gen_gvec_uabsdiff_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vabsdiffh(SHORTCODE) \ - gen_gvec_sabsdiff(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + gen_gvec_sabsdiff_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vabsdiffw(SHORTCODE) \ - gen_gvec_sabsdiff(MO_32, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + gen_gvec_sabsdiff_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_VEC_AVG(VECE, SHIFT_FN) \ do { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ - tcg_gen_gvec_and(MO_64, tmpoff, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - SHIFT_FN(VECE, VdV_off, VdV_off, 1, \ + tcg_gen_gvec_and_var(MO_64, tcg_env, tmpoff, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + tcg_gen_gvec_xor_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + SHIFT_FN(VECE, VdV_base, VdV_off, VdV_base, VdV_off, 1, \ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - tcg_gen_gvec_add(VECE, VdV_off, tmpoff, VdV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + tcg_gen_gvec_add_var(VECE, VdV_base, VdV_off, tcg_env, tmpoff, \ + VdV_base, VdV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vavgub(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavguh(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavguw(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavgb(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_sari_var) =20 #define fGEN_TCG_V6_vavgh(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_sari_var) =20 #define fGEN_TCG_V6_vavgw(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_sari_var) =20 #define fGEN_TCG_VEC_AVGRND(VECE, SHIFT_FN) \ do { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ - tcg_gen_gvec_or(MO_64, tmpoff, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - SHIFT_FN(VECE, VdV_off, VdV_off, 1, \ + tcg_gen_gvec_or_var(MO_64, tcg_env, tmpoff, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + tcg_gen_gvec_xor_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + SHIFT_FN(VECE, VdV_base, VdV_off, VdV_base, VdV_off, 1, \ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - tcg_gen_gvec_sub(VECE, VdV_off, tmpoff, VdV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + tcg_gen_gvec_sub_var(VECE, VdV_base, VdV_off, tcg_env, tmpoff, \ + VdV_base, VdV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vavgubrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavguhrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavguwrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavgbrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_sari_var) =20 #define fGEN_TCG_V6_vavghrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_sari_var) =20 #define fGEN_TCG_V6_vavgwrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_sari_var) =20 /* Vector shift right - various forms */ #define fGEN_TCG_V6_vasrh(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ - tcg_gen_gvec_sars(MO_16, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_sars_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vasrh_acc(SHORTCODE) \ @@ -418,18 +466,19 @@ static inline void assert_vhist_tmp(DisasContext *ctx) intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ - tcg_gen_gvec_sars(MO_16, tmpoff, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_sars_var(MO_16, tcg_env, tmpoff, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_add_var(MO_16, VxV_base, VxV_off, VxV_base, VxV_off, \ + tcg_env, tmpoff, sizeof(MMVector), \ + sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vasrw(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ - tcg_gen_gvec_sars(MO_32, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_sars_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vasrw_acc(SHORTCODE) \ @@ -437,34 +486,35 @@ static inline void assert_vhist_tmp(DisasContext *ctx) intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ - tcg_gen_gvec_sars(MO_32, tmpoff, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_sars_var(MO_32, tcg_env, tmpoff, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_add_var(MO_32, VxV_base, VxV_off, VxV_base, VxV_off, \ + tcg_env, tmpoff, sizeof(MMVector), \ + sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vlsrb(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 7); \ - tcg_gen_gvec_shrs(MO_8, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shrs_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vlsrh(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ - tcg_gen_gvec_shrs(MO_16, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shrs_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vlsrw(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ - tcg_gen_gvec_shrs(MO_32, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shrs_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 /* Vector shift left - various forms */ @@ -472,16 +522,16 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 7); \ - tcg_gen_gvec_shls(MO_8, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shls_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vaslh(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ - tcg_gen_gvec_shls(MO_16, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shls_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vaslh_acc(SHORTCODE) \ @@ -489,18 +539,19 @@ static inline void assert_vhist_tmp(DisasContext *ctx) intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ - tcg_gen_gvec_shls(MO_16, tmpoff, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shls_var(MO_16, tcg_env, tmpoff, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_add_var(MO_16, VxV_base, VxV_off, VxV_base, VxV_off, \ + tcg_env, tmpoff, sizeof(MMVector), \ + sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vaslw(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ - tcg_gen_gvec_shls(MO_32, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shls_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vaslw_acc(SHORTCODE) \ @@ -508,95 +559,109 @@ static inline void assert_vhist_tmp(DisasContext *ct= x) intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ - tcg_gen_gvec_shls(MO_32, tmpoff, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shls_var(MO_32, tcg_env, tmpoff, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_add_var(MO_32, VxV_base, VxV_off, VxV_base, VxV_off, \ + tcg_env, tmpoff, sizeof(MMVector), \ + sizeof(MMVector)); \ } while (0) =20 /* Vector max - various forms */ #define fGEN_TCG_V6_vmaxw(SHORTCODE) \ - tcg_gen_gvec_smax(MO_32, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smax_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vmaxh(SHORTCODE) \ - tcg_gen_gvec_smax(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smax_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vmaxuh(SHORTCODE) \ - tcg_gen_gvec_umax(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_umax_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vmaxb(SHORTCODE) \ - tcg_gen_gvec_smax(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smax_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vmaxub(SHORTCODE) \ - tcg_gen_gvec_umax(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_umax_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 /* Vector min - various forms */ #define fGEN_TCG_V6_vminw(SHORTCODE) \ - tcg_gen_gvec_smin(MO_32, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smin_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vminh(SHORTCODE) \ - tcg_gen_gvec_smin(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smin_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vminuh(SHORTCODE) \ - tcg_gen_gvec_umin(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_umin_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vminb(SHORTCODE) \ - tcg_gen_gvec_smin(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smin_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vminub(SHORTCODE) \ - tcg_gen_gvec_umin(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_umin_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 /* Vector logical ops */ #define fGEN_TCG_V6_vxor(SHORTCODE) \ - tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_xor_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vand(SHORTCODE) \ - tcg_gen_gvec_and(MO_64, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_and_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vor(SHORTCODE) \ - tcg_gen_gvec_or(MO_64, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_or_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, VvV_b= ase, \ + VvV_off, sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vnot(SHORTCODE) \ - tcg_gen_gvec_not(MO_64, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_not_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 /* Q register logical ops */ #define fGEN_TCG_V6_pred_or(SHORTCODE) \ - tcg_gen_gvec_or(MO_64, QdV_off, QsV_off, QtV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_or_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, QtV_b= ase, \ + QtV_off, sizeof(MMQReg), sizeof(MMQReg)) =20 #define fGEN_TCG_V6_pred_and(SHORTCODE) \ - tcg_gen_gvec_and(MO_64, QdV_off, QsV_off, QtV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_and_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, \ + QtV_base, QtV_off, sizeof(MMQReg), sizeof(MMQReg)) =20 #define fGEN_TCG_V6_pred_xor(SHORTCODE) \ - tcg_gen_gvec_xor(MO_64, QdV_off, QsV_off, QtV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_xor_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, \ + QtV_base, QtV_off, sizeof(MMQReg), sizeof(MMQReg)) =20 #define fGEN_TCG_V6_pred_or_n(SHORTCODE) \ - tcg_gen_gvec_orc(MO_64, QdV_off, QsV_off, QtV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_orc_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, \ + QtV_base, QtV_off, sizeof(MMQReg), sizeof(MMQReg)) =20 #define fGEN_TCG_V6_pred_and_n(SHORTCODE) \ - tcg_gen_gvec_andc(MO_64, QdV_off, QsV_off, QtV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_andc_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, \ + QtV_base, QtV_off, sizeof(MMQReg), sizeof(MMQReg= )) =20 #define fGEN_TCG_V6_pred_not(SHORTCODE) \ - tcg_gen_gvec_not(MO_64, QdV_off, QsV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_not_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, \ + sizeof(MMQReg), sizeof(MMQReg)) =20 /* Vector compares */ #define fGEN_TCG_VEC_CMP(COND, TYPE, SIZE) \ do { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ - tcg_gen_gvec_cmp(COND, TYPE, tmpoff, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - vec_to_qvec(SIZE, QdV_off, tmpoff); \ + tcg_gen_gvec_cmp_var(COND, TYPE, tcg_env, tmpoff, VuV_base, VuV_of= f, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)); \ + vec_to_qvec(SIZE, QdV_base, QdV_off, tcg_env, tmpoff); \ } while (0) =20 #define fGEN_TCG_V6_vgtw(SHORTCODE) \ @@ -624,100 +689,102 @@ static inline void assert_vhist_tmp(DisasContext *c= tx) do { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ intptr_t qoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_cmp(COND, TYPE, tmpoff, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - vec_to_qvec(SIZE, qoff, tmpoff); \ - OP(MO_64, QxV_off, QxV_off, qoff, sizeof(MMQReg), sizeof(MMQReg));= \ + tcg_gen_gvec_cmp_var(COND, TYPE, tcg_env, tmpoff, VuV_base, VuV_of= f, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)); \ + vec_to_qvec(SIZE, tcg_env, qoff, tcg_env, tmpoff); \ + OP(MO_64, QxV_base, QxV_off, QxV_base, QxV_off, tcg_env, qoff, \ + sizeof(MMQReg), sizeof(MMQReg)); \ } while (0) =20 #define fGEN_TCG_V6_vgtw_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgtw_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgtw_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_vgtuw_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgtuw_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgtuw_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_vgth_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgth_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgth_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_vgtuh_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgtuh_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgtuh_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_vgtb_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgtb_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgtb_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_vgtub_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgtub_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgtub_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_veqw_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_veqw_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_veqw_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_veqh_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_veqh_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_veqh_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_veqb_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_veqb_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_veqb_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_xor_var) =20 /* Vector splat - various forms */ #define fGEN_TCG_V6_lvsplatw(SHORTCODE) \ - tcg_gen_gvec_dup_i32(MO_32, VdV_off, \ - sizeof(MMVector), sizeof(MMVector), RtV) + tcg_gen_gvec_dup_i32_var(MO_32, VdV_base, VdV_off, sizeof(MMVector), \ + sizeof(MMVector), RtV) =20 #define fGEN_TCG_V6_lvsplath(SHORTCODE) \ - tcg_gen_gvec_dup_i32(MO_16, VdV_off, \ - sizeof(MMVector), sizeof(MMVector), RtV) + tcg_gen_gvec_dup_i32_var(MO_16, VdV_base, VdV_off, sizeof(MMVector), \ + sizeof(MMVector), RtV) =20 #define fGEN_TCG_V6_lvsplatb(SHORTCODE) \ - tcg_gen_gvec_dup_i32(MO_8, VdV_off, \ - sizeof(MMVector), sizeof(MMVector), RtV) + tcg_gen_gvec_dup_i32_var(MO_8, VdV_base, VdV_off, sizeof(MMVector), \ + sizeof(MMVector), RtV) =20 /* Vector absolute value - various forms */ #define fGEN_TCG_V6_vabsb(SHORTCODE) \ - tcg_gen_gvec_abs(MO_8, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_abs_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vabsh(SHORTCODE) \ - tcg_gen_gvec_abs(MO_16, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_abs_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vabsw(SHORTCODE) \ - tcg_gen_gvec_abs(MO_32, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_abs_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 /* Vector loads */ #define fGEN_TCG_V6_vL32b_pi(SHORTCODE) SHORTCODE @@ -743,14 +810,14 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_V6_vL32b_nt_tmp_ppu(SHORTCODE) SHORTCODE =20 /* Predicated vector loads */ -#define fGEN_TCG_PRED_VEC_LOAD(GET_EA, PRED, DSTOFF, INC) \ +#define fGEN_TCG_PRED_VEC_LOAD(GET_EA, PRED, DST, INC) \ do { \ TCGv LSB =3D tcg_temp_new(); \ TCGLabel *false_label =3D gen_new_label(); \ GET_EA; \ PRED; \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ - gen_vreg_load(ctx, DSTOFF, EA, true); \ + gen_vreg_load(ctx, DST##_base, DST##_off, EA, true); \ INC; \ gen_set_label(false_label); \ } while (0) @@ -758,12 +825,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_PRED_VEC_LOAD_pred_pi \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ fEA_REG(RxV), \ - VdV_off, \ + VdV, \ fPM_I(RxV, siV * sizeof(MMVector))) #define fGEN_TCG_PRED_VEC_LOAD_npred_pi \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - VdV_off, \ + VdV, \ fPM_I(RxV, siV * sizeof(MMVector))) =20 #define fGEN_TCG_V6_vL32b_pred_pi(SHORTCODE) \ @@ -794,12 +861,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_PRED_VEC_LOAD_pred_ai \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - VdV_off, \ + VdV, \ do {} while (0)) #define fGEN_TCG_PRED_VEC_LOAD_npred_ai \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - VdV_off, \ + VdV, \ do {} while (0)) =20 #define fGEN_TCG_V6_vL32b_pred_ai(SHORTCODE) \ @@ -830,12 +897,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_PRED_VEC_LOAD_pred_ppu \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ fEA_REG(RxV), \ - VdV_off, \ + VdV, \ fPM_M(RxV, MuV)) #define fGEN_TCG_PRED_VEC_LOAD_npred_ppu \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - VdV_off, \ + VdV, \ fPM_M(RxV, MuV)) =20 #define fGEN_TCG_V6_vL32b_pred_ppu(SHORTCODE) \ @@ -878,7 +945,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_NEWVAL_VEC_STORE(GET_EA, INC) \ do { \ GET_EA; \ - gen_vreg_store(ctx, EA, OsN_off, insn->slot, true); \ + gen_vreg_store(ctx, EA, OsN_base, OsN_off, insn->slot, true); \ INC; \ } while (0) =20 @@ -908,14 +975,15 @@ static inline void assert_vhist_tmp(DisasContext *ctx) fGEN_TCG_NEWVAL_VEC_STORE_ppu =20 /* Predicated vector stores */ -#define fGEN_TCG_PRED_VEC_STORE(GET_EA, PRED, SRCOFF, ALIGN, INC) \ +#define fGEN_TCG_PRED_VEC_STORE(GET_EA, PRED, SRC, ALIGN, INC) \ do { \ TCGv LSB =3D tcg_temp_new(); \ TCGLabel *false_label =3D gen_new_label(); \ GET_EA; \ PRED; \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ - gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \ + gen_vreg_store(ctx, EA, SRC##_base, SRC##_off, insn->slot, \ + ALIGN); \ INC; \ gen_set_label(false_label); \ } while (0) @@ -923,22 +991,22 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_PRED_VEC_STORE_pred_pi(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_REG(RxV), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ fPM_I(RxV, siV * sizeof(MMVector))) #define fGEN_TCG_PRED_VEC_STORE_npred_pi(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ fPM_I(RxV, siV * sizeof(MMVector))) #define fGEN_TCG_PRED_VEC_STORE_new_pred_pi \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_REG(RxV), \ - OsN_off, true, \ + OsN, true, \ fPM_I(RxV, siV * sizeof(MMVector))) #define fGEN_TCG_PRED_VEC_STORE_new_npred_pi \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - OsN_off, true, \ + OsN, true, \ fPM_I(RxV, siV * sizeof(MMVector))) =20 #define fGEN_TCG_V6_vS32b_pred_pi(SHORTCODE) \ @@ -965,22 +1033,22 @@ static inline void assert_vhist_tmp(DisasContext *ct= x) #define fGEN_TCG_PRED_VEC_STORE_pred_ai(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ do { } while (0)) #define fGEN_TCG_PRED_VEC_STORE_npred_ai(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ do { } while (0)) #define fGEN_TCG_PRED_VEC_STORE_new_pred_ai \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - OsN_off, true, \ + OsN, true, \ do { } while (0)) #define fGEN_TCG_PRED_VEC_STORE_new_npred_ai \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - OsN_off, true, \ + OsN, true, \ do { } while (0)) =20 #define fGEN_TCG_V6_vS32b_pred_ai(SHORTCODE) \ @@ -1007,22 +1075,22 @@ static inline void assert_vhist_tmp(DisasContext *c= tx) #define fGEN_TCG_PRED_VEC_STORE_pred_ppu(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_REG(RxV), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ fPM_M(RxV, MuV)) #define fGEN_TCG_PRED_VEC_STORE_npred_ppu(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ fPM_M(RxV, MuV)) #define fGEN_TCG_PRED_VEC_STORE_new_pred_ppu \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_REG(RxV), \ - OsN_off, true, \ + OsN, true, \ fPM_M(RxV, MuV)) #define fGEN_TCG_PRED_VEC_STORE_new_npred_ppu \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - OsN_off, true, \ + OsN, true, \ fPM_M(RxV, MuV)) =20 #define fGEN_TCG_V6_vS32b_pred_ppu(SHORTCODE) \ diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index f498398367c..238ee089cba 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -59,6 +59,14 @@ TCGv gen_get_half(TCGv result, int N, TCGv src, bool sig= n); void gen_set_half(int N, TCGv result, TCGv src); void gen_set_half_i64(int N, TCGv_i64 result, TCGv src); void probe_noshuf_load(TCGv va, int s, int mi); +void gen_gvec_sabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void gen_gvec_uabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); void gen_gvec_sabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void gen_gvec_uabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index b36f833b1de..df695d0731c 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -286,26 +286,28 @@ fV_AL_CHECK(EA, fVECSIZE() - 1); \ } while (0) #ifdef QEMU_GENERATE -#define fLOADMMV(EA, DST) gen_vreg_load(ctx, DST##_off, EA, true) +#define fLOADMMV(EA, DST) gen_vreg_load(ctx, DST##_base, DST##_off, EA, tr= ue) #endif #ifdef QEMU_GENERATE -#define fLOADMMVU(EA, DST) gen_vreg_load(ctx, DST##_off, EA, false) +#define fLOADMMVU(EA, DST) gen_vreg_load(ctx, DST##_base, DST##_off, EA, f= alse) #endif #ifdef QEMU_GENERATE #define fSTOREMMV(EA, SRC) \ - gen_vreg_store(ctx, EA, SRC##_off, insn->slot, true) + gen_vreg_store(ctx, EA, SRC##_base, SRC##_off, insn->slot, true) #endif #ifdef QEMU_GENERATE #define fSTOREMMVQ(EA, SRC, MASK) \ - gen_vreg_masked_store(ctx, EA, SRC##_off, MASK##_off, insn->slot, fals= e) + gen_vreg_masked_store(ctx, EA, SRC##_base, SRC##_off, \ + MASK##_base, MASK##_off, insn->slot, false) #endif #ifdef QEMU_GENERATE #define fSTOREMMVNQ(EA, SRC, MASK) \ - gen_vreg_masked_store(ctx, EA, SRC##_off, MASK##_off, insn->slot, true) + gen_vreg_masked_store(ctx, EA, SRC##_base, SRC##_off, \ + MASK##_base, MASK##_off, insn->slot, true) #endif #ifdef QEMU_GENERATE #define fSTOREMMVU(EA, SRC) \ - gen_vreg_store(ctx, EA, SRC##_off, insn->slot, false) + gen_vreg_store(ctx, EA, SRC##_base, SRC##_off, insn->slot, false) #endif #define fVFOREACH(WIDTH, VAR) for (VAR =3D 0; VAR < fVELEM(WIDTH); VAR++) #define fVARRAY_ELEMENT_ACCESS(ARRAY, TYPE, INDEX) \ diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index b33d5dbdbe8..d5940b93763 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -215,9 +215,9 @@ static inline void ctx_log_reg_read_pair(DisasContext *= ctx, int rnum) } =20 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, - int num, bool alloc_ok); + int num, bool alloc_ok, TCGv_ptr *base); intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, - int num, bool alloc_ok); + int num, bool alloc_ok, TCGv_ptr *base); =20 static inline void ctx_start_hvx_insn(DisasContext *ctx) { @@ -363,6 +363,8 @@ extern TCGv_i64 hex_llsc_val_i64; extern TCGv hex_vstore_addr[VSTORES_MAX]; extern TCGv hex_vstore_size[VSTORES_MAX]; extern TCGv hex_vstore_pending[VSTORES_MAX]; +#define hex_hvx_ptr tcg_env +#define HEX_HVX_OFFSET(member) offsetof(CPUHexagonState, member) #ifndef CONFIG_USER_ONLY extern TCGv_i32 hex_greg[NUM_GREGS]; extern TCGv_i32 hex_t_sreg[NUM_SREGS]; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 19486e0f741..7298cd27a0e 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -191,7 +191,7 @@ static void print_vreg(FILE *f, CPUHexagonState *env, i= nt regnum, if (skip_if_zero) { bool nonzero_found =3D false; for (int i =3D 0; i < MAX_VEC_SIZE_BYTES; i++) { - if (env->VRegs[regnum].ub[i] !=3D 0) { + if (hex_hvx(env)->VRegs[regnum].ub[i] !=3D 0) { nonzero_found =3D true; break; } @@ -202,9 +202,10 @@ static void print_vreg(FILE *f, CPUHexagonState *env, = int regnum, } =20 qemu_fprintf(f, " v%d =3D ( ", regnum); - qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1= ]); + qemu_fprintf(f, "0x%02x", + hex_hvx(env)->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]); for (int i =3D MAX_VEC_SIZE_BYTES - 2; i >=3D 0; i--) { - qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]); + qemu_fprintf(f, ", 0x%02x", hex_hvx(env)->VRegs[regnum].ub[i]); } qemu_fprintf(f, " )\n"); } @@ -220,7 +221,7 @@ static void print_qreg(FILE *f, CPUHexagonState *env, i= nt regnum, if (skip_if_zero) { bool nonzero_found =3D false; for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { - if (env->QRegs[regnum].ub[i] !=3D 0) { + if (hex_hvx(env)->QRegs[regnum].ub[i] !=3D 0) { nonzero_found =3D true; break; } @@ -232,9 +233,9 @@ static void print_qreg(FILE *f, CPUHexagonState *env, i= nt regnum, =20 qemu_fprintf(f, " q%d =3D ( ", regnum); qemu_fprintf(f, "0x%02x", - env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]); + hex_hvx(env)->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1= ]); for (int i =3D MAX_VEC_SIZE_BYTES / 8 - 2; i >=3D 0; i--) { - qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]); + qemu_fprintf(f, ", 0x%02x", hex_hvx(env)->QRegs[regnum].ub[i]); } qemu_fprintf(f, " )\n"); } diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index b9856cfc978..76ab5235f6e 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -80,8 +80,8 @@ static int gdb_get_vreg(CPUHexagonState *env, GByteArray = *mem_buf, int n) { int total =3D 0; int i; - for (i =3D 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) { - total +=3D gdb_get_reg32(mem_buf, env->VRegs[n].uw[i]); + for (i =3D 0; i < ARRAY_SIZE(hex_hvx(env)->VRegs[n].uw); i++) { + total +=3D gdb_get_reg32(mem_buf, hex_hvx(env)->VRegs[n].uw[i]); } return total; } @@ -90,8 +90,8 @@ static int gdb_get_qreg(CPUHexagonState *env, GByteArray = *mem_buf, int n) { int total =3D 0; int i; - for (i =3D 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) { - total +=3D gdb_get_reg32(mem_buf, env->QRegs[n].uw[i]); + for (i =3D 0; i < ARRAY_SIZE(hex_hvx(env)->QRegs[n].uw); i++) { + total +=3D gdb_get_reg32(mem_buf, hex_hvx(env)->QRegs[n].uw[i]); } return total; } @@ -116,8 +116,8 @@ int hexagon_hvx_gdb_read_register(CPUState *cs, GByteAr= ray *mem_buf, int n) static int gdb_put_vreg(CPUHexagonState *env, uint8_t *mem_buf, int n) { int i; - for (i =3D 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) { - env->VRegs[n].uw[i] =3D ldl_le_p(mem_buf); + for (i =3D 0; i < ARRAY_SIZE(hex_hvx(env)->VRegs[n].uw); i++) { + hex_hvx(env)->VRegs[n].uw[i] =3D ldl_le_p(mem_buf); mem_buf +=3D 4; } return MAX_VEC_SIZE_BYTES; @@ -126,8 +126,8 @@ static int gdb_put_vreg(CPUHexagonState *env, uint8_t *= mem_buf, int n) static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n) { int i; - for (i =3D 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) { - env->QRegs[n].uw[i] =3D ldl_le_p(mem_buf); + for (i =3D 0; i < ARRAY_SIZE(hex_hvx(env)->QRegs[n].uw); i++) { + hex_hvx(env)->QRegs[n].uw[i] =3D ldl_le_p(mem_buf); mem_buf +=3D 4; } return MAX_VEC_SIZE_BYTES / 8; diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 4e9a9670d54..e1330d8e0b2 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -56,8 +56,10 @@ static void gen_sabsdiff_vec(unsigned vece, TCGv_vec d, = TCGv_vec a, TCGv_vec b) tcg_gen_sub_vec(vece, d, d, t); } =20 -void gen_gvec_sabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void gen_gvec_sabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_sub_vec, INDEX_op_smin_vec, INDEX_op_smax_vec, 0 @@ -75,7 +77,15 @@ void gen_gvec_sabsdiff(unsigned vece, uint32_t dofs, uin= t32_t aofs, }; =20 tcg_debug_assert(vece =3D=3D MO_16 || vece =3D=3D MO_32); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &ops[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &ops[vece]); +} + +void gen_gvec_sabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + gen_gvec_sabsdiff_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bof= s, + oprsz, maxsz); } =20 static void gen_uabsdiff_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_v= ec b) @@ -87,8 +97,10 @@ static void gen_uabsdiff_vec(unsigned vece, TCGv_vec d, = TCGv_vec a, TCGv_vec b) tcg_gen_sub_vec(vece, d, d, t); } =20 -void gen_gvec_uabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void gen_gvec_uabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_sub_vec, INDEX_op_umin_vec, INDEX_op_umax_vec, 0 @@ -105,7 +117,15 @@ void gen_gvec_uabsdiff(unsigned vece, uint32_t dofs, u= int32_t aofs, }; =20 tcg_debug_assert(vece =3D=3D MO_8 || vece =3D=3D MO_16); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &ops[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &ops[vece]); +} + +void gen_gvec_uabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + gen_gvec_uabsdiff_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bof= s, + oprsz, maxsz); } =20 TCGv gen_read_reg(TCGv result, int num) @@ -1435,54 +1455,56 @@ static void gen_asr_r_svw_trun(DisasContext *ctx, T= CGv RdV, gen_set_label(done); } =20 -static intptr_t vreg_src_off(DisasContext *ctx, int num) +static intptr_t vreg_src_off(DisasContext *ctx, int num, TCGv_ptr *base) { - intptr_t offset =3D offsetof(CPUHexagonState, VRegs[num]); + intptr_t offset =3D HEX_HVX_OFFSET(VRegs[num]); =20 + *base =3D hex_hvx_ptr; if (test_bit(num, ctx->vregs_select)) { - offset =3D ctx_future_vreg_off(ctx, num, 1, false); + offset =3D ctx_future_vreg_off(ctx, num, 1, false, base); } if (test_bit(num, ctx->vregs_updated_tmp)) { - offset =3D ctx_tmp_vreg_off(ctx, num, 1, false); + offset =3D ctx_tmp_vreg_off(ctx, num, 1, false, base); } return offset; } =20 -static void gen_vreg_write(DisasContext *ctx, intptr_t srcoff, int num, - VRegWriteType type) +static void gen_vreg_write(DisasContext *ctx, TCGv_ptr srcbase, + intptr_t srcoff, int num, VRegWriteType type) { + TCGv_ptr dstbase; intptr_t dstoff; =20 if (type !=3D EXT_TMP) { - dstoff =3D ctx_future_vreg_off(ctx, num, 1, true); - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, - sizeof(MMVector), sizeof(MMVector)); + dstoff =3D ctx_future_vreg_off(ctx, num, 1, true, &dstbase); } else { - dstoff =3D ctx_tmp_vreg_off(ctx, num, 1, false); - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, - sizeof(MMVector), sizeof(MMVector)); + dstoff =3D ctx_tmp_vreg_off(ctx, num, 1, false, &dstbase); } + tcg_gen_gvec_mov_var(MO_64, dstbase, dstoff, srcbase, srcoff, + sizeof(MMVector), sizeof(MMVector)); } =20 -static void gen_vreg_write_pair(DisasContext *ctx, intptr_t srcoff, int nu= m, - VRegWriteType type) +static void gen_vreg_write_pair(DisasContext *ctx, TCGv_ptr srcbase, + intptr_t srcoff, int num, VRegWriteType ty= pe) { - gen_vreg_write(ctx, srcoff, num ^ 0, type); + gen_vreg_write(ctx, srcbase, srcoff, num ^ 0, type); srcoff +=3D sizeof(MMVector); - gen_vreg_write(ctx, srcoff, num ^ 1, type); + gen_vreg_write(ctx, srcbase, srcoff, num ^ 1, type); } =20 -static intptr_t get_result_qreg(DisasContext *ctx, int qnum) +static intptr_t get_result_qreg(DisasContext *ctx, int qnum, TCGv_ptr *bas= e) { if (ctx->need_commit) { + *base =3D tcg_env; return offsetof(CPUHexagonState, future_QRegs[qnum]); } else { - return offsetof(CPUHexagonState, QRegs[qnum]); + *base =3D hex_hvx_ptr; + return HEX_HVX_OFFSET(QRegs[qnum]); } } =20 -static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src, - bool aligned) +static void gen_vreg_load(DisasContext *ctx, TCGv_ptr dstbase, + intptr_t dstoff, TCGv src, bool aligned) { TCGv_i64 tmp =3D tcg_temp_new_i64(); if (aligned) { @@ -1491,12 +1513,12 @@ static void gen_vreg_load(DisasContext *ctx, intptr= _t dstoff, TCGv src, for (int i =3D 0; i < sizeof(MMVector) / 8; i++) { tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_LE | MO_UQ); tcg_gen_addi_tl(src, src, 8); - tcg_gen_st_i64(tmp, tcg_env, dstoff + i * 8); + tcg_gen_st_i64(tmp, dstbase, dstoff + i * 8); } } =20 -static void gen_vreg_store(DisasContext *ctx, TCGv EA, intptr_t srcoff, - int slot, bool aligned) +static void gen_vreg_store(DisasContext *ctx, TCGv EA, TCGv_ptr srcbase, + intptr_t srcoff, int slot, bool aligned) { intptr_t dstoff =3D offsetof(CPUHexagonState, vstore[slot].data); intptr_t maskoff =3D offsetof(CPUHexagonState, vstore[slot].mask); @@ -1517,13 +1539,16 @@ static void gen_vreg_store(DisasContext *ctx, TCGv = EA, intptr_t srcoff, tcg_gen_movi_tl(hex_vstore_size[slot], sizeof(MMVector)); =20 /* Copy the data to the vstore buffer */ - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMVector), sizeof(MMVec= tor)); + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, srcbase, srcoff, + sizeof(MMVector), sizeof(MMVector)); /* Set the mask to all 1's */ tcg_gen_gvec_dup_imm(MO_64, maskoff, sizeof(MMQReg), sizeof(MMQReg), ~= 0LL); } =20 -static void gen_vreg_masked_store(DisasContext *ctx, TCGv EA, intptr_t src= off, - intptr_t bitsoff, int slot, bool invert) +static void gen_vreg_masked_store(DisasContext *ctx, TCGv EA, + TCGv_ptr srcbase, intptr_t srcoff, + TCGv_ptr bitsbase, intptr_t bitsoff, + int slot, bool invert) { intptr_t dstoff =3D offsetof(CPUHexagonState, vstore[slot].data); intptr_t maskoff =3D offsetof(CPUHexagonState, vstore[slot].mask); @@ -1534,16 +1559,19 @@ static void gen_vreg_masked_store(DisasContext *ctx= , TCGv EA, intptr_t srcoff, tcg_gen_movi_tl(hex_vstore_size[slot], sizeof(MMVector)); =20 /* Copy the data to the vstore buffer */ - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMVector), sizeof(MMVec= tor)); + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, srcbase, srcoff, + sizeof(MMVector), sizeof(MMVector)); /* Copy the mask */ - tcg_gen_gvec_mov(MO_64, maskoff, bitsoff, sizeof(MMQReg), sizeof(MMQRe= g)); + tcg_gen_gvec_mov_var(MO_64, tcg_env, maskoff, bitsbase, bitsoff, + sizeof(MMQReg), sizeof(MMQReg)); if (invert) { tcg_gen_gvec_not(MO_64, maskoff, maskoff, sizeof(MMQReg), sizeof(MMQReg)); } } =20 -static void vec_to_qvec(size_t size, intptr_t dstoff, intptr_t srcoff) +static void vec_to_qvec(size_t size, TCGv_ptr dstbase, intptr_t dstoff, + TCGv_ptr srcbase, intptr_t srcoff) { TCGv_i64 tmp =3D tcg_temp_new_i64(); TCGv_i64 word =3D tcg_temp_new_i64(); @@ -1553,7 +1581,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff,= intptr_t srcoff) TCGv_i64 ones =3D tcg_constant_i64(~0); =20 for (int i =3D 0; i < sizeof(MMVector) / 8; i++) { - tcg_gen_ld_i64(tmp, tcg_env, srcoff + i * 8); + tcg_gen_ld_i64(tmp, srcbase, srcoff + i * 8); tcg_gen_movi_i64(mask, 0); =20 for (int j =3D 0; j < 8; j +=3D size) { @@ -1562,7 +1590,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff,= intptr_t srcoff) tcg_gen_deposit_i64(mask, mask, bits, j, size); } =20 - tcg_gen_st8_i64(mask, tcg_env, dstoff + i); + tcg_gen_st8_i64(mask, dstbase, dstoff + i); } } =20 diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 0d08ac77361..47c7953b92e 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1408,7 +1408,8 @@ void HELPER(vhist)(CPUHexagonState *env) unsigned char regno =3D value >> 3; unsigned char element =3D value & 7; =20 - env->VRegs[regno].uh[(sizeof(MMVector) / 16) * lane + element]= ++; + hex_hvx(env)->VRegs[regno] + .uh[(sizeof(MMVector) / 16) * lane + element]++; } } } @@ -1424,7 +1425,7 @@ void HELPER(vhistq)(CPUHexagonState *env) unsigned char element =3D value & 7; =20 if (fGETQBIT(env->qtmp, sizeof(MMVector) / 8 * lane + i)) { - env->VRegs[regno].uh[ + hex_hvx(env)->VRegs[regno].uh[ (sizeof(MMVector) / 16) * lane + element]++; } } @@ -1441,8 +1442,8 @@ void HELPER(vwhist256)(CPUHexagonState *env) unsigned int vindex =3D (bucket >> 3) & 0x1F; unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); =20 - env->VRegs[vindex].uh[elindex] =3D - env->VRegs[vindex].uh[elindex] + weight; + hex_hvx(env)->VRegs[vindex].uh[elindex] =3D + hex_hvx(env)->VRegs[vindex].uh[elindex] + weight; } } =20 @@ -1457,8 +1458,8 @@ void HELPER(vwhist256q)(CPUHexagonState *env) unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); =20 if (fGETQBIT(env->qtmp, 2 * i)) { - env->VRegs[vindex].uh[elindex] =3D - env->VRegs[vindex].uh[elindex] + weight; + hex_hvx(env)->VRegs[vindex].uh[elindex] =3D + hex_hvx(env)->VRegs[vindex].uh[elindex] + weight; } } } @@ -1473,8 +1474,8 @@ void HELPER(vwhist256_sat)(CPUHexagonState *env) unsigned int vindex =3D (bucket >> 3) & 0x1F; unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); =20 - env->VRegs[vindex].uh[elindex] =3D - fVSATUH(env->VRegs[vindex].uh[elindex] + weight); + hex_hvx(env)->VRegs[vindex].uh[elindex] =3D + fVSATUH(hex_hvx(env)->VRegs[vindex].uh[elindex] + weight); } } =20 @@ -1489,8 +1490,8 @@ void HELPER(vwhist256q_sat)(CPUHexagonState *env) unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); =20 if (fGETQBIT(env->qtmp, 2 * i)) { - env->VRegs[vindex].uh[elindex] =3D - fVSATUH(env->VRegs[vindex].uh[elindex] + weight); + hex_hvx(env)->VRegs[vindex].uh[elindex] =3D + fVSATUH(hex_hvx(env)->VRegs[vindex].uh[elindex] + weight); } } } @@ -1505,8 +1506,8 @@ void HELPER(vwhist128)(CPUHexagonState *env) unsigned int vindex =3D (bucket >> 3) & 0x1F; unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); =20 - env->VRegs[vindex].uw[elindex] =3D - env->VRegs[vindex].uw[elindex] + weight; + hex_hvx(env)->VRegs[vindex].uw[elindex] =3D + hex_hvx(env)->VRegs[vindex].uw[elindex] + weight; } } =20 @@ -1521,8 +1522,8 @@ void HELPER(vwhist128q)(CPUHexagonState *env) unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); =20 if (fGETQBIT(env->qtmp, 2 * i)) { - env->VRegs[vindex].uw[elindex] =3D - env->VRegs[vindex].uw[elindex] + weight; + hex_hvx(env)->VRegs[vindex].uw[elindex] =3D + hex_hvx(env)->VRegs[vindex].uw[elindex] + weight; } } } @@ -1538,8 +1539,8 @@ void HELPER(vwhist128m)(CPUHexagonState *env, int32_t= uiV) unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); =20 if ((bucket & 1) =3D=3D uiV) { - env->VRegs[vindex].uw[elindex] =3D - env->VRegs[vindex].uw[elindex] + weight; + hex_hvx(env)->VRegs[vindex].uw[elindex] =3D + hex_hvx(env)->VRegs[vindex].uw[elindex] + weight; } } } @@ -1555,8 +1556,8 @@ void HELPER(vwhist128qm)(CPUHexagonState *env, int32_= t uiV) unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); =20 if (((bucket & 1) =3D=3D uiV) && fGETQBIT(env->qtmp, 2 * i)) { - env->VRegs[vindex].uw[elindex] =3D - env->VRegs[vindex].uw[elindex] + weight; + hex_hvx(env)->VRegs[vindex].uw[elindex] =3D + hex_hvx(env)->VRegs[vindex].uw[elindex] + weight; } } } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index bf92166e0fd..bebfeb2daca 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -82,14 +82,18 @@ static const char * const hexagon_prednames[] =3D { }; =20 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, - int num, bool alloc_ok) + int num, bool alloc_ok, TCGv_ptr *base) { intptr_t offset; =20 if (!ctx->need_commit) { - return offsetof(CPUHexagonState, VRegs[regnum]); + /* Short circuit: the write goes straight to the register file. */ + *base =3D hex_hvx_ptr; + return HEX_HVX_OFFSET(VRegs[regnum]); } =20 + *base =3D tcg_env; + /* See if it is already allocated */ for (int i =3D 0; i < ctx->future_vregs_idx; i++) { if (ctx->future_vregs_num[i] =3D=3D regnum) { @@ -108,10 +112,12 @@ intptr_t ctx_future_vreg_off(DisasContext *ctx, int r= egnum, } =20 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, - int num, bool alloc_ok) + int num, bool alloc_ok, TCGv_ptr *base) { intptr_t offset; =20 + *base =3D tcg_env; + /* See if it is already allocated */ for (int i =3D 0; i < ctx->tmp_vregs_idx; i++) { if (ctx->tmp_vregs_num[i] =3D=3D regnum) { @@ -743,26 +749,28 @@ static void gen_start_packet(DisasContext *ctx) if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) { i =3D find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); while (i < NUM_VREGS) { + TCGv_ptr VdV_base; const intptr_t VdV_off =3D - ctx_future_vreg_off(ctx, i, 1, true); - intptr_t src_off =3D offsetof(CPUHexagonState, VRegs[i]); - tcg_gen_gvec_mov(MO_64, VdV_off, - src_off, - sizeof(MMVector), - sizeof(MMVector)); + ctx_future_vreg_off(ctx, i, 1, true, &VdV_base); + intptr_t src_off =3D HEX_HVX_OFFSET(VRegs[i]); + tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, + hex_hvx_ptr, src_off, + sizeof(MMVector), + sizeof(MMVector)); i =3D find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i= + 1); } } if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) { i =3D find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); while (i < NUM_VREGS) { + TCGv_ptr VdV_base; const intptr_t VdV_off =3D - ctx_tmp_vreg_off(ctx, i, 1, true); - intptr_t src_off =3D offsetof(CPUHexagonState, VRegs[i]); - tcg_gen_gvec_mov(MO_64, VdV_off, - src_off, - sizeof(MMVector), - sizeof(MMVector)); + ctx_tmp_vreg_off(ctx, i, 1, true, &VdV_base); + intptr_t src_off =3D HEX_HVX_OFFSET(VRegs[i]); + tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, + hex_hvx_ptr, src_off, + sizeof(MMVector), + sizeof(MMVector)); i =3D find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + = 1); } } @@ -1062,31 +1070,34 @@ static void gen_commit_hvx(DisasContext *ctx) /* * for (i =3D 0; i < ctx->vreg_log_idx; i++) { * int rnum =3D ctx->vreg_log[i]; - * env->VRegs[rnum] =3D env->future_VRegs[rnum]; + * hex_hvx(env)->VRegs[rnum] =3D env->future_VRegs[rnum]; * } */ for (i =3D 0; i < ctx->vreg_log_idx; i++) { int rnum =3D ctx->vreg_log[i]; - intptr_t dstoff =3D offsetof(CPUHexagonState, VRegs[rnum]); - intptr_t srcoff =3D ctx_future_vreg_off(ctx, rnum, 1, false); + intptr_t dstoff =3D HEX_HVX_OFFSET(VRegs[rnum]); + TCGv_ptr srcbase; + intptr_t srcoff =3D ctx_future_vreg_off(ctx, rnum, 1, false, &srcb= ase); size_t size =3D sizeof(MMVector); =20 - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); + tcg_gen_gvec_mov_var(MO_64, hex_hvx_ptr, dstoff, srcbase, srcoff, + size, size); } =20 /* * for (i =3D 0; i < ctx->qreg_log_idx; i++) { * int rnum =3D ctx->qreg_log[i]; - * env->QRegs[rnum] =3D env->future_QRegs[rnum]; + * hex_hvx(env)->QRegs[rnum] =3D env->future_QRegs[rnum]; * } */ for (i =3D 0; i < ctx->qreg_log_idx; i++) { int rnum =3D ctx->qreg_log[i]; - intptr_t dstoff =3D offsetof(CPUHexagonState, QRegs[rnum]); + intptr_t dstoff =3D HEX_HVX_OFFSET(QRegs[rnum]); intptr_t srcoff =3D offsetof(CPUHexagonState, future_QRegs[rnum]); size_t size =3D sizeof(MMQReg); =20 - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); + tcg_gen_gvec_mov_var(MO_64, hex_hvx_ptr, dstoff, tcg_env, srcoff, + size, size); } =20 if (pkt_has_hvx_store(&ctx->pkt)) { diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index c180c19b092..02c54506145 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -434,6 +434,14 @@ def is_hvx_reg(self): return True def hvx_off(self): return f"{self.reg_tcg()}_off" + def hvx_base(self): + return f"{self.reg_tcg()}_base" + def decl_tcg_ptr(self, f): + ptr =3D self.reg_tcg() + f.write(code_fmt(f"""\ + TCGv_ptr {ptr} =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr({ptr}, {self.hvx_base()}, {self.hvx_off()}); + """)) def helper_proto_type(self): return "ptr" def helper_arg_type(self): @@ -778,18 +786,17 @@ class VRegDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; const intptr_t {self.hvx_off()} =3D - {vreg_offset_func(tag)}(ctx, {self.reg_num}, 1, true); + {vreg_offset_func(tag)}(ctx, {self.reg_num}, 1, + true, &{self.hvx_base()}); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_zero(self, f): f.write(code_fmt(f"""\ - tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, - sizeof(MMVector), sizeof(MMVector), 0); + tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, + {self.hvx_off()}, sizeof(MMVector), sizeof(MMVector), = 0); """)) def gen_write(self, f, tag): pass @@ -809,13 +816,12 @@ class VRegSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ - const intptr_t {self.hvx_off()} =3D vreg_src_off(ctx, {self.re= g_num}); + TCGv_ptr {self.hvx_base()}; + const intptr_t {self.hvx_off()} =3D + vreg_src_off(ctx, {self.reg_num}, &{self.hvx_base()}); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()})= */ @@ -830,8 +836,10 @@ def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) if skip_qemu_helper(tag): f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; const intptr_t {self.hvx_off()} =3D - ctx_future_vreg_off(ctx, {self.reg_num}, 1, true); + ctx_future_vreg_off(ctx, {self.reg_num}, 1, + true, &{self.hvx_base()}); """)) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ @@ -846,21 +854,24 @@ class VRegReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; + TCGv_ptr {self.reg_tcg()}_srcbase; const intptr_t {self.hvx_off()} =3D - {vreg_offset_func(tag)}(ctx, {self.reg_num}, 1, true); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - vreg_src_off(ctx, {self.reg_num}), - sizeof(MMVector), sizeof(MMVector)); + {vreg_offset_func(tag)}(ctx, {self.reg_num}, 1, + true, &{self.hvx_base()}); + const intptr_t {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num}, &{self.reg_tcg()}_srcbas= e); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, {self.hvx_off()= }, + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_zero(self, f): f.write(code_fmt(f"""\ - tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, - sizeof(MMVector), sizeof(MMVector), 0); + tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, + {self.hvx_off()}, sizeof(MMVector), sizeof(MMVector), = 0); """)) def gen_write(self, f, tag): pass @@ -884,15 +895,21 @@ class VRegTmp(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()} =3D tcg_env; const intptr_t {self.hvx_off()} =3D offsetof(CPUHexagonState, = vtmp); """)) if not skip_qemu_helper(tag): + self.decl_tcg_ptr(f) f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - vreg_src_off(ctx, {self.reg_num}), - sizeof(MMVector), sizeof(MMVector)); + TCGv_ptr {self.reg_tcg()}_srcbase; + const intptr_t {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num}, + &{self.reg_tcg()}_srcbase); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, + {self.hvx_off()}, + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); """)) def gen_zero(self, f): f.write(code_fmt(f"""\ @@ -901,8 +918,8 @@ def gen_zero(self, f): """)) def gen_write(self, f, tag): f.write(code_fmt(f"""\ - gen_vreg_write(ctx, {self.hvx_off()}, {self.reg_num}, - {hvx_newv(tag)}); + gen_vreg_write(ctx, {self.hvx_base()}, {self.hvx_off()}, + {self.reg_num}, {hvx_newv(tag)}); """)) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ @@ -924,17 +941,16 @@ class VRegPairDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; const intptr_t {self.hvx_off()} =3D - {vreg_offset_func(tag)}(ctx, {self.reg_num}, 2, true); + {vreg_offset_func(tag)}(ctx, {self.reg_num}, 2, + true, &{self.hvx_base()}); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_zero(self, f): f.write(code_fmt(f"""\ - tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, + tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_o= ff()}, sizeof(MMVectorPair), sizeof(MMVectorPair), 0); """)) def gen_write(self, f, tag): @@ -955,20 +971,27 @@ class VRegPairSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()} =3D tcg_env; + TCGv_ptr {self.reg_tcg()}_srcbase; const intptr_t {self.hvx_off()} =3D offsetof(CPUHexagonState, {self.reg_tcg()}); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - vreg_src_off(ctx, {self.reg_num}), - sizeof(MMVector), sizeof(MMVector)); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()} + sizeof(MMVector), - vreg_src_off(ctx, {self.reg_num} ^ 1), - sizeof(MMVector), sizeof(MMVector)); + intptr_t {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num}, &{self.reg_tcg()}_srcbas= e); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, {self.hvx_off()= }, + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); + {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num} ^ 1, + &{self.reg_tcg()}_srcbase); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, + {self.hvx_off()} + sizeof(MMVector), + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name= ()}) */ @@ -982,29 +1005,36 @@ class VRegPairReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()} =3D tcg_env; + TCGv_ptr {self.reg_tcg()}_srcbase; const intptr_t {self.hvx_off()} =3D offsetof(CPUHexagonState, {self.reg_tcg()}); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - vreg_src_off(ctx, {self.reg_num}), - sizeof(MMVector), sizeof(MMVector)); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()} + sizeof(MMVector), - vreg_src_off(ctx, {self.reg_num} ^ 1), - sizeof(MMVector), sizeof(MMVector)); + intptr_t {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num}, &{self.reg_tcg()}_srcbas= e); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, {self.hvx_off()= }, + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); + {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num} ^ 1, + &{self.reg_tcg()}_srcbase); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, + {self.hvx_off()} + sizeof(MMVector), + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_zero(self, f): f.write(code_fmt(f"""\ - tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, + tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_o= ff()}, sizeof(MMVectorPair), sizeof(MMVectorPair), 0); """)) def gen_write(self, f, tag): f.write(code_fmt(f"""\ - gen_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num}, - {hvx_newv(tag)}); + gen_vreg_write_pair(ctx, {self.hvx_base()}, {self.hvx_off()}, + {self.reg_num}, {hvx_newv(tag)}); """)) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ @@ -1026,14 +1056,12 @@ class QRegDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; const intptr_t {self.hvx_off()} =3D - get_result_qreg(ctx, {self.reg_num}); + get_result_qreg(ctx, {self.reg_num}, &{self.hvx_base()}); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -1049,14 +1077,12 @@ class QRegSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()} =3D hex_hvx_ptr; const intptr_t {self.hvx_off()} =3D - offsetof(CPUHexagonState, QRegs[{self.reg_num}]); + HEX_HVX_OFFSET(QRegs[{self.reg_num}]); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */ @@ -1070,17 +1096,16 @@ class QRegReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; const intptr_t {self.hvx_off()} =3D - get_result_qreg(ctx, {self.reg_num}); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - offsetof(CPUHexagonState, QRegs[{self.reg_num= }]), - sizeof(MMQReg), sizeof(MMQReg)); + get_result_qreg(ctx, {self.reg_num}, &{self.hvx_base()}); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, {self.hvx_off()= }, + hex_hvx_ptr, + HEX_HVX_OFFSET(QRegs[{self.reg_num}]), + sizeof(MMQReg), sizeof(MMQReg)); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301530; cv=none; d=zohomail.com; s=zohoarc; b=kzmT3NR7IggwKMgkp0xs0vBkyz3W7Ck56iiKq6lk7juiXRjZzLhp5Ll0N7E936i4+5ALor6ZKsrHVxs7Hy2d/3TamzVSwnwRkq6mYLDjDoTmKg+BuSDigNbYtVVT5JNAthT+TOH3oZMgsh09K+v51LqfwaJJJHRgpyM7tln3JJo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301530; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Oq9n4WL+RXCe6ldrt5N5L0VWIHW0Td7ZxjPFUkRIk7o=; b=UemwlsFmMcTLwe+H7R/n0kr7lMylOQyA6oiXBGhDe38nBdryEAvKSvshvnT/ADjgK1m3BcM9EzogEa5ZiAajfI5rVlknXJy/DVF4OlkR3hBNz7WULVL0VSy55qeYAM2o/9ak5YXIPpjuOxaYjdOzLdEeZ01p/ukQU3o8Bb+1Gyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790301530251984.7438126799017; Thu, 24 Sep 2026 18:58:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9vAK-0006PL-Fb; Thu, 24 Sep 2026 21:55:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9vAH-0006Dr-70 for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:53 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9vAE-0006Ba-0U for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:52 -0400 Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1ksCe155581 for ; Fri, 25 Sep 2026 01:55:39 GMT Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw1tjkdb9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 01:55:38 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-331b2ec616fso1394907eec.1 for ; Thu, 24 Sep 2026 18:55:38 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301531994158500 The HVX register file belongs to an extension context, not a hardware threa= d. Model each system-emulation context as a QOM device, link the contexts to each vCPU, and use SSR:XA to select the active context. Keep one embedded context per linux-user CPU. Carry the selected register-= file base with HVX operands so translated code can address the selected context at run time. Reviewed-by: Richard Henderson Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon.h | 1 + include/hw/hexagon/hexagon_hvx_context.h | 27 ++++++++ target/hexagon/cpu.h | 24 +++++-- target/hexagon/cpu_helper.h | 1 + target/hexagon/translate.h | 7 +- hw/hexagon/hex-subsys.c | 29 ++++++++ hw/hexagon/hexagon_hvx_context.c | 84 ++++++++++++++++++++++++ target/hexagon/cpu.c | 16 +++++ target/hexagon/cpu_helper.c | 82 +++++++++++++++++++++++ target/hexagon/machine.c | 12 ++++ target/hexagon/translate.c | 9 ++- hw/hexagon/meson.build | 1 + 12 files changed, 286 insertions(+), 7 deletions(-) create mode 100644 include/hw/hexagon/hexagon_hvx_context.h create mode 100644 hw/hexagon/hexagon_hvx_context.c diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 62398eeb359..9b5d33ffc3b 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -173,6 +173,7 @@ struct HexagonCommonMachineState { DeviceState *qtimer; DeviceState *glob_regs; DeviceState *tlb; + unsigned num_hvx_ctx; }; =20 #endif diff --git a/include/hw/hexagon/hexagon_hvx_context.h b/include/hw/hexagon/= hexagon_hvx_context.h new file mode 100644 index 00000000000..ab85816a7ff --- /dev/null +++ b/include/hw/hexagon/hexagon_hvx_context.h @@ -0,0 +1,27 @@ +/* + * Hexagon HVX Extension Context QOM Object + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEXAGON_HVX_CONTEXT_H +#define HEXAGON_HVX_CONTEXT_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" +#include "target/hexagon/cpu.h" + +#define TYPE_HEXAGON_HVX_CONTEXT "hexagon-hvx-context" +OBJECT_DECLARE_SIMPLE_TYPE(HexagonHVXContextState, HEXAGON_HVX_CONTEXT) + +struct HexagonHVXContextState { + SysBusDevice parent_obj; + + /* Physical context number, as SSR:XA maps to it. */ + uint32_t index; + + HexagonHVXContext regs; +}; + +#endif /* HEXAGON_HVX_CONTEXT_H */ diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 965abe4f6d4..df4c0182247 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -29,6 +29,7 @@ =20 typedef struct HexagonTLBState HexagonTLBState; typedef struct HexagonGlobalRegState HexagonGlobalRegState; +typedef struct HexagonHVXContextState HexagonHVXContextState; =20 #include "cpu-qom.h" #include "exec/cpu-common.h" @@ -49,6 +50,7 @@ typedef struct HexagonGlobalRegState HexagonGlobalRegStat= e; #define REG_WRITES_MAX 32 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ #define VSTORES_MAX 2 +#define HVX_CONTEXTS_MAX 8 #define MAX_TLB_ENTRIES 1024 #define THREADS_MAX 16 =20 @@ -120,6 +122,11 @@ typedef struct { /* Maximum number of vector temps in a packet */ #define VECTOR_TEMPS_MAX 4 =20 +typedef struct HexagonHVXContext { + MMVector VRegs[NUM_VREGS]; + MMQReg QRegs[NUM_QREGS]; +} QEMU_ALIGNED(16) HexagonHVXContext; + typedef struct CPUArchState { target_ulong gpr[TOTAL_PER_THREAD_REGS]; target_ulong pred[NUM_PREGS]; @@ -159,11 +166,15 @@ typedef struct CPUArchState { target_ulong llsc_val; uint64_t llsc_val_i64; =20 - MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16); +#ifdef CONFIG_USER_ONLY + HexagonHVXContext hvx_ctx; +#else + HexagonHVXContext *hvx; +#endif + MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); =20 - MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); =20 /* Temporaries used within instructions */ @@ -196,6 +207,7 @@ struct ArchCPU { CPUHexagonState env; HexagonCPUConfig cfg; #ifndef CONFIG_USER_ONLY + HexagonHVXContextState *hvx_ctx[HVX_CONTEXTS_MAX]; HexagonTLBState *tlb; uint32_t boot_addr; HexagonGlobalRegState *globalregs; @@ -204,9 +216,13 @@ struct ArchCPU { #endif }; =20 -static inline CPUHexagonState *hex_hvx(CPUHexagonState *env) +static inline HexagonHVXContext *hex_hvx(CPUHexagonState *env) { - return env; +#ifdef CONFIG_USER_ONLY + return &env->hvx_ctx; +#else + return env->hvx; +#endif } =20 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index 12512efd74f..afb4df59f80 100644 --- a/target/hexagon/cpu_helper.h +++ b/target/hexagon/cpu_helper.h @@ -15,6 +15,7 @@ void hexagon_peek_memory_range(CPUHexagonState *env, uint= 32_t start_addr, uint32_t length, uintptr_t retaddr); uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index); void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old); +unsigned hexagon_hvx_select_context(CPUHexagonState *env, uint32_t ssr); int get_cpu_mode(const CPUHexagonState *env); int get_exe_mode(const CPUHexagonState *env); void clear_wait_mode(CPUHexagonState *env); diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index d5940b93763..e17261761b2 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -363,8 +363,13 @@ extern TCGv_i64 hex_llsc_val_i64; extern TCGv hex_vstore_addr[VSTORES_MAX]; extern TCGv hex_vstore_size[VSTORES_MAX]; extern TCGv hex_vstore_pending[VSTORES_MAX]; +#ifdef CONFIG_USER_ONLY #define hex_hvx_ptr tcg_env -#define HEX_HVX_OFFSET(member) offsetof(CPUHexagonState, member) +#define HEX_HVX_OFFSET(member) offsetof(CPUHexagonState, hvx_ctx.member) +#else +extern TCGv_ptr hex_hvx_ptr; +#define HEX_HVX_OFFSET(member) offsetof(HexagonHVXContext, member) +#endif #ifndef CONFIG_USER_ONLY extern TCGv_i32 hex_greg[NUM_GREGS]; extern TCGv_i32 hex_t_sreg[NUM_SREGS]; diff --git a/hw/hexagon/hex-subsys.c b/hw/hexagon/hex-subsys.c index 4e3a418340e..9818cf58878 100644 --- a/hw/hexagon/hex-subsys.c +++ b/hw/hexagon/hex-subsys.c @@ -9,6 +9,7 @@ #include "qapi/error.h" #include "hw/hexagon/hex-subsys.h" #include "hw/hexagon/hexagon_globalreg.h" +#include "hw/hexagon/hexagon_hvx_context.h" #include "hw/hexagon/hexagon_tlb.h" #include "hw/intc/hex-l2vic.h" #include "hw/timer/qct-qtimer.h" @@ -98,6 +99,27 @@ static DeviceState *tlb_create(HexagonCommonMachineState= *hms, return tlb; } =20 +/* + * Create the core's HVX extension contexts. There are fewer of them than + * there are hardware threads, and SSR:XA picks which one a thread uses, so + * they belong to the subsystem rather than to any one CPU. + */ +static void hvx_contexts_create(HexagonCommonMachineState *hms, + const struct hexagon_machine_config *m_cfg) +{ + unsigned n =3D m_cfg->cfgtable.ext_contexts; + assert(n <=3D HVX_CONTEXTS_MAX); + for (unsigned i =3D 0; i < n; i++) { + DeviceState *ctx =3D qdev_new(TYPE_HEXAGON_HVX_CONTEXT); + g_autofree char *name =3D g_strdup_printf("hvx-context[%u]", i); + + object_property_add_child(OBJECT(hms), name, OBJECT(ctx)); + qdev_prop_set_uint32(ctx, "index", i); + sysbus_realize_and_unref(SYS_BUS_DEVICE(ctx), &error_fatal); + } + hms->num_hvx_ctx =3D n; +} + static DeviceState *cluster_create(HexagonCommonMachineState *hms) { DeviceState *cluster =3D qdev_new(TYPE_CPU_CLUSTER); @@ -140,6 +162,7 @@ void hex_subsys_create(HexagonCommonMachineState *hms, hms->qtimer =3D qtimer_create(hms, m_cfg); hms->glob_regs =3D globalreg_create(hms, m_cfg, rev); hms->tlb =3D tlb_create(hms, m_cfg); + hvx_contexts_create(hms, m_cfg); } =20 void hex_subsys_add_cpu(HexagonCommonMachineState *hms, DeviceState *cpu) @@ -151,6 +174,12 @@ void hex_subsys_add_cpu(HexagonCommonMachineState *hms= , DeviceState *cpu) &error_fatal); object_property_set_link(OBJECT(cpu), "l2vic", OBJECT(hms->l2vic), &error_fatal); + for (unsigned i =3D 0; i < hms->num_hvx_ctx; i++) { + g_autofree char *name =3D g_strdup_printf("hvx-context[%u]", i); + Object *ctx =3D object_resolve_path_component(OBJECT(hms), name); + + object_property_set_link(OBJECT(cpu), name, ctx, &error_fatal); + } } =20 void hex_subsys_realize_cluster(HexagonCommonMachineState *hms) diff --git a/hw/hexagon/hexagon_hvx_context.c b/hw/hexagon/hexagon_hvx_cont= ext.c new file mode 100644 index 00000000000..3b73498298e --- /dev/null +++ b/hw/hexagon/hexagon_hvx_context.c @@ -0,0 +1,84 @@ +/* + * Hexagon HVX Extension Context QOM Object + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/hexagon/hexagon_hvx_context.h" +#include "hw/core/qdev-properties.h" +#include "migration/vmstate.h" + +static void hexagon_hvx_context_reset_hold(Object *obj, ResetType type) +{ + HexagonHVXContextState *s =3D HEXAGON_HVX_CONTEXT(obj); + + memset(&s->regs, 0, sizeof(s->regs)); +} + +/* gvec needs VRegs/QRegs 16-aligned within the struct. */ +QEMU_BUILD_BUG_ON(offsetof(HexagonHVXContextState, regs) % 16 !=3D 0); + +static const VMStateDescription vmstate_mmvector =3D { + .name =3D "hexagon_mmvector", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]){ + VMSTATE_UINT64_ARRAY(ud, MMVector, MAX_VEC_SIZE_BYTES / 8), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_mmqreg =3D { + .name =3D "hexagon_mmqreg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]){ + VMSTATE_UINT64_ARRAY(ud, MMQReg, MAX_VEC_SIZE_BYTES / 8 / 8), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_hexagon_hvx_context =3D { + .name =3D "hexagon_hvx_context", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]){ + VMSTATE_STRUCT_ARRAY(regs.VRegs, HexagonHVXContextState, NUM_VREGS, + 1, vmstate_mmvector, MMVector), + VMSTATE_STRUCT_ARRAY(regs.QRegs, HexagonHVXContextState, NUM_QREGS, + 1, vmstate_mmqreg, MMQReg), + VMSTATE_END_OF_LIST() + } +}; + +static const Property hexagon_hvx_context_properties[] =3D { + DEFINE_PROP_UINT32("index", HexagonHVXContextState, index, 0), +}; + +static void hexagon_hvx_context_class_init(ObjectClass *klass, const void = *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D hexagon_hvx_context_reset_hold; + dc->vmsd =3D &vmstate_hexagon_hvx_context; + dc->user_creatable =3D false; + device_class_set_props(dc, hexagon_hvx_context_properties); +} + +static const TypeInfo hexagon_hvx_context_info =3D { + .name =3D TYPE_HEXAGON_HVX_CONTEXT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(HexagonHVXContextState), + .instance_align =3D __alignof(HexagonHVXContextState), + .class_init =3D hexagon_hvx_context_class_init, +}; + +static void hexagon_hvx_context_register_types(void) +{ + type_register_static(&hexagon_hvx_context_info); +} + +type_init(hexagon_hvx_context_register_types) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 7298cd27a0e..912bae7b6c2 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -43,6 +43,7 @@ #include "exec/page-protection.h" #include "exec/target_page.h" #include "hw/hexagon/hexagon_globalreg.h" +#include "hw/hexagon/hexagon_hvx_context.h" #endif =20 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) @@ -328,6 +329,9 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState = *cs) CPUHexagonState *env =3D cpu_env(cs); vaddr pc =3D env->gpr[HEX_REG_PC]; uint32_t hex_flags =3D 0; +#ifndef CONFIG_USER_ONLY + HexagonCPU *cpu; +#endif =20 if (pc =3D=3D env->gpr[HEX_REG_SA0]) { hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); @@ -338,10 +342,12 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUStat= e *cs) } =20 #ifndef CONFIG_USER_ONLY + cpu =3D env_archcpu(env); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, cpu_mmu_index(env_cpu(env), false)); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED, + cpu->hvx_ctx[0] && GET_SSR_FIELD(SSR_XE, env->t_sreg[HEX_SREG_SSR]= )); #else hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, MMU_USER_IDX); @@ -449,6 +455,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) env->t_sreg[HEX_SREG_HTID] =3D cpu->htid; env->threadId =3D cpu->htid; hexagon_cpu_soft_reset(env); + hexagon_hvx_select_context(env, env->t_sreg[HEX_SREG_SSR]); env->cause_code =3D HEX_EVENT_NONE; env->gpr[HEX_REG_PC] =3D cpu->boot_addr; #endif @@ -554,7 +561,16 @@ static void hexagon_cpu_init(Object *obj) { #ifndef CONFIG_USER_ONLY HexagonCPU *cpu =3D HEXAGON_CPU(obj); + qdev_init_gpio_in(DEVICE(cpu), hexagon_cpu_set_irq, 8); + + for (int i =3D 0; i < HVX_CONTEXTS_MAX; i++) { + object_property_add_link(obj, "hvx-context[*]", + TYPE_HEXAGON_HVX_CONTEXT, + (Object **)&cpu->hvx_ctx[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } #endif } =20 diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index eea5f60b46c..cf0762ff05f 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -11,6 +11,7 @@ #include "hw/core/boards.h" #include "hw/hexagon/hexagon.h" #include "hw/hexagon/hexagon_globalreg.h" +#include "hw/hexagon/hexagon_hvx_context.h" #include "hex_interrupts.h" #include "hex_mmu.h" #include "system/runstate.h" @@ -246,6 +247,75 @@ void hexagon_resume_threads(CPUHexagonState *current_e= nv, uint32_t mask) } } =20 +static unsigned hexagon_hvx_context_count(HexagonCPU *cpu) +{ + unsigned n; + + for (n =3D 0; n < HVX_CONTEXTS_MAX; n++) { + if (!cpu->hvx_ctx[n]) { + break; + } + } + return n; +} + +static unsigned hexagon_hvx_context_index(HexagonCPU *cpu, uint8_t xa) +{ + unsigned n =3D hexagon_hvx_context_count(cpu); + + if (n =3D=3D 0) { + return 0; + } + if (xa >=3D n) { + qemu_log_mask(LOG_GUEST_ERROR, + "SSR.XA %u is out of range for %u HVX contexts\n", + xa, n); + } + /* + * The behavior here is unspecified, reference simulator uses + * mappings that effectively keep the context in-range. The + * modulus seems just as good as any. + */ + return xa % n; +} + +/* + * Diagnostic only. Called separately from hexagon_hvx_select_context() + * so migration post_load, where other CPUs' env->hvx may still be stale, + * doesn't trip a false positive. + */ +static void hexagon_hvx_check_overcommit(CPUHexagonState *env, unsigned id= x) +{ + CPUState *cs; + unsigned users =3D 0; + + CPU_FOREACH(cs) { + CPUHexagonState *other =3D cpu_env(cs); + + if (other->hvx =3D=3D env->hvx && + GET_SSR_FIELD(SSR_XE, other->t_sreg[HEX_SREG_SSR])) { + users++; + } + } + + if (users > 1) { + qemu_log_mask(LOG_GUEST_ERROR, + "HVX context %u is enabled for %u hardware threads " + "at once, which is undefined\n", idx, users); + } +} + +unsigned hexagon_hvx_select_context(CPUHexagonState *env, uint32_t ssr) +{ + HexagonCPU *cpu =3D env_archcpu(env); + unsigned idx =3D hexagon_hvx_context_index(cpu, GET_SSR_FIELD(SSR_XA, = ssr)); + + if (cpu->hvx_ctx[0]) { + env->hvx =3D &cpu->hvx_ctx[idx]->regs; + } + return idx; +} + void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old) { bool old_EX, old_UM, old_GM, old_IE; @@ -269,6 +339,18 @@ void hexagon_modify_ssr(CPUHexagonState *env, uint32_t= new, uint32_t old) hex_mmu_mode_change(env); } =20 + bool xa_changed =3D GET_SSR_FIELD(SSR_XA, new) !=3D GET_SSR_FIELD(SSR_= XA, old); + bool xe_changed =3D GET_SSR_FIELD(SSR_XE, new) !=3D GET_SSR_FIELD(SSR_= XE, old); + + if (xa_changed || xe_changed) { + unsigned idx =3D xa_changed + ? hexagon_hvx_select_context(env, new) + : hexagon_hvx_context_index(env_archcpu(env), + GET_SSR_FIELD(SSR_XA, new)); + + hexagon_hvx_check_overcommit(env, idx); + } + old_asid =3D GET_SSR_FIELD(SSR_ASID, old); new_asid =3D GET_SSR_FIELD(SSR_ASID, new); if (new_asid !=3D old_asid) { diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c index bf4646f4a8b..179b6f53a2a 100644 --- a/target/hexagon/machine.c +++ b/target/hexagon/machine.c @@ -7,11 +7,23 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" #include "cpu.h" +#include "cpu_helper.h" + +static int hexagon_cpu_post_load(void *opaque, int version_id) +{ + HexagonCPU *cpu =3D opaque; + CPUHexagonState *env =3D &cpu->env; + + hexagon_hvx_select_context(env, env->t_sreg[HEX_SREG_SSR]); + + return 0; +} =20 const VMStateDescription vmstate_hexagon_cpu =3D { .name =3D "cpu", .version_id =3D 2, .minimum_version_id =3D 2, + .post_load =3D hexagon_cpu_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(env.gpr, HexagonCPU, TOTAL_PER_THREAD_REGS), VMSTATE_UINT32_ARRAY(env.pred, HexagonCPU, NUM_PREGS), diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index bebfeb2daca..827859e052c 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -70,6 +70,9 @@ TCGv hex_imprecise_exception; TCGv hex_vstore_addr[VSTORES_MAX]; TCGv hex_vstore_size[VSTORES_MAX]; TCGv hex_vstore_pending[VSTORES_MAX]; +#ifndef CONFIG_USER_ONLY +TCGv_ptr hex_hvx_ptr; +#endif =20 #ifndef CONFIG_USER_ONLY TCGv_i32 hex_greg[NUM_GREGS]; @@ -1070,7 +1073,7 @@ static void gen_commit_hvx(DisasContext *ctx) /* * for (i =3D 0; i < ctx->vreg_log_idx; i++) { * int rnum =3D ctx->vreg_log[i]; - * hex_hvx(env)->VRegs[rnum] =3D env->future_VRegs[rnum]; + * env->hvx->VRegs[rnum] =3D env->future_VRegs[rnum]; * } */ for (i =3D 0; i < ctx->vreg_log_idx; i++) { @@ -1087,7 +1090,7 @@ static void gen_commit_hvx(DisasContext *ctx) /* * for (i =3D 0; i < ctx->qreg_log_idx; i++) { * int rnum =3D ctx->qreg_log[i]; - * hex_hvx(env)->QRegs[rnum] =3D env->future_QRegs[rnum]; + * env->hvx->QRegs[rnum] =3D env->future_QRegs[rnum]; * } */ for (i =3D 0; i < ctx->qreg_log_idx; i++) { @@ -1421,6 +1424,8 @@ void hexagon_translate_init(void) opcode_init(); =20 #ifndef CONFIG_USER_ONLY + hex_hvx_ptr =3D tcg_global_mem_new_ptr(tcg_env, + offsetof(CPUHexagonState, hvx), "hvx"); for (i =3D 0; i < NUM_GREGS; i++) { hex_greg[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUHexagonState, greg[i]), diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build index 720a5d54dcc..c4b257dfa28 100644 --- a/hw/hexagon/meson.build +++ b/hw/hexagon/meson.build @@ -1,6 +1,7 @@ hexagon_ss =3D ss.source_set() hexagon_ss.add(files('hexagon_tlb.c')) hexagon_ss.add(files('hexagon_globalreg.c')) +hexagon_ss.add(files('hexagon_hvx_context.c')) hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hex-subsys.c')) hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c')) hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c')) --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301451605158500 These tests pass now that HVX is modeled for system emulation. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/functional/hexagon/test_arch_tests.py | 7 +++++++ tests/functional/hexagon/test_systests.py | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/tests/functional/hexagon/test_arch_tests.py b/tests/functional= /hexagon/test_arch_tests.py index 40f76e25ae6..28bf2f02d39 100755 --- a/tests/functional/hexagon/test_arch_tests.py +++ b/tests/functional/hexagon/test_arch_tests.py @@ -119,6 +119,13 @@ def test_user_mode(self) -> None: """ self.run_uart_test("test_user_mode") =20 + def test_hvx_context(self) -> None: + """Tests the HVX coprocessor context: SSR XA context selection + and isolation, vsplat/store, and the NO_COPROC_ENABLE exception + raised when SSR:XE is clear. + """ + self.run_uart_test("test_hvx_context") + =20 if __name__ =3D=3D "__main__": QemuSystemTest.main() diff --git a/tests/functional/hexagon/test_systests.py b/tests/functional/h= exagon/test_systests.py index 2779efa9172..c8137a71713 100755 --- a/tests/functional/hexagon/test_systests.py +++ b/tests/functional/hexagon/test_systests.py @@ -99,5 +99,11 @@ def test_mmu_multi_tlb(self): def test_timer_reg(self): self.run_exit_zero("timer_reg") =20 + def test_hvx_multi(self): + self.run_exit_zero("hvx-multi") + + def test_standalone_vec(self): + self.run_exit_zero("standalone_vec") + if __name__ =3D=3D "__main__": QemuSystemTest.main() --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301522; cv=none; d=zohomail.com; s=zohoarc; b=YgkWBcLBdo0P8ZPdJLpVujc8XwHeDF2sSrhgw+YU9l31BE5KwYNohfDMhwUmYL3YXZ7JMf/wYhxn73SYbc6TgMyLatE1t3WTD0Ndb/cxe9xiLNOxN0gvAIBfF+FfMaFAM+a6424WWDyLp89GoUkT3L1RTgeF9RrM0a4nCxtEnI4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301522; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ttYhn+nxYV7THJXOANMUgfsxcJMG45b4A8vkhxzLY6E=; b=JyqijDe8dtBSw0Hd9T6jxBugp3TAIN6OyRmiCp+xjzStYW9BrFSsn85F9LXJZOatIDCc/RoOjn1mh5/i5WeyodxW3GYxQsOKL8HAWHpEmz06W+p6u6b6pVEUbSi4Vh+baaizDhavEYOPCOliXSJByJiPOePcsYlvjGUNVnOcMTs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790301522039736.9010737946177; Thu, 24 Sep 2026 18:58:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9vAD-0005vV-BW; Thu, 24 Sep 2026 21:55:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9vAA-0005o3-OI for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:46 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9vA8-0006Bl-6Z for qemu-devel@nongnu.org; Thu, 24 Sep 2026 21:55:46 -0400 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1kYCn843473 for ; Fri, 25 Sep 2026 01:55:42 GMT Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw874hjsq-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 01:55:42 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-338c2e27430so377883eec.0 for ; Thu, 24 Sep 2026 18:55:42 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301524180158500 Keep HVX lanes host-native while converting byte indexes at memory and helper boundaries. Also place vector comparison predicate bytes according to host word order. Suggested-by: Anton Johansson Reviewed-by: Anton Johansson Reviewed-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- target/hexagon/mmvec/macros.h | 23 +++++++++++++++-------- target/hexagon/mmvec/mmvec.h | 18 ++++++++++++++++++ target/hexagon/cpu.c | 16 ++++++++++------ target/hexagon/genptr.c | 3 ++- target/hexagon/mmvec/system_ext_mmvec.c | 2 +- target/hexagon/op_helper.c | 17 ++++++++++++----- 6 files changed, 58 insertions(+), 21 deletions(-) diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index df695d0731c..5e346b7296f 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -53,7 +53,7 @@ =20 #define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \ do { \ - env->vtcm_log.data.ub[IDX] =3D (VAL); \ + hexagon_mmvec_set_byte(&env->vtcm_log.data, IDX, VAL); \ if (MASK) { \ set_bit((IDX), env->vtcm_log.mask); \ } else { \ @@ -133,7 +133,8 @@ target_ulong va_high =3D EA + LEN; \ for (int i0 =3D 0; i0 < 4; i0++) { \ log_byte =3D (va + i0) <=3D va_high; \ - LOG_VTCM_BYTE(va + i0, log_byte, INC. ub[4 * IDX + i0], \ + LOG_VTCM_BYTE(va + i0, log_byte, \ + hexagon_mmvec_get_byte(&(INC), 4 * IDX + i0), \ 4 * IDX + i0); \ } \ } while (0) @@ -144,7 +145,8 @@ target_ulong va_high =3D EA + LEN; \ for (int i0 =3D 0; i0 < 2; i0++) { \ log_byte =3D (va + i0) <=3D va_high; \ - LOG_VTCM_BYTE(va + i0, log_byte, INC.ub[2 * IDX + i0], \ + LOG_VTCM_BYTE(va + i0, log_byte, \ + hexagon_mmvec_get_byte(&(INC), 2 * IDX + i0), \ 2 * IDX + i0); \ } \ } while (0) @@ -157,7 +159,8 @@ target_ulong va_high =3D EA + LEN; \ for (int i0 =3D 0; i0 < 2; i0++) { \ log_byte =3D (va + i0) <=3D va_high; \ - LOG_VTCM_BYTE(va + i0, log_byte, INC.ub[2 * IDX + i0], \ + LOG_VTCM_BYTE(va + i0, log_byte, \ + hexagon_mmvec_get_byte(&(INC), 2 * IDX + i0), \ 2 * IDX + i0); \ } \ } while (0) @@ -174,7 +177,8 @@ log_byte =3D ((va + i0) <=3D va_high) && QVAL; \ uint8_t B; \ B =3D cpu_ldub_data_ra(env, EA + i0, ra); \ - env->tmp_VRegs[0].ub[ELEMENT_SIZE * IDX + i0] =3D B; \ + hexagon_mmvec_set_byte(&env->tmp_VRegs[0], \ + ELEMENT_SIZE * IDX + i0, B); \ LOG_VTCM_BYTE(va + i0, log_byte, B, ELEMENT_SIZE * IDX + i0); \ } \ } while (0) @@ -216,9 +220,10 @@ uint8_t val; \ val =3D cpu_ldub_data_ra(env, env->vtcm_log.va[i + j],= ra); \ dst |=3D val << (8 * j); \ - inc |=3D env->vtcm_log.data.ub[j + i] << (8 * j); \ + inc |=3D hexagon_mmvec_get_byte(&env->vtcm_log.data, j= + i) \ + << (8 * j); \ clear_bit(j + i, env->vtcm_log.mask); \ - env->vtcm_log.data.ub[j + i] =3D 0; \ + hexagon_mmvec_set_byte(&env->vtcm_log.data, j + i, 0);= \ } \ dst +=3D inc; \ for (int j =3D 0; j < sizeof(TYPE); j++) { \ @@ -249,7 +254,9 @@ int log_byte =3D 0; \ for (i0 =3D 0; i0 < ELEM_SIZE; i0++) { \ log_byte =3D ((va + i0) <=3D va_high) && QVAL; \ - LOG_VTCM_BYTE(va + i0, log_byte, IN.ub[ELEM_SIZE * IDX + i0], \ + LOG_VTCM_BYTE(va + i0, log_byte, \ + hexagon_mmvec_get_byte(&(IN), \ + ELEM_SIZE * IDX + i0),= \ ELEM_SIZE * IDX + i0); \ } \ } while (0) diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h index 8e72f2f6ae7..662f9d1597e 100644 --- a/target/hexagon/mmvec/mmvec.h +++ b/target/hexagon/mmvec/mmvec.h @@ -20,6 +20,7 @@ =20 #include "exec/target_long.h" #include "qemu/bitmap.h" +#include "qemu/bitops.h" =20 #define MAX_VEC_SIZE_LOGBYTES 7 #define MAX_VEC_SIZE_BYTES (1 << MAX_VEC_SIZE_LOGBYTES) @@ -69,6 +70,23 @@ typedef union { int8_t b[MAX_VEC_SIZE_BYTES / 1 / 8]; } MMQReg; =20 +static inline uint8_t hexagon_mmvec_get_byte(const MMVector *v, size_t ind= ex) +{ + return extract64(v->ud[index / 8], (index % 8) * 8, 8); +} + +static inline void hexagon_mmvec_set_byte(MMVector *v, size_t index, + uint8_t value) +{ + v->ud[index / 8] =3D deposit64(v->ud[index / 8], (index % 8) * 8, 8, + value); +} + +static inline uint8_t hexagon_mmqreg_get_byte(const MMQReg *q, size_t inde= x) +{ + return extract32(q->uw[index / 4], (index % 4) * 8, 8); +} + typedef struct { MMVector data; DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 912bae7b6c2..1f7d8a8df70 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -192,7 +192,7 @@ static void print_vreg(FILE *f, CPUHexagonState *env, i= nt regnum, if (skip_if_zero) { bool nonzero_found =3D false; for (int i =3D 0; i < MAX_VEC_SIZE_BYTES; i++) { - if (hex_hvx(env)->VRegs[regnum].ub[i] !=3D 0) { + if (hexagon_mmvec_get_byte(&hex_hvx(env)->VRegs[regnum], i) != =3D 0) { nonzero_found =3D true; break; } @@ -204,9 +204,11 @@ static void print_vreg(FILE *f, CPUHexagonState *env, = int regnum, =20 qemu_fprintf(f, " v%d =3D ( ", regnum); qemu_fprintf(f, "0x%02x", - hex_hvx(env)->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]); + hexagon_mmvec_get_byte(&hex_hvx(env)->VRegs[regnum], + MAX_VEC_SIZE_BYTES - 1)); for (int i =3D MAX_VEC_SIZE_BYTES - 2; i >=3D 0; i--) { - qemu_fprintf(f, ", 0x%02x", hex_hvx(env)->VRegs[regnum].ub[i]); + qemu_fprintf(f, ", 0x%02x", + hexagon_mmvec_get_byte(&hex_hvx(env)->VRegs[regnum], = i)); } qemu_fprintf(f, " )\n"); } @@ -222,7 +224,7 @@ static void print_qreg(FILE *f, CPUHexagonState *env, i= nt regnum, if (skip_if_zero) { bool nonzero_found =3D false; for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { - if (hex_hvx(env)->QRegs[regnum].ub[i] !=3D 0) { + if (hexagon_mmqreg_get_byte(&hex_hvx(env)->QRegs[regnum], i) != =3D 0) { nonzero_found =3D true; break; } @@ -234,9 +236,11 @@ static void print_qreg(FILE *f, CPUHexagonState *env, = int regnum, =20 qemu_fprintf(f, " q%d =3D ( ", regnum); qemu_fprintf(f, "0x%02x", - hex_hvx(env)->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1= ]); + hexagon_mmqreg_get_byte(&hex_hvx(env)->QRegs[regnum], + MAX_VEC_SIZE_BYTES / 8 - 1)); for (int i =3D MAX_VEC_SIZE_BYTES / 8 - 2; i >=3D 0; i--) { - qemu_fprintf(f, ", 0x%02x", hex_hvx(env)->QRegs[regnum].ub[i]); + qemu_fprintf(f, ", 0x%02x", + hexagon_mmqreg_get_byte(&hex_hvx(env)->QRegs[regnum],= i)); } qemu_fprintf(f, " )\n"); } diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index e1330d8e0b2..cd4ae2f6838 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -1590,7 +1590,8 @@ static void vec_to_qvec(size_t size, TCGv_ptr dstbase= , intptr_t dstoff, tcg_gen_deposit_i64(mask, mask, bits, j, size); } =20 - tcg_gen_st8_i64(mask, dstbase, dstoff + i); + tcg_gen_st8_i64(mask, dstbase, + dstoff + (i ^ (HOST_BIG_ENDIAN ? 3 : 0))); } } =20 diff --git a/target/hexagon/mmvec/system_ext_mmvec.c b/target/hexagon/mmvec= /system_ext_mmvec.c index 8351f2cc01b..081cadd814a 100644 --- a/target/hexagon/mmvec/system_ext_mmvec.c +++ b/target/hexagon/mmvec/system_ext_mmvec.c @@ -26,7 +26,7 @@ void mem_gather_store(CPUHexagonState *env, target_ulong = vaddr, int slot) env->vstore_pending[slot] =3D 1; env->vstore[slot].va =3D vaddr; env->vstore[slot].size =3D size; - memcpy(&env->vstore[slot].data.ub[0], &env->tmp_VRegs[0], size); + memcpy(&env->vstore[slot].data, &env->tmp_VRegs[0], size); =20 /* On a gather store, overwrite the store mask to emulate dropped gath= ers */ bitmap_copy(env->vstore[slot].mask, env->vtcm_log.mask, size); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 47c7953b92e..4f00ca773f3 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -168,7 +168,10 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env) int size =3D env->vstore[i].size; for (int j =3D 0; j < size; j++) { if (test_bit(j, env->vstore[i].mask)) { - cpu_stb_data_ra(env, va + j, env->vstore[i].data.ub[j]= , ra); + cpu_stb_data_ra(env, va + j, + hexagon_mmvec_get_byte(&env->vstore[i]= .data, + j), + ra); } } } @@ -191,9 +194,11 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env) for (int i =3D 0; i < sizeof(MMVector); i++) { if (test_bit(i, env->vtcm_log.mask)) { cpu_stb_data_ra(env, env->vtcm_log.va[i], - env->vtcm_log.data.ub[i], ra); + hexagon_mmvec_get_byte(&env->vtcm_log= .data, + i), + ra); clear_bit(i, env->vtcm_log.mask); - env->vtcm_log.data.ub[i] =3D 0; + hexagon_mmvec_set_byte(&env->vtcm_log.data, i, 0); } =20 } @@ -1404,7 +1409,8 @@ void HELPER(vhist)(CPUHexagonState *env) =20 for (int lane =3D 0; lane < 8; lane++) { for (int i =3D 0; i < sizeof(MMVector) / 8; ++i) { - unsigned char value =3D input->ub[(sizeof(MMVector) / 8) * lan= e + i]; + unsigned char value =3D hexagon_mmvec_get_byte(input, + (sizeof(MMVector) / 8) * lane + i); unsigned char regno =3D value >> 3; unsigned char element =3D value & 7; =20 @@ -1420,7 +1426,8 @@ void HELPER(vhistq)(CPUHexagonState *env) =20 for (int lane =3D 0; lane < 8; lane++) { for (int i =3D 0; i < sizeof(MMVector) / 8; ++i) { - unsigned char value =3D input->ub[(sizeof(MMVector) / 8) * lan= e + i]; + unsigned char value =3D hexagon_mmvec_get_byte(input, + (sizeof(MMVector) / 8) * lane + i); unsigned char regno =3D value >> 3; unsigned char element =3D value & 7; =20 --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301467632158500 The region-length bounds check compared (EA + i0) <=3D (EA + LEN), which reduces to i0 <=3D LEN and never actually depends on the region base. This let vgather/vscatter keep elements whose offset was beyond the declared region instead of dropping them. Compare the offset to the region length directly instead. Only load bytes for gather lanes that are kept. A dropped or predicate-false lane must not access memory and raise an exception. Reviewed-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- target/hexagon/mmvec/macros.h | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index 5e346b7296f..f85d99735d2 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -130,9 +130,9 @@ do { \ int log_byte =3D 0; \ target_ulong va =3D EA; \ - target_ulong va_high =3D EA + LEN; \ + int in_region =3D (OFFSET) <=3D (LEN); \ for (int i0 =3D 0; i0 < 4; i0++) { \ - log_byte =3D (va + i0) <=3D va_high; \ + log_byte =3D in_region; \ LOG_VTCM_BYTE(va + i0, log_byte, \ hexagon_mmvec_get_byte(&(INC), 4 * IDX + i0), \ 4 * IDX + i0); \ @@ -142,9 +142,9 @@ do { \ int log_byte =3D 0; \ target_ulong va =3D EA; \ - target_ulong va_high =3D EA + LEN; \ + int in_region =3D (OFFSET) <=3D (LEN); \ for (int i0 =3D 0; i0 < 2; i0++) { \ - log_byte =3D (va + i0) <=3D va_high; \ + log_byte =3D in_region; \ LOG_VTCM_BYTE(va + i0, log_byte, \ hexagon_mmvec_get_byte(&(INC), 2 * IDX + i0), \ 2 * IDX + i0); \ @@ -156,9 +156,9 @@ do { \ int log_byte =3D 0; \ target_ulong va =3D EA; \ - target_ulong va_high =3D EA + LEN; \ + int in_region =3D (OFFSET) <=3D (LEN); \ for (int i0 =3D 0; i0 < 2; i0++) { \ - log_byte =3D (va + i0) <=3D va_high; \ + log_byte =3D in_region; \ LOG_VTCM_BYTE(va + i0, log_byte, \ hexagon_mmvec_get_byte(&(INC), 2 * IDX + i0), \ 2 * IDX + i0); \ @@ -170,15 +170,18 @@ do { \ int i0; \ target_ulong va =3D EA; \ - target_ulong va_high =3D EA + LEN; \ uintptr_t ra =3D GETPC(); \ int log_byte =3D 0; \ + int in_region =3D (OFFSET) <=3D (LEN); \ for (i0 =3D 0; i0 < ELEMENT_SIZE; i0++) { \ - log_byte =3D ((va + i0) <=3D va_high) && QVAL; \ - uint8_t B; \ - B =3D cpu_ldub_data_ra(env, EA + i0, ra); \ - hexagon_mmvec_set_byte(&env->tmp_VRegs[0], \ - ELEMENT_SIZE * IDX + i0, B); \ + uint8_t B =3D 0; \ + \ + log_byte =3D in_region && QVAL; \ + if (log_byte) { \ + B =3D cpu_ldub_data_ra(env, va + i0, ra); \ + hexagon_mmvec_set_byte(&env->tmp_VRegs[0], \ + ELEMENT_SIZE * IDX + i0, B); \ + } \ LOG_VTCM_BYTE(va + i0, log_byte, B, ELEMENT_SIZE * IDX + i0); \ } \ } while (0) @@ -250,10 +253,10 @@ do { \ int i0; \ target_ulong va =3D EA; \ - target_ulong va_high =3D EA + LEN; \ int log_byte =3D 0; \ + int in_region =3D (OFFSET) <=3D (LEN); \ for (i0 =3D 0; i0 < ELEM_SIZE; i0++) { \ - log_byte =3D ((va + i0) <=3D va_high) && QVAL; \ + log_byte =3D in_region && QVAL; \ LOG_VTCM_BYTE(va + i0, log_byte, \ hexagon_mmvec_get_byte(&(IN), \ ELEM_SIZE * IDX + i0),= \ --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301530; cv=none; d=zohomail.com; s=zohoarc; b=bRIjCedYBmxA+udyE49PrzE2B4Tg0fNOnTO2nCrz4hVsCTvzhIS+wsbapS7E4/XvPJP//76KJtym47LUW6e7ykN+XRHyygMrCkJGw+18Ielcx06N9Z5w3SaNIg2QmAHOZ6RL7YQNY8iquHl+gcWUh3jfK7hpj8S/m9spL9xH0u4= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301531956158500 Cover the case where an offset lies beyond the region length: it must be dropped rather than read/written. Place one dropped gather offset on a PROT_NONE page to verify that the instruction does not access memory for that lane. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/scatter_gather.c | 137 ++++++++++++++++++++++++++++- 1 file changed, 136 insertions(+), 1 deletion(-) diff --git a/tests/tcg/hexagon/scatter_gather.c b/tests/tcg/hexagon/scatter= _gather.c index bf8b5e03172..40f00cc6cf5 100644 --- a/tests/tcg/hexagon/scatter_gather.c +++ b/tests/tcg/hexagon/scatter_gather.c @@ -31,7 +31,11 @@ #include #include #include +#include #include +#include +#include +#include =20 typedef long HVX_Vector __attribute__((__vector_size__(128))) __attribute__((aligned(128))); @@ -85,6 +89,23 @@ unsigned int word_predicates[MATRIX_SIZE] __attribute_= _((aligned(128))); /* make this big enough for all the operations */ const size_t region_len =3D sizeof(vtcm); =20 +/* Mu (region length - 1); offset is kept iff offset <=3D Mu */ +#define REGION_LEN_TEST_MU 127 +#define GATHER_LEN_TEST_PAGE_SIZE 4096 +static unsigned char *gather_len_test_src; +static unsigned char gather_len_test_dst[128] __attribute__((aligned(128))= ); +static unsigned char gather_len_test_dst_ref[128]; + +/* The dropped offset must remain in the backing destination buffer. */ +#define SCATTER_LEN_TEST_DST_SIZE 512 +static unsigned char scatter_len_test_dst[SCATTER_LEN_TEST_DST_SIZE] + __attribute__((aligned(128))); +static unsigned char scatter_len_test_dst_ref[SCATTER_LEN_TEST_DST_SIZE]; +static unsigned short region_len_test_offsets[MATRIX_SIZE] + __attribute__((aligned(128))); +static unsigned short scatter_len_test_values[MATRIX_SIZE] + __attribute__((aligned(128))); + /* optionally add sync instructions */ #define SYNC_VECTOR 1 =20 @@ -96,7 +117,7 @@ static void sync_scatter(void *addr) * synchronization. Normally the dummy load would be deferred as * long as possible to minimize stalls. */ - asm volatile("vmem(%0 + #0):scatter_release\n" : : "r"(addr)); + asm volatile("vmem(%[addr] + #0):scatter_release\n" : : [addr] "r"(add= r)); /* use volatile to force the load */ volatile HVX_Vector vDummy =3D *(HVX_Vector *)addr; vDummy =3D vDummy; #endif @@ -855,6 +876,112 @@ void check_gather_16_32_masked(void) MATRIX_SIZE * sizeof(unsigned short)); } =20 +static void init_region_len_test_offsets(void) +{ + memset(region_len_test_offsets, 0, sizeof(region_len_test_offsets)); + region_len_test_offsets[0] =3D 0; /* in region */ + region_len_test_offsets[1] =3D REGION_LEN_TEST_MU - 1; /* in region */ + region_len_test_offsets[2] =3D REGION_LEN_TEST_MU; /* in region */ + region_len_test_offsets[3] =3D REGION_LEN_TEST_MU + 1; /* dropped */ + region_len_test_offsets[4] =3D 256; /* dropped */ +} + +/* vgather must drop elements whose offset is beyond the region */ +void create_gather_region_len_test(void) +{ + unsigned char *mapping; + + mapping =3D mmap(NULL, 2 * GATHER_LEN_TEST_PAGE_SIZE, + PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + assert(mapping !=3D MAP_FAILED); + assert(mprotect(mapping + GATHER_LEN_TEST_PAGE_SIZE, + GATHER_LEN_TEST_PAGE_SIZE, PROT_NONE) =3D=3D 0); + gather_len_test_src =3D mapping + GATHER_LEN_TEST_PAGE_SIZE - 256; + + for (int i =3D 0; i < 256; i++) { + gather_len_test_src[i] =3D (unsigned char)(13 + 7 * i); + } + init_region_len_test_offsets(); + memset(gather_len_test_dst, FILL_CHAR, sizeof(gather_len_test_dst)); +} + +/* gather with a region shorter than the source buffer, using HVX */ +void vector_gather_region_len(void) +{ + HVX_Vector voff =3D *(HVX_Vector *)region_len_test_offsets; + + Q6_vgather_ARMVh((HVX_Vector *)gather_len_test_dst, + (int)(uintptr_t)gather_len_test_src, + REGION_LEN_TEST_MU, voff); + + sync_gather(gather_len_test_dst); +} + +/* gather with a region shorter than the source buffer, using C */ +void scalar_gather_region_len(unsigned char *dst) +{ + for (int i =3D 0; i < MATRIX_SIZE; i++) { + unsigned short off =3D region_len_test_offsets[i]; + if (off <=3D REGION_LEN_TEST_MU) { + dst[2 * i] =3D gather_len_test_src[off]; + dst[2 * i + 1] =3D gather_len_test_src[off + 1]; + } + } +} + +void check_gather_region_len(void) +{ + memset(gather_len_test_dst_ref, FILL_CHAR, + sizeof(gather_len_test_dst_ref)); + scalar_gather_region_len(gather_len_test_dst_ref); + check_buffer(__func__, gather_len_test_dst, gather_len_test_dst_ref, + sizeof(gather_len_test_dst_ref)); +} + +/* vscatter must drop elements whose offset is beyond the region */ +void create_scatter_region_len_test(void) +{ + init_region_len_test_offsets(); + for (int i =3D 0; i < MATRIX_SIZE; i++) { + scatter_len_test_values[i] =3D 0x4100 + i; + } + memset(scatter_len_test_dst, FILL_CHAR, sizeof(scatter_len_test_dst)); +} + +/* scatter with a region shorter than the destination buffer, using HVX */ +void vector_scatter_region_len(void) +{ + HVX_Vector voff =3D *(HVX_Vector *)region_len_test_offsets; + HVX_Vector vval =3D *(HVX_Vector *)scatter_len_test_values; + + Q6_vscatter_RMVhV((int)(uintptr_t)scatter_len_test_dst, + REGION_LEN_TEST_MU, voff, vval); + + sync_scatter(scatter_len_test_dst); +} + +/* scatter with a region shorter than the destination buffer, using C */ +void scalar_scatter_region_len(unsigned char *dst) +{ + for (int i =3D 0; i < MATRIX_SIZE; i++) { + unsigned short off =3D region_len_test_offsets[i]; + if (off <=3D REGION_LEN_TEST_MU) { + memcpy(dst + off, &scatter_len_test_values[i], + sizeof(scatter_len_test_values[i])); + } + } +} + +void check_scatter_region_len(void) +{ + memset(scatter_len_test_dst_ref, FILL_CHAR, + sizeof(scatter_len_test_dst_ref)); + scalar_scatter_region_len(scatter_len_test_dst_ref); + check_buffer(__func__, scatter_len_test_dst, scatter_len_test_dst_ref, + sizeof(scatter_len_test_dst_ref)); +} + /* print scatter16 buffer */ void print_scatter16_buffer(void) { @@ -1035,6 +1162,14 @@ int main() print_scatter16_32_buffer(); check_scatter_16_32_masked(); =20 + create_gather_region_len_test(); + vector_gather_region_len(); + check_gather_region_len(); + + create_scatter_region_len_test(); + vector_scatter_region_len(); + check_scatter_region_len(); + puts(err ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301361442158500 Content-Type: text/plain; charset="utf-8" The masked histogram instructions save the predicate operand to the qtmp temporary with a gvec move sized sizeof(MMVector). Both source and destination are MMQReg, which is eight times smaller, so the move read 112 bytes past the predicate register and wrote them over the fields following qtmp in CPUHexagonState, that is vstore[0]. Use the size of the registers actually being copied. Fixes: 7ba7657bc93 ("Hexagon HVX helper overrides for histogram instructio= ns") Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain --- target/hexagon/gen_tcg_hvx.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h index f399291dc66..548b49b4156 100644 --- a/target/hexagon/gen_tcg_hvx.h +++ b/target/hexagon/gen_tcg_hvx.h @@ -50,7 +50,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ - sizeof(MMVector), sizeof(MMVector)); \ + sizeof(MMQReg), sizeof(MMQReg)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vhistq(tcg_env); \ @@ -66,7 +66,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ - sizeof(MMVector), sizeof(MMVector)); \ + sizeof(MMQReg), sizeof(MMQReg)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vwhist256q(tcg_env); \ @@ -82,7 +82,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ - sizeof(MMVector), sizeof(MMVector)); \ + sizeof(MMQReg), sizeof(MMQReg)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vwhist256q_sat(tcg_env); \ @@ -98,7 +98,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ - sizeof(MMVector), sizeof(MMVector)); \ + sizeof(MMQReg), sizeof(MMQReg)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vwhist128q(tcg_env); \ @@ -115,7 +115,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ - sizeof(MMVector), sizeof(MMVector)); \ + sizeof(MMQReg), sizeof(MMQReg)); \ } else { \ TCGv tcgv_uiV =3D tcg_constant_tl(uiV); \ assert_vhist_tmp(ctx); \ --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790301507; cv=none; d=zohomail.com; s=zohoarc; b=KBZFBwmzjT1yD+Pvqk2Qqk3bLkfOwUo7IGNvYDV/zSjuoFyrrmvd8GGopBO79jcnt8mGSJVsrTsn354PffAHngcWbk722VhUVsPu0Fwblg5JQqwbCyPk9F/oUkiW7EOU2iRgMZRj0DUprq13ubEpI0jZ9nRmVZtt5roST1edbyY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790301507; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790301507802158500 A Q reg can be built by a vector compare or by vand(Vu, Rt), and those reach the predicate register through independent code paths. Check that both select the same byte lanes, so a byte-order mistake in either one is caught. The input alternates every eight lanes: a flatter pattern stays unchanged when predicate bytes are permuted and hides the bug. Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- tests/tcg/hexagon/hvx_misc.c | 45 ++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c index 0285886c2a5..425baee7a30 100644 --- a/tests/tcg/hexagon/hvx_misc.c +++ b/tests/tcg/hexagon/hvx_misc.c @@ -181,6 +181,50 @@ static void test_store_unaligned(void) check_output_w(__LINE__, 2); } =20 +/* + * A Q register can be built either by a vector compare or by vand(Vu, Rt). + * Those are two independent code paths onto the same predicate-register + * layout, so cross-check that they select exactly the same byte lanes. + * A byte-order mistake in either one shows up here as a mismatch. + * + * The input pattern has to vary across 8-lane blocks, otherwise a predica= te + * whose bytes are permuted still selects the same lanes and the mismatch = is + * invisible. + */ +static void test_qreg_alias(void) +{ + HVX_Vector *pcmp =3D (HVX_Vector *)&output[0]; + HVX_Vector *pand =3D (HVX_Vector *)&output[1]; + HVX_Vector input; + HVX_Vector ones; + HVX_VectorPred qcmp; + HVX_VectorPred qand; + + for (int i =3D 0; i < BUFSIZE; i++) { + /* + * Build 0/1 per byte, alternating every 8 lanes, so that "!=3D 0"= and + * "low bit set" describe the same lanes. Then form one predicate + * with a compare and the other with vand(Vu, Rt), store 0xff thro= ugh + * each, and require the two result vectors to be identical. + */ + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES; j++) { + expect[0].ub[j] =3D ((j >> 3) + i) & 1; + } + memcpy(&input, &expect[0], sizeof(MMVector)); + memset(output, 0, 2 * sizeof(MMVector)); + + ones =3D Q6_V_vsplat_R(0xffffffff); + qcmp =3D Q6_Q_vcmp_gt_VubVub(input, Q6_V_vzero()); + qand =3D Q6_Q_vand_VR(input, 0x01010101); + Q6_vmem_QRIV(qcmp, pcmp, ones); + Q6_vmem_QRIV(qand, pand, ones); + + for (int j =3D 0; j < MAX_VEC_SIZE_BYTES; j++) { + check(__LINE__, i, j, output[0].ub[j], output[1].ub[j]); + } + } +} + static void test_masked_store(bool invert) { void *p0 =3D buffer0; @@ -642,6 +686,7 @@ int main() test_store_unaligned(); test_masked_store(false); test_masked_store(true); + test_qreg_alias(); test_new_value_store(); test_max_temps(); =20 --=20 2.34.1 From nobody Sat Sep 26 19:12:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1790303207; cv=none; d=zohomail.com; s=zohoarc; b=BjKclD+HOpDoLhvzpSHjMWpPqrxNb59q/btl6ZI0FltaKy4psi6dTMGoeJjikZlIh2j5dK4q+HGIU6OCALe5Qr2ylUjc5nJKK3/X5mORxu1y0bihX2z5QVi4FwOBaxVuunDpH+wX5f5NU04YAyUXuAi0w+R5bS0gpiw+7Abt30g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1790303207; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=F0fNILJeSQGwqAxngRB09jlDZ2G63LIowNuVxxlCX/Y=; b=aaBcWENa9UcZhFaL1Bo7ioNpfMZ0dO8zR301z84avrBrZaKCBRfh1BviitkkgPCPnSQNiMMecg85sBvCNLdhzlWR3xXgFT9MrhlHqn1Zq6TJ7pQ/uq7/O9Sxg2JwsKpVa1UzDv4gf+/HsVZ8wUQ5cxxzhJr/hju75z0dPknbYpU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1790303207264139.90766417440216; Thu, 24 Sep 2026 19:26:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x9vdP-0006z0-7k; Thu, 24 Sep 2026 22:25:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9vdM-0006ym-K8 for qemu-devel@nongnu.org; Thu, 24 Sep 2026 22:25:56 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x9vdJ-0008Tr-6X for qemu-devel@nongnu.org; Thu, 24 Sep 2026 22:25:55 -0400 Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68P1kmm33884076 for ; Fri, 25 Sep 2026 02:25:50 GMT Received: from mail-dy1-f198.google.com (mail-dy1-f198.google.com [74.125.82.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gw4652uef-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 25 Sep 2026 02:25:50 +0000 (GMT) Received: by mail-dy1-f198.google.com with SMTP id 5a478bee46e88-30c0d568830so760393eec.1 for ; Thu, 24 Sep 2026 19:25:50 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1790303210503158500 LEN suggested a region size, but the parameter is actually the region's last valid byte offset. Rename it to OFFS_REG_END to make the semantics clearer. Link: https://lore.kernel.org/qemu-devel/63513430-7bd1-486c-b693-49d1076562= ed@oss.qualcomm.com/ Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- target/hexagon/mmvec/macros.h | 76 +++++++++++++++++++---------------- 1 file changed, 42 insertions(+), 34 deletions(-) diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index f85d99735d2..4ac53aca0b9 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -126,11 +126,12 @@ env->vtcm_log.op =3D true; \ env->vtcm_log.op_size =3D SIZE; \ } while (0) -#define fVLOG_VTCM_WORD_INCREMENT(EA, OFFSET, INC, IDX, ALIGNMENT, LEN) \ +#define fVLOG_VTCM_WORD_INCREMENT(EA, OFFSET, INC, IDX, ALIGNMENT, \ + OFFS_REG_END) \ do { \ int log_byte =3D 0; \ target_ulong va =3D EA; \ - int in_region =3D (OFFSET) <=3D (LEN); \ + int in_region =3D (OFFSET) <=3D (OFFS_REG_END); \ for (int i0 =3D 0; i0 < 4; i0++) { \ log_byte =3D in_region; \ LOG_VTCM_BYTE(va + i0, log_byte, \ @@ -138,11 +139,12 @@ 4 * IDX + i0); \ } \ } while (0) -#define fVLOG_VTCM_HALFWORD_INCREMENT(EA, OFFSET, INC, IDX, ALIGNMENT, LEN= ) \ +#define fVLOG_VTCM_HALFWORD_INCREMENT(EA, OFFSET, INC, IDX, ALIGNMENT, \ + OFFS_REG_END) \ do { \ int log_byte =3D 0; \ target_ulong va =3D EA; \ - int in_region =3D (OFFSET) <=3D (LEN); \ + int in_region =3D (OFFSET) <=3D (OFFS_REG_END); \ for (int i0 =3D 0; i0 < 2; i0++) { \ log_byte =3D in_region; \ LOG_VTCM_BYTE(va + i0, log_byte, \ @@ -152,11 +154,11 @@ } while (0) =20 #define fVLOG_VTCM_HALFWORD_INCREMENT_DV(EA, OFFSET, INC, IDX, IDX2, IDX_H= , \ - ALIGNMENT, LEN) \ + ALIGNMENT, OFFS_REG_END) \ do { \ int log_byte =3D 0; \ target_ulong va =3D EA; \ - int in_region =3D (OFFSET) <=3D (LEN); \ + int in_region =3D (OFFSET) <=3D (OFFS_REG_END); \ for (int i0 =3D 0; i0 < 2; i0++) { \ log_byte =3D in_region; \ LOG_VTCM_BYTE(va + i0, log_byte, \ @@ -166,13 +168,14 @@ } while (0) =20 /* NOTE - Will this always be tmp_VRegs[0]; */ -#define GATHER_FUNCTION(EA, OFFSET, IDX, LEN, ELEMENT_SIZE, BANK_IDX, QVAL= ) \ +#define GATHER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, ELEMENT_SIZE, \ + BANK_IDX, QVAL) \ do { \ int i0; \ target_ulong va =3D EA; \ uintptr_t ra =3D GETPC(); \ int log_byte =3D 0; \ - int in_region =3D (OFFSET) <=3D (LEN); \ + int in_region =3D (OFFSET) <=3D (OFFS_REG_END); \ for (i0 =3D 0; i0 < ELEMENT_SIZE; i0++) { \ uint8_t B =3D 0; \ \ @@ -185,31 +188,34 @@ LOG_VTCM_BYTE(va + i0, log_byte, B, ELEMENT_SIZE * IDX + i0); \ } \ } while (0) -#define fVLOG_VTCM_GATHER_WORD(EA, OFFSET, IDX, LEN) \ +#define fVLOG_VTCM_GATHER_WORD(EA, OFFSET, IDX, OFFS_REG_END) \ do { \ - GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, 1); \ + GATHER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 4, IDX, 1); \ } while (0) -#define fVLOG_VTCM_GATHER_HALFWORD(EA, OFFSET, IDX, LEN) \ +#define fVLOG_VTCM_GATHER_HALFWORD(EA, OFFSET, IDX, OFFS_REG_END) \ do { \ - GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, 1); \ + GATHER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 2, IDX, 1); \ } while (0) -#define fVLOG_VTCM_GATHER_HALFWORD_DV(EA, OFFSET, IDX, IDX2, IDX_H, LEN) \ +#define fVLOG_VTCM_GATHER_HALFWORD_DV(EA, OFFSET, IDX, IDX2, IDX_H, \ + OFFS_REG_END) \ do { \ - GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, (2 * IDX2 + IDX_H), 1); \ + GATHER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 2, \ + (2 * IDX2 + IDX_H), 1); \ } while (0) -#define fVLOG_VTCM_GATHER_WORDQ(EA, OFFSET, IDX, Q, LEN) \ +#define fVLOG_VTCM_GATHER_WORDQ(EA, OFFSET, IDX, Q, OFFS_REG_END) \ do { \ - GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, \ + GATHER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 4, IDX, \ fGETQBIT(QsV, 4 * IDX + i0)); \ } while (0) -#define fVLOG_VTCM_GATHER_HALFWORDQ(EA, OFFSET, IDX, Q, LEN) \ +#define fVLOG_VTCM_GATHER_HALFWORDQ(EA, OFFSET, IDX, Q, OFFS_REG_END) \ do { \ - GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, \ + GATHER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 2, IDX, \ fGETQBIT(QsV, 2 * IDX + i0)); \ } while (0) -#define fVLOG_VTCM_GATHER_HALFWORDQ_DV(EA, OFFSET, IDX, IDX2, IDX_H, Q, LE= N) \ +#define fVLOG_VTCM_GATHER_HALFWORDQ_DV(EA, OFFSET, IDX, IDX2, IDX_H, Q, \ + OFFS_REG_END) \ do { \ - GATHER_FUNCTION(EA, OFFSET, IDX, LEN, 2, (2 * IDX2 + IDX_H), \ + GATHER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 2, (2 * IDX2 + IDX_= H), \ fGETQBIT(QsV, 2 * IDX + i0)); \ } while (0) #define SCATTER_OP_WRITE_TO_MEM(TYPE) \ @@ -249,12 +255,13 @@ } \ } \ } while (0) -#define SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, ELEM_SIZE, BANK_IDX, QVAL, = IN) \ +#define SCATTER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, ELEM_SIZE, \ + BANK_IDX, QVAL, IN) \ do { \ int i0; \ target_ulong va =3D EA; \ int log_byte =3D 0; \ - int in_region =3D (OFFSET) <=3D (LEN); \ + int in_region =3D (OFFSET) <=3D (OFFS_REG_END); \ for (i0 =3D 0; i0 < ELEM_SIZE; i0++) { \ log_byte =3D in_region && QVAL; \ LOG_VTCM_BYTE(va + i0, log_byte, \ @@ -263,32 +270,33 @@ ELEM_SIZE * IDX + i0); \ } \ } while (0) -#define fVLOG_VTCM_HALFWORD(EA, OFFSET, IN, IDX, LEN) \ +#define fVLOG_VTCM_HALFWORD(EA, OFFSET, IN, IDX, OFFS_REG_END) \ do { \ - SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, 1, IN); \ + SCATTER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 2, IDX, 1, IN); \ } while (0) -#define fVLOG_VTCM_WORD(EA, OFFSET, IN, IDX, LEN) \ +#define fVLOG_VTCM_WORD(EA, OFFSET, IN, IDX, OFFS_REG_END) \ do { \ - SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, 1, IN); \ + SCATTER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 4, IDX, 1, IN); \ } while (0) -#define fVLOG_VTCM_HALFWORDQ(EA, OFFSET, IN, IDX, Q, LEN) \ +#define fVLOG_VTCM_HALFWORDQ(EA, OFFSET, IN, IDX, Q, OFFS_REG_END) \ do { \ - SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, IDX, \ + SCATTER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 2, IDX, \ fGETQBIT(QsV, 2 * IDX + i0), IN); \ } while (0) -#define fVLOG_VTCM_WORDQ(EA, OFFSET, IN, IDX, Q, LEN) \ +#define fVLOG_VTCM_WORDQ(EA, OFFSET, IN, IDX, Q, OFFS_REG_END) \ do { \ - SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 4, IDX, \ + SCATTER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 4, IDX, \ fGETQBIT(QsV, 4 * IDX + i0), IN); \ } while (0) -#define fVLOG_VTCM_HALFWORD_DV(EA, OFFSET, IN, IDX, IDX2, IDX_H, LEN) \ +#define fVLOG_VTCM_HALFWORD_DV(EA, OFFSET, IN, IDX, IDX2, IDX_H, OFFS_REG_= END) \ do { \ - SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, \ + SCATTER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 2, \ (2 * IDX2 + IDX_H), 1, IN); \ } while (0) -#define fVLOG_VTCM_HALFWORDQ_DV(EA, OFFSET, IN, IDX, Q, IDX2, IDX_H, LEN) \ +#define fVLOG_VTCM_HALFWORDQ_DV(EA, OFFSET, IN, IDX, Q, IDX2, IDX_H, \ + OFFS_REG_END) \ do { \ - SCATTER_FUNCTION(EA, OFFSET, IDX, LEN, 2, (2 * IDX2 + IDX_H), \ + SCATTER_FUNCTION(EA, OFFSET, IDX, OFFS_REG_END, 2, (2 * IDX2 + IDX= _H), \ fGETQBIT(QsV, 2 * IDX + i0), IN); \ } while (0) #define fSTORERELEASE(EA, TYPE) \ --=20 2.34.1