This RFC series refines the Armv6-M support in QEMU by correcting NVIC
limits, modelling the optional Cortex-M0+ privilege extension,
tightening MPU register access, fixing MPU region size checks, masking
TEX bits for Armv6-M, and reusing QEMU's existing PMSAv7 implementation
for the compatible v6-M MPU.
Following review of the RP2040/Pico v3 RFC, these generic Arm changes
have been split into a standalone series. While they are motivated by
the Pico bring-up effort, the patches address generic Armv6-M behaviour
and improve Arm M-profile emulation independently of the Pico machine.
They incorporate the review comments from Peter Maydell and Alex Bennee
on the RP2040/Pico v3 RFC:
Link: https://lore.kernel.org/qemu-devel/20260906194438.93046-1-gilles.grimaud@univ-lille.fr/
The RP2040/Pico machine series will be posted separately and will depend
on these generic Arm changes. The two new check-tcg tests pass with the
Arm TCG cross compiler.
The series consists of six patches:
- enforce Armv6-M NVIC limits (max 32 external interrupts, respect
reserved registers, add TCG test)
- model Cortex-M0+ privilege extension (feature bit, CPU type, allow
privileged writes to CONTROL.nPRIV when Main Extension or privilege
extension present)
- limit MPU RBAR and RASR/RLAR alias registers to the Main Extension
(reorder cases, guard with ARM_FEATURE_M_MAIN)
- mask TEX bits in MPU_RASR for Armv6-M (use mask 0x1707, preserve
Armv7-M behaviour)
- enforce the architectural minimum region sizes for v6-M, v7-M and v7-R
- extend PMSAv7 support to v6-M CPUs (widen conditionals to accept
ARM_FEATURE_M, keep PMSAv8 path for v8-M)
Together, these patches add two new TCG assembly tests
(test-armv6m-control.S and test-armv6m-nvic.S) that verify the corrected
NVIC behaviour and Cortex-M0 CONTROL.nPRIV handling, and update the
corresponding meson.build file.
The series is ready for review and testing; please send any comments or
suggestions.
Gilles Grimaud (6):
target/arm: enforce Armv6-M NVIC limits
target/arm: model Cortex-M0+ privilege extension
target/arm: MPU - limit regs RBAR/RASR A1-A3 to Main Extension
target/arm: MPU_RASR: mask TEX bits for Armv6-M
target/arm: fix MPU SIZE min for v6-M/v7-M/v7-R
target/arm: extend PMSAv7 support to v6-M CPUs
hw/intc/armv7m_nvic.c | 42 +++++++++++--
target/arm/cpu.c | 12 +++-
target/arm/cpu.h | 1 +
target/arm/machine.c | 3 +-
target/arm/ptw.c | 14 ++++-
target/arm/tcg/cpu-v7m.c | 11 ++++
target/arm/tcg/m_helper.c | 4 +-
tests/tcg/arm/system/meson.build | 12 ++++
tests/tcg/arm/system/test-armv6m-control.S | 66 ++++++++++++++++++++
tests/tcg/arm/system/test-armv6m-nvic.S | 70 ++++++++++++++++++++++
10 files changed, 222 insertions(+), 13 deletions(-)
create mode 100644 tests/tcg/arm/system/test-armv6m-control.S
create mode 100644 tests/tcg/arm/system/test-armv6m-nvic.S
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2.55.0