From nobody Sat Sep 26 21:38:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=univ-lille.fr ARC-Seal: i=1; a=rsa-sha256; t=1789413895; cv=none; d=zohomail.com; s=zohoarc; b=Hx64E0ATqMOzEbuJO6WgCojObvy4DBfwg9miPkyfLhMPUhcQDZGWLZJlZenzrjWQiQyG26yYFZRUpoDsm7ddMQTOCNHXcVMgj4o+cOObP7bFecKvrPCfV0Ujci55LPdRlEVxPTqjUIENI5xCdmqBgqd22Cd8U/UuL/XlZZlR1PM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789413895; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=eTORqgHRjvLB7Zq5ZRd5F5B/wCOqFwPXotdNGYO5WvM=; b=Tgx9y7yN9WF8E1YLoyhzjyvV2ukENcXIVbdbEUl+QykhQgiuDA6UFVZ8D0f3TwvEsSaeLw7vt46x84Igsy3kxyDvVqgMAgPgt15nyViZ62mv/jXXGN+n4DiemXP6zeMHjMWbxOCGhPkQ5okVkjAU4M2R4zo8RXthJyc4zJjLsqk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789413895096369.2631771511773; Mon, 14 Sep 2026 12:24:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x6CIF-0001lO-7j; Mon, 14 Sep 2026 15:24:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x6CIC-0001ek-C2; Mon, 14 Sep 2026 15:24:40 -0400 Received: from smtp-out-1.univ-lille.fr ([194.254.129.82]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x6CIA-0002Pj-25; Mon, 14 Sep 2026 15:24:40 -0400 Received: from smtp01.univ-lille.fr (smtp01.univ-lille.fr [194.254.129.95]) by smtp-out-1.univ-lille.fr (Postfix) with ESMTPS id 4hkFTH6nhhzBqZm; Mon, 14 Sep 2026 21:24:35 +0200 (CEST) Received: from mac.home (lfbn-lil-1-243-101.w90-45.abo.wanadoo.fr [90.45.87.101]) (Authenticated sender: gilles.grimaud) by smtp01.univ-lille.fr (Postfix) with ESMTPSA id 4hkFTH1qQTz801x; Mon, 14 Sep 2026 21:24:35 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=univ-lille.fr; s=dkim; t=1789413876; bh=eTORqgHRjvLB7Zq5ZRd5F5B/wCOqFwPXotdNGYO5WvM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m74jP/Z94JKQc6CMxVff2h0kDv8vyWTL2kpnOEzWQKT8GzNeRV2L0SOp1OAMbj1ZO 5op3GmSUW62H2T7/Jev94oClgdmFuRSMmgA1VDj7jc5g5sOMu4t3B1qxKAmC5y4T4d C8ieZ7ZLNkzKVE//K2IU9cBvWCGVDhOQCngDJKwm/CiT6qKyvQhravQdi+OWT7ISfW JlYkXQeLPXFWY+53L4HbuM7Vaekyf8zNLhpUBo3kyiCrDyDetn5K6RIReB+JZgglbI uGXESVl8zVVRXrnnb5cEaIJOAfPnN9w1DyI2vIw60uNQXyqErl2vS2RzuwAemjmY6p t1Yady6F8DvWg== From: Gilles Grimaud To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Subject: [RFC PATCH v1 1/6] target/arm: enforce Armv6-M NVIC limits Date: Mon, 14 Sep 2026 21:23:17 +0200 Message-ID: <20260914192323.29250-2-gilles.grimaud@univ-lille.fr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> References: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=194.254.129.82; envelope-from=gilles.grimaud@univ-lille.fr; helo=smtp-out-1.univ-lille.fr X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @univ-lille.fr) X-ZM-MESSAGEID: 1789413897987158500 Content-Type: text/plain; charset="utf-8" Armv6-M supports no more than 32 external interrupts. Its ICTR and Active Bit Register locations are reserved, and Cortex-M0 implements two priority bits. Reject Armv6-M NVIC configurations with more than 32 external interrupts. Add a check-tcg test that verifies the reserved register behavior and priority masking on the microbit machine. Signed-off-by: Gilles Grimaud Reviewed-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 5 ++ tests/tcg/arm/system/meson.build | 6 +++ tests/tcg/arm/system/test-armv6m-nvic.S | 70 +++++++++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 tests/tcg/arm/system/test-armv6m-nvic.S diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a7651f831e..b1d27dfb32 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2728,6 +2728,11 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) return; } =20 + if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7) && s->num_irq > 32) { + error_setg(errp, "Armv6-M NVIC cannot exceed 32 external IRQs"); + return; + } + qdev_init_gpio_in(dev, set_irq_level, s->num_irq); =20 /* include space for internal exception vectors */ diff --git a/tests/tcg/arm/system/meson.build b/tests/tcg/arm/system/meson.= build index 4c77b9c3d6..5286997670 100644 --- a/tests/tcg/arm/system/meson.build +++ b/tests/tcg/arm/system/meson.build @@ -39,6 +39,12 @@ tests +=3D { '-T', files('test-armv6m-undef.ld')], 'qemu_args': ['-M', 'microbit', qemu_base_args], }, + 'test-armv6m-nvic.S': { + 'cflags': ['-mcpu=3Dcortex-m0', '-mfloat-abi=3Dsoft', '-nostdlib', + '-Wl,--build-id=3Dnone', + '-T', files('test-armv6m-undef.ld')], + 'qemu_args': ['-M', 'microbit', qemu_base_args], + }, 'semiconsole.c': { 'cflags': cflags, 'qemu_args': ['-serial', 'none', '-chardev', 'stdio,mux=3Don,id=3Dstdi= o0', diff --git a/tests/tcg/arm/system/test-armv6m-nvic.S b/tests/tcg/arm/system= /test-armv6m-nvic.S new file mode 100644 index 0000000000..ecb29eaa3d --- /dev/null +++ b/tests/tcg/arm/system/test-armv6m-nvic.S @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Test Armv6-M NVIC register behavior. */ + +.syntax unified +.cpu cortex-m0 +.thumb + +#define SRAM_BASE 0x20000000 +#define SRAM_SIZE (16 * 1024) + +#define NVIC_ICTR 0xe000e004 +#define NVIC_IABR0 0xe000e300 +#define NVIC_IPR0 0xe000e400 + +#define semihosting_call bkpt 0xab +#define SYS_EXIT 0x18 + +vector_table: + .word SRAM_BASE + SRAM_SIZE + .word reset + 1 + .word 0 + .word failure + 1 + .rept 44 + .word 0 + .endr + +.equ exc_reset_thumb, reset + 1 +.global exc_reset_thumb +reset: + /* ICTR is reserved and reads as zero on Armv6-M. */ + ldr r0, =3DNVIC_ICTR + ldr r1, [r0] + cmp r1, 0 + bne failure + + /* The Active Bit Register is reserved and behaves as RAZ/WI. */ + ldr r0, =3DNVIC_IABR0 + movs r1, 1 + str r1, [r0] + ldr r1, [r0] + cmp r1, 0 + bne failure + + /* Cortex-M0 implements the two most significant priority bits. */ + ldr r0, =3DNVIC_IPR0 + movs r1, 0xff + strb r1, [r0] + ldrb r1, [r0] + cmp r1, 0xc0 + bne failure + +success: + movs r0, 1 + b exit + +failure: + movs r0, 0 + +exit: + movs r1, 0 + cmp r0, 1 + bne 1f + ldr r1, ADP_Stopped_ApplicationExit +1: + movs r0, SYS_EXIT + semihosting_call + +.align 2 +ADP_Stopped_ApplicationExit: + .word 0x20026 --=20 2.55.0 From nobody Sat Sep 26 21:38:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 14 Sep 2026 21:25:36 +0200 (CEST) Received: from mac.home (lfbn-lil-1-243-101.w90-45.abo.wanadoo.fr [90.45.87.101]) (Authenticated sender: gilles.grimaud) by smtp01.univ-lille.fr (Postfix) with ESMTPSA id 4hkFVS1Qfcz80JX; Mon, 14 Sep 2026 21:25:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=univ-lille.fr; s=dkim; t=1789413936; bh=tbh+Br5kxKIjFAp5cHgNYrIJK3nC03h/+dmIwaKU+/w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WxvwY0cV5NLTjVUanVpQCUptZEY7am8X/lNJ8g3h5FCyWKi8uk61zkQ9iDgJ8j3ek yfggIxY6z3mFiej1KhnS08SdfCvzpzorFOKb1OwzW6C7OSVaz86CPj2ugkMbjzrlbb aRhUR3BLG3D0ubgZ0caQPAiQ1XVeNTD0oezra1Mi0YUzGh/WmOocGsDley8iwQpsaY hmPjoCYXR/ixik3Xx18Y3W7MhCih6OzT383EGGgDEhxZ5b/EsqneHA1TTxg7HcfJT8 EaZrI5MAewbciL6zpomoqNzH197SsxrbE1MkK5VQqO3W/X4kj0cXWKk3ck2bXcMzMz s/4w40VFp2+SQ== From: Gilles Grimaud To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Subject: [RFC PATCH v1 2/6] target/arm: model Cortex-M0+ privilege extension Date: Mon, 14 Sep 2026 21:23:18 +0200 Message-ID: <20260914192323.29250-3-gilles.grimaud@univ-lille.fr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> References: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=194.254.129.106; envelope-from=gilles.grimaud@univ-lille.fr; helo=smtp-out-2.univ-lille.fr X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @univ-lille.fr) X-ZM-MESSAGEID: 1789413963905158500 Content-Type: text/plain; charset="utf-8" The Armv6-M Unprivileged/Privileged Extension is optional. Cortex-M0 does not implement it, while Cortex-M0+ may implement it. The RP2040 Cortex-M0+ configuration provides the extension. Add an ARM feature bit and a cortex-m0plus CPU type that enables it. Permit privileged writes to CONTROL.nPRIV when either the Main Extension or the optional privilege extension is present. Update the microbit Cortex-M0 test to verify that writes to nPRIV are ignored. Signed-off-by: Gilles Grimaud --- target/arm/cpu.h | 1 + target/arm/tcg/cpu-v7m.c | 11 ++++ target/arm/tcg/m_helper.c | 4 +- tests/tcg/arm/system/meson.build | 6 ++ tests/tcg/arm/system/test-armv6m-control.S | 66 ++++++++++++++++++++++ 5 files changed, 87 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/arm/system/test-armv6m-control.S diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e3f931dba2..66606b3444 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2168,6 +2168,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ + ARM_FEATURE_M_UNPRIV, /* M profile Unprivileged/Privileged Extension */ ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ /* * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5M= Hz diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c index 48b31d5eac..ac99c93ec3 100644 --- a/target/arm/tcg/cpu-v7m.c +++ b/target/arm/tcg/cpu-v7m.c @@ -76,6 +76,15 @@ static void cortex_m0_initfn(Object *obj) SET_IDREG(isar, ID_ISAR6, 0x00000000); } =20 +static void cortex_m0plus_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cortex_m0_initfn(obj); + set_feature(&cpu->env, ARM_FEATURE_M_UNPRIV); + cpu->midr =3D 0x410cc601; +} + static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -325,6 +334,8 @@ static void arm_v7m_class_init(ObjectClass *oc, const v= oid *data) static const ARMCPUInfo arm_v7m_cpus[] =3D { { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m0plus", .initfn =3D cortex_m0plus_initfn, + .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 33c9e7c55b..f8461a4d66 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -2775,7 +2775,9 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) !arm_v7m_is_handler_mode(env))) { write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) = !=3D 0); } - if (cur_el > 0 && arm_feature(env, ARM_FEATURE_M_MAIN)) { + if (cur_el > 0 && + (arm_feature(env, ARM_FEATURE_M_MAIN) || + arm_feature(env, ARM_FEATURE_M_UNPRIV))) { env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA= SK; env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR= IV_MASK; } diff --git a/tests/tcg/arm/system/meson.build b/tests/tcg/arm/system/meson.= build index 5286997670..e92a83a8d5 100644 --- a/tests/tcg/arm/system/meson.build +++ b/tests/tcg/arm/system/meson.build @@ -45,6 +45,12 @@ tests +=3D { '-T', files('test-armv6m-undef.ld')], 'qemu_args': ['-M', 'microbit', qemu_base_args], }, + 'test-armv6m-control.S': { + 'cflags': ['-mcpu=3Dcortex-m0', '-mfloat-abi=3Dsoft', '-nostdlib', + '-Wl,--build-id=3Dnone', + '-T', files('test-armv6m-undef.ld')], + 'qemu_args': ['-M', 'microbit', qemu_base_args], + }, 'semiconsole.c': { 'cflags': cflags, 'qemu_args': ['-serial', 'none', '-chardev', 'stdio,mux=3Don,id=3Dstdi= o0', diff --git a/tests/tcg/arm/system/test-armv6m-control.S b/tests/tcg/arm/sys= tem/test-armv6m-control.S new file mode 100644 index 0000000000..42ce42db2b --- /dev/null +++ b/tests/tcg/arm/system/test-armv6m-control.S @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Test that Cortex-M0 does not implement CONTROL.nPRIV. */ + +.syntax unified +.cpu cortex-m0 +.thumb + +#define SRAM_BASE 0x20000000 +#define SRAM_SIZE (16 * 1024) + +#define semihosting_call bkpt 0xab +#define SYS_EXIT 0x18 + +vector_table: + .word SRAM_BASE + SRAM_SIZE + .word reset + 1 + .word 0 + .word failure + 1 + .rept 7 + .word 0 + .endr + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .rept 32 + .word 0 + .endr + +.equ exc_reset_thumb, reset + 1 +.global exc_reset_thumb +reset: + /* Thread mode starts privileged. */ + mrs r0, control + movs r1, 1 + tst r0, r1 + bne failure + + /* Cortex-M0 does not implement the optional privilege extension. */ + movs r0, 1 + msr control, r0 + isb + mrs r0, control + tst r0, r1 + bne failure + +success: + movs r0, 1 + b exit + +failure: + movs r0, 0 + +exit: + movs r1, 0 + cmp r0, 1 + bne 1f + ldr r1, ADP_Stopped_ApplicationExit +1: + movs r0, SYS_EXIT + semihosting_call + +.align 2 +ADP_Stopped_ApplicationExit: + .word 0x20026 --=20 2.55.0 From nobody Sat Sep 26 21:38:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 14 Sep 2026 21:26:36 +0200 (CEST) Received: from mac.home (lfbn-lil-1-243-101.w90-45.abo.wanadoo.fr [90.45.87.101]) (Authenticated sender: gilles.grimaud) by smtp02.univ-lille.fr (Postfix) with ESMTPSA id 4hkFWc4vf3z6skd; Mon, 14 Sep 2026 21:26:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=univ-lille.fr; s=dkim; t=1789413996; bh=XxwgYaAYLA/mT9oSgpWMCLwsZdkMXri0oTbI+Pp7kD8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OG1QoWwfFUBxNGT+JRtwnAlYWzmFwyA1TUe282FsuA4sqevDKq0sI0OnHp6HOk9ff 0DMih01CM5ilGe5z+IXqc2VXpgzGQXqyLjCoVMNDhOsK7DtxvgRkRdzz93CsdelCDy 1vh6VtCW8eiMRBybcqjGw8xjoAh+YTqmLgGGsp7YQr1NNNaSHjXwv8MQOpxHKUTxnh MGRLc/s6631XBSs43x+mU+lMooYARFex34gVcvQVZFvJNTGK1nzPLm0yE+4+fYMNE4 LxpeKMmng7u/gwcYC0IL7BD0eYT1susBOJWHGEI1SCjNdoQMdOQDCN1qrVZLvIGH3s pxjak9mSSkZuQ== From: Gilles Grimaud To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Subject: [RFC PATCH v1 3/6] target/arm: MPU - limit regs RBAR/RASR A1-A3 to Main Extension Date: Mon, 14 Sep 2026 21:23:19 +0200 Message-ID: <20260914192323.29250-4-gilles.grimaud@univ-lille.fr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> References: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=194.254.129.82; envelope-from=gilles.grimaud@univ-lille.fr; helo=smtp-out-1.univ-lille.fr X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @univ-lille.fr) X-ZM-MESSAGEID: 1789414062771158500 Content-Type: text/plain; charset="utf-8" The alias registers MPU_RBAR_A1-A3 and MPU_RASR_A1-A3 (v7M) or MPU_RLAR_A1-A3 (v8M) exist only when the Main Extension is implemented (ARM_FEATURE_M_MAIN). The current NVIC decoder groups the principal register and its aliases in the same case fall-through, so once the PMSAv7 path is enabled for v6-M (or the PMSAv8 path for v8-M Baseline) the aliases become incorrectly accessible. The fix reorders the case statements for the four locations (read and write of RBAR and RASR/RLAR) in hw/intc/armv7m_nvic.c. Alias cases are placed before the principal register case with a fall-through and are guarded by a test of ARM_FEATURE_M_MAIN. If the Main Extension is absent the code jumps to bad_offset, causing a read to log "NVIC: Bad read offset" and return zero, and a write to log "NVIC: Bad write offset" and be ignored. The principal MPU_RBAR and MPU_RASR/RLAR registers remain functional for CPUs that implement the corresponding MPU. Suggested-by: Peter Maydell Signed-off-by: Gilles Grimaud Reviewed-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index b1d27dfb32..51d3dba852 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1382,10 +1382,15 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) return cpu->env.v7m.mpu_ctrl[attrs.secure]; case 0xd98: /* MPU_RNR */ return cpu->env.pmsav7.rnr[attrs.secure]; - case 0xd9c: /* MPU_RBAR */ case 0xda4: /* MPU_RBAR_A1 */ case 0xdac: /* MPU_RBAR_A2 */ case 0xdb4: /* MPU_RBAR_A3 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + /* These aliases are not present for v6M or v8M without Main */ + goto bad_offset; + } + /* fall through */ + case 0xd9c: /* MPU_RBAR */ { int region =3D cpu->env.pmsav7.rnr[attrs.secure]; =20 @@ -1410,10 +1415,16 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) } return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf); } - case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + /* These aliases are not present for v6M or v8M without Main */ + goto bad_offset; + } + /* fall through */ + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ { int region =3D cpu->env.pmsav7.rnr[attrs.secure]; =20 @@ -1892,10 +1903,15 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, cpu->env.pmsav7.rnr[attrs.secure] =3D value; } break; - case 0xd9c: /* MPU_RBAR */ case 0xda4: /* MPU_RBAR_A1 */ case 0xdac: /* MPU_RBAR_A2 */ case 0xdb4: /* MPU_RBAR_A3 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + /* These aliases are not present for v6M or v8M without Main */ + goto bad_offset; + } + /* fall through */ + case 0xd9c: /* MPU_RBAR */ { int region; =20 @@ -1943,10 +1959,16 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, tlb_flush(CPU(cpu)); break; } - case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + /* These aliases are not present for v6M or v8M without Main */ + goto bad_offset; + } + /* fall through */ + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ { int region =3D cpu->env.pmsav7.rnr[attrs.secure]; =20 --=20 2.55.0 From nobody Sat Sep 26 21:38:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=univ-lille.fr ARC-Seal: i=1; a=rsa-sha256; t=1789414105; cv=none; d=zohomail.com; s=zohoarc; b=n8BjbkksoXitngCHQhWGL8yZ6qmuvKAOeKTjl+WAl5CjeMGFXYCmxWyTcM79s7VzkB2885UmciHpXjNKzXxyrQt9s5s0ORFk28b5tISnqm4uo/SUtb8rOCVMGhdv3HkLBOfgcPqeXjk0tyrefLsqWSX5H7RsNDalNjrwDwfM9W8= ARC-Message-Signature: i=1; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TMtyE9AYLIsSDiLPJkHseJNDf5qkcWOScOvBYqYI7EbJaIohcjR4WX1BrZszYIp5N AbkFqKl/svI3MPpPrXAD1k5fZNWzsNHbHjSGGs1n+b52/xfclNrqimxtxM0NBM0/t3 ap4cBqRTKuoRFM4N7mqwZ5nLMPDsjTMy4q2iiEVPvFbydzd1tf1wPseuQ63VqrJyYG oE7rLoqb7X7a+wq+yqAMWVW5YphrYJaPBHZgUSY2zLG56BU4TN2piMiWIcq8tb4oJP extOaGMlxvn38WNNyAnex4+lR4wn4SLhC3LLgLHcpRdq40XnDH8T+HS67TRTXIjS8t LOFZf+4pRh8YA== From: Gilles Grimaud To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Subject: [RFC PATCH v1 4/6] target/arm: MPU_RASR: mask TEX bits for Armv6-M Date: Mon, 14 Sep 2026 21:23:20 +0200 Message-ID: <20260914192323.29250-5-gilles.grimaud@univ-lille.fr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> References: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=194.254.129.82; envelope-from=gilles.grimaud@univ-lille.fr; helo=smtp-out-1.univ-lille.fr X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @univ-lille.fr) X-ZM-MESSAGEID: 1789414106752158500 Content-Type: text/plain; charset="utf-8" Keep the existing mask (0x173f) for CPUs with ARM_FEATURE_V7, and use a mask that excludes TEX (0x1707) for Armv6-M. PMSAv8 is handled by the earlier branch and is unaffected by this change. After writing MPU_RASR on an Armv6-M CPU a subsequent read returns zero for the TEX bits; Armv7-M behaviour remains unchanged. Suggested-by: Peter Maydell Signed-off-by: Gilles Grimaud Reviewed-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 51d3dba852..4136c91f23 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1996,7 +1996,12 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, } =20 cpu->env.pmsav7.drsr[region] =3D value & 0xff3f; - cpu->env.pmsav7.dracr[region] =3D (value >> 16) & 0x173f; + if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + cpu->env.pmsav7.dracr[region] =3D (value >> 16) & 0x173f; + } else { + /* Armv6-M has XN, AP, S, C and B, but no TEX field. */ + cpu->env.pmsav7.dracr[region] =3D (value >> 16) & 0x1707; + } tlb_flush(CPU(cpu)); break; } --=20 2.55.0 From nobody Sat Sep 26 21:38:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789414135946217.33219770135236; Mon, 14 Sep 2026 12:28:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x6CMC-0004iC-1T; Mon, 14 Sep 2026 15:28:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x6CM4-0004a4-Sj; Mon, 14 Sep 2026 15:28:41 -0400 Received: from smtp-out-1.univ-lille.fr ([194.254.129.82]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x6CM3-000303-Bt; Mon, 14 Sep 2026 15:28:40 -0400 Received: from smtp02.univ-lille.fr (smtp02.univ-lille.fr [194.254.129.96]) by smtp-out-1.univ-lille.fr (Postfix) with ESMTPS id 4hkFYx6D3NzBqPV; Mon, 14 Sep 2026 21:28:37 +0200 (CEST) Received: from mac.home (lfbn-lil-1-243-101.w90-45.abo.wanadoo.fr [90.45.87.101]) (Authenticated sender: gilles.grimaud) by smtp02.univ-lille.fr (Postfix) with ESMTPSA id 4hkFYx4hMhz6skd; Mon, 14 Sep 2026 21:28:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=univ-lille.fr; s=dkim; t=1789414117; bh=mZeRvHBGZjvTQDaNJAFKTjoSRtReNyYV8QT57TH3mGU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uabNaIEbPTfsU1CRhmpWK3IvsmgbIiqUWrglHY1YnBBDf6Z6KTm5aam05V0YOG440 /v9WJPzCS3WLXZFiCQOJ52KoAR2/vMmjGqzP/YboYjwOK7yGt5VZlDntQj6nU5Hz/7 FbAhbFupExrCNn5Y7SUT/fi5wXybWJxUwWpx/AQUjOUK1cICXXDoflvxfgF7SHDhh+ lji5MvJKrQk2wn69FvfcNPpaprNEBnmzEY2GqBrS6A5xDneVgTuktlngMu+/Cvs5SI gWzqfHDtXFWUcYV5OCHJ3uBpXl8A/3K9v5oZ/N11uLgRBth3nqcmBaAXIdwwM9YkeW FyXspFlwCESdg== From: Gilles Grimaud To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Subject: [RFC PATCH v1 5/6] target/arm: fix MPU SIZE min for v6-M/v7-M/v7-R Date: Mon, 14 Sep 2026 21:23:21 +0200 Message-ID: <20260914192323.29250-6-gilles.grimaud@univ-lille.fr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> References: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=194.254.129.82; envelope-from=gilles.grimaud@univ-lille.fr; helo=smtp-out-1.univ-lille.fr X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @univ-lille.fr) X-ZM-MESSAGEID: 1789414136750158500 Content-Type: text/plain; charset="utf-8" The PMSAv7 walk accepted any non-zero region size field, but Armv6-M requires a minimum of 7 (256 B), Armv7-M requires 4 (32 B) and v7-R retains its current minimum of 1 (4 B). Introduce rsize_min based on ARM_FEATURE_M and ARM_FEATURE_V7 and reject smaller values. The PMSAv8 path is handled earlier and remains unchanged. Suggested-by: Peter Maydell Signed-off-by: Gilles Grimaud Reviewed-by: Peter Maydell --- target/arm/ptw.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a29de0385f..cb9e73fc0a 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2720,6 +2720,11 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; bool is_user =3D regime_is_user(mmu_idx); bool secure =3D arm_space_is_secure(ptw->in_space); + uint32_t rsize_min =3D 1; + + if (arm_feature(env, ARM_FEATURE_M)) { + rsize_min =3D arm_feature(env, ARM_FEATURE_V7) ? 4 : 7; + } =20 result->f.phys_addr =3D address; result->f.lg_page_size =3D TARGET_PAGE_BITS; @@ -2748,11 +2753,13 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, continue; } =20 - if (!rsize) { + if (rsize < rsize_min) { qemu_log_mask(LOG_GUEST_ERROR, - "DRSR[%d]: Rsize field cannot be 0\n", n); + "DRSR[%d]: invalid Rsize field 0x%x\n", + n, rsize); continue; } + rsize++; rmask =3D (1ull << rsize) - 1; =20 --=20 2.55.0 From nobody Sat Sep 26 21:38:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=univ-lille.fr ARC-Seal: i=1; a=rsa-sha256; t=1789414208; cv=none; d=zohomail.com; s=zohoarc; b=d9sfRPMTrxHiyIhkXy6MV4ABtHmuNbDDGHPwMtfr5KQ+rQi22WnPV6ck5A9tZZYetjt9rzPKdmzWOrkDxWAxWo16QrsXMj2qN19PHcXxZQ2WrTBd5qnAw7zvEAn56nowo5DUVjyhRIHw15PqcIPvHN2hPMMHMLJraXu0s2MBLec= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789414208; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mC5RfBj6ylyOwDGowPmggfi/LrsOz8J7K11WQCUcqXg=; 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Mon, 14 Sep 2026 15:29:41 -0400 Received: from smtp02.univ-lille.fr (smtp02.univ-lille.fr [194.254.129.96]) by smtp-out-1.univ-lille.fr (Postfix) with ESMTPS id 4hkFb62n7MzBqYN; Mon, 14 Sep 2026 21:29:38 +0200 (CEST) Received: from mac.home (lfbn-lil-1-243-101.w90-45.abo.wanadoo.fr [90.45.87.101]) (Authenticated sender: gilles.grimaud) by smtp02.univ-lille.fr (Postfix) with ESMTPSA id 4hkFb616YNz6sxf; Mon, 14 Sep 2026 21:29:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=univ-lille.fr; s=dkim; t=1789414178; bh=mC5RfBj6ylyOwDGowPmggfi/LrsOz8J7K11WQCUcqXg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D3atsqv4miufLiJ4+ZIYGkutfWaVrx1wOa2BOCA9e1lnzRlWlZqFwWNkuMNdC6j4O NcnSqQyJHobDn57A++5oihVKA2/jd3dZdDZV5vwrYhZVu+2hY/btjUBc2cZsgL5AL4 lQhFNjv1TIjBDPizlHS9QGG7SCPrFLyoFosqrDIJtZQs0mQ/5p+5AxOzXDh1rBi/xU 9a3b6trLpc2U1JCg1XD9C1yF01CyMvfflDC3Fk/XdNXC1fMo8g54tRUuuEQqNp78bK SMr+ESgSN1slqwOa4C5CPNOCoNJjpFys4ZaJ5Pt7mf9GdFE65lqccSCfvSOjUGuOgu eusB/LC91ruJg== From: Gilles Grimaud To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Subject: [RFC PATCH v1 6/6] target/arm: extend PMSAv7 support to v6-M CPUs Date: Mon, 14 Sep 2026 21:23:22 +0200 Message-ID: <20260914192323.29250-7-gilles.grimaud@univ-lille.fr> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> References: <20260914192323.29250-1-gilles.grimaud@univ-lille.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=194.254.129.82; envelope-from=gilles.grimaud@univ-lille.fr; helo=smtp-out-1.univ-lille.fr X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @univ-lille.fr) X-ZM-MESSAGEID: 1789414209729158500 Content-Type: text/plain; charset="utf-8" QEMU conditions PMSAv7 storage, reset, allocation, the pmsav7-dregion prope= rty, migration and address translation on ARM_FEATURE_V7, which prevents the Arm= v6-M MPU from being used. The checks are widened to also accept ARM_FEATURE_M wh= ile preserving the PMSAv8 path for v8-M CPUs (PMSAv8 is tested first and the migration vmstate excludes v8-M with !ARM_FEATURE_V8). This lets a Cortex-M= 0+ declare and use its MPU regions without setting ARM_FEATURE_V7, while v8-M = CPUs continue to use PMSAv8 storage and migration. Suggested-by: Peter Maydell Signed-off-by: Gilles Grimaud Reviewed-by: Peter Maydell --- target/arm/cpu.c | 12 +++++++++--- target/arm/machine.c | 3 ++- target/arm/ptw.c | 3 ++- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 77aa78f00e..f58a1db843 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -617,7 +617,8 @@ static void arm_cpu_reset_hold(Object *obj, ResetType t= ype) sizeof(*env->pmsav8.rlar[M_REG_S]) * cpu->pmsav7_dregion); } - } else if (arm_feature(env, ARM_FEATURE_V7)) { + } else if (arm_feature(env, ARM_FEATURE_V7) || + arm_feature(env, ARM_FEATURE_M)) { memset(env->pmsav7.drbar, 0, sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); memset(env->pmsav7.drsr, 0, @@ -1656,7 +1657,11 @@ static void arm_cpu_post_init(Object *obj) #ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); - if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + /* + * QEMU's PMSAv7 state also models the Armv6-M MPU register layout. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_V7) || + arm_feature(&cpu->env, ARM_FEATURE_M)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_pmsav7_dregion_property); } @@ -2332,7 +2337,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } =20 if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7)) { + (arm_feature(env, ARM_FEATURE_V7) || + arm_feature(env, ARM_FEATURE_M))) { uint32_t nr =3D cpu->pmsav7_dregion; =20 if (nr > 0xff) { diff --git a/target/arm/machine.c b/target/arm/machine.c index 7005f4e5d7..53a2734d25 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -584,7 +584,8 @@ static bool pmsav7_needed(void *opaque) CPUARMState *env =3D &cpu->env; =20 return arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7) && + (arm_feature(env, ARM_FEATURE_V7) || + arm_feature(env, ARM_FEATURE_M)) && !arm_feature(env, ARM_FEATURE_V8); } =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index cb9e73fc0a..f537502d3b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3908,7 +3908,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T= ranslate *ptw, /* PMSAv8 */ ret =3D get_phys_addr_pmsav8(env, ptw, address, access_type, result, fi); - } else if (arm_feature(env, ARM_FEATURE_V7)) { + } else if (arm_feature(env, ARM_FEATURE_V7) || + arm_feature(env, ARM_FEATURE_M)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, ptw, address, access_type, result, fi); --=20 2.55.0