Add HVX contexts to Hexagon translation, necessary for system emulation.
Change the HVX instruction translation to access the context via a base
pointer.
Modeling the HVX context mapping while avoiding the need to copy the
context when the OS scheduler decides to remap them required some general
TCG gvec changes to enable some more _var forms.
Brian Cain (9):
tcg: split out _var forms of gvec logical, abs and min/max ops
tcg: add base arguments to the gvec 2s, dup_i32 and cmp expanders
tcg: split out _var forms of gvec saturating/mul/shift-immediate ops
target/hexagon: raise an exception for HVX with SSR:XE clear
target/hexagon: reach the HVX register file through a pointer
target/hexagon: carry a base ptr w/HVX reg offsets
target/hexagon: move the HVX register file into a QOM object
target/hexagon: select the HVX register file with SSR:XA
tests/functional/hexagon: add test_hvx_context arch test
include/hw/hexagon/hexagon.h | 1 +
include/hw/hexagon/hexagon_hvx_context.h | 27 +
include/tcg/tcg-op-gvec-common.h | 97 +++
target/hexagon/cpu.h | 18 +-
target/hexagon/cpu_helper.h | 1 +
target/hexagon/gen_tcg_hvx.h | 608 ++++++++++---------
target/hexagon/genptr.h | 8 +
target/hexagon/mmvec/macros.h | 14 +-
target/hexagon/translate.h | 7 +-
hw/hexagon/hex-subsys.c | 36 ++
hw/hexagon/hexagon_hvx_context.c | 83 +++
linux-user/hexagon/cpu_loop.c | 2 +
linux-user/main.c | 3 +
target/hexagon/cpu.c | 39 +-
target/hexagon/cpu_helper.c | 72 +++
target/hexagon/gdbstub.c | 16 +-
target/hexagon/genptr.c | 102 ++--
target/hexagon/machine.c | 12 +
target/hexagon/op_helper.c | 37 +-
target/hexagon/translate.c | 73 ++-
tcg/tcg-op-gvec.c | 617 ++++++++++++++------
hw/hexagon/meson.build | 1 +
target/hexagon/hex_common.py | 180 +++---
tests/functional/hexagon/test_arch_tests.py | 7 +
24 files changed, 1437 insertions(+), 624 deletions(-)
create mode 100644 include/hw/hexagon/hexagon_hvx_context.h
create mode 100644 hw/hexagon/hexagon_hvx_context.c
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2.34.1