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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789054431404158500 target/hexagon is about to address its HVX register file through a runtime base pointer rather than a constant offset from env, in order to share one register file between several vCPUs. The gvec ops it needs have no base-parameterized form yet. Split tcg_gen_gvec_{and,or,xor,andc,orc,not,abs,smin,umin,smax,umax} the same way tcg_gen_gvec_{add,sub,mov,dup_imm} already are: the work moves to a _var function taking a TCGv_ptr base per operand, and the existing entry point becomes a wrapper passing tcg_env. The aofs =3D=3D bofs shortcuts also have to compare the bases, since equal offsets into different objects are not the same operand. Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- include/tcg/tcg-op-gvec-common.h | 45 ++++++++ tcg/tcg-op-gvec.c | 184 ++++++++++++++++++++++++------- 2 files changed, 189 insertions(+), 40 deletions(-) diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-com= mon.h index ea0c87f4db6..99a6685e8a5 100644 --- a/include/tcg/tcg-op-gvec-common.h +++ b/include/tcg/tcg-op-gvec-common.h @@ -287,6 +287,13 @@ void tcg_gen_gvec_mov_var(unsigned vece, TCGv_ptr dbas= e, uint32_t dofs, TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, uint32_t maxsz); =20 +void tcg_gen_gvec_not_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_abs_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -335,6 +342,23 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, = uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 /* Min/max. */ +void tcg_gen_gvec_smin_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_umin_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_smax_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_umax_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -344,6 +368,27 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, u= int32_t aofs, void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 +void tcg_gen_gvec_and_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_or_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_xor_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_andc_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_orc_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 27f3807b004..191ac0fa864 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1911,8 +1911,9 @@ void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dof= s, uint32_t oprsz, tcg_gen_gvec_dup_imm_var(vece, tcg_env, dofs, oprsz, maxsz, x); } =20 -void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_not_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen2 g =3D { .fni8 =3D tcg_gen_not_i64, @@ -1920,7 +1921,13 @@ void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, = uint32_t aofs, .fno =3D gen_helper_gvec_not, .prefer_i64 =3D true, }; - tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g); + tcg_gen_gvec_2_var(dbase, dofs, abase, aofs, oprsz, maxsz, &g); +} + +void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_not_var(vece, tcg_env, dofs, tcg_env, aofs, oprsz, maxsz); } =20 /* Perform a vector addition using normal addition and a mask. The mask @@ -2427,8 +2434,10 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs= , uint32_t aofs, tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_smin_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_smin_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2452,11 +2461,21 @@ void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs= , uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_smin_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + +void tcg_gen_gvec_umin_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_umin_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2480,11 +2499,21 @@ void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs= , uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_umin_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + +void tcg_gen_gvec_smax_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_smax_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2508,11 +2537,21 @@ void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs= , uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_smax_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + +void tcg_gen_gvec_umax_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_umax_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2536,7 +2575,15 @@ void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs,= uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_umax_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); } =20 /* Perform a vector negation using normal negation and a mask. @@ -2645,8 +2692,9 @@ static void tcg_gen_vec_abs16_i64(TCGv_i64 d, TCGv_i6= 4 b) gen_absv_mask(d, b, MO_16); } =20 -void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_abs_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_abs_vec, 0 }; static const GVecGen2 g[4] =3D { @@ -2674,11 +2722,19 @@ void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs,= uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_2(dofs, aofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_2_var(dbase, dofs, abase, aofs, oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_abs_var(vece, tcg_env, dofs, tcg_env, aofs, oprsz, maxsz); +} + +void tcg_gen_gvec_and_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g =3D { .fni8 =3D tcg_gen_and_i64, @@ -2687,15 +2743,25 @@ void tcg_gen_gvec_and(unsigned vece, uint32_t dofs,= uint32_t aofs, .prefer_i64 =3D true, }; =20 - if (aofs =3D=3D bofs) { - tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + if (abase =3D=3D bbase && aofs =3D=3D bofs) { + tcg_gen_gvec_mov_var(vece, dbase, dofs, abase, aofs, oprsz, maxsz); } else { - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g); } } =20 -void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_and_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, + oprsz, maxsz); +} + +void tcg_gen_gvec_or_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g =3D { .fni8 =3D tcg_gen_or_i64, @@ -2704,15 +2770,25 @@ void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, = uint32_t aofs, .prefer_i64 =3D true, }; =20 - if (aofs =3D=3D bofs) { - tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + if (abase =3D=3D bbase && aofs =3D=3D bofs) { + tcg_gen_gvec_mov_var(vece, dbase, dofs, abase, aofs, oprsz, maxsz); } else { - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g); } } =20 -void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_or_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, + oprsz, maxsz); +} + +void tcg_gen_gvec_xor_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g =3D { .fni8 =3D tcg_gen_xor_i64, @@ -2721,15 +2797,25 @@ void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs,= uint32_t aofs, .prefer_i64 =3D true, }; =20 - if (aofs =3D=3D bofs) { - tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0); + if (abase =3D=3D bbase && aofs =3D=3D bofs) { + tcg_gen_gvec_dup_imm_var(MO_64, dbase, dofs, oprsz, maxsz, 0); } else { - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g); } } =20 -void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_xor_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, + oprsz, maxsz); +} + +void tcg_gen_gvec_andc_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g =3D { .fni8 =3D tcg_gen_andc_i64, @@ -2738,15 +2824,25 @@ void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs= , uint32_t aofs, .prefer_i64 =3D true, }; =20 - if (aofs =3D=3D bofs) { - tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, 0); + if (abase =3D=3D bbase && aofs =3D=3D bofs) { + tcg_gen_gvec_dup_imm_var(MO_64, dbase, dofs, oprsz, maxsz, 0); } else { - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g); } } =20 -void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_andc_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bof= s, + oprsz, maxsz); +} + +void tcg_gen_gvec_orc_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g =3D { .fni8 =3D tcg_gen_orc_i64, @@ -2755,13 +2851,21 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs,= uint32_t aofs, .prefer_i64 =3D true, }; =20 - if (aofs =3D=3D bofs) { - tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, -1); + if (abase =3D=3D bbase && aofs =3D=3D bofs) { + tcg_gen_gvec_dup_imm_var(MO_64, dbase, dofs, oprsz, maxsz, -1); } else { - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g); } } =20 +void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_orc_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, + oprsz, maxsz); +} + void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) { --=20 2.34.1 From nobody Sat Sep 26 20:50:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789054428; cv=none; d=zohomail.com; s=zohoarc; b=IhlZjBN43nKhSwXFHKOFbA8GeMRgl30wuga1iUPxJekMWssRDt0wMPlh02MQlM6U/W1xUO7UhCe0nar/FFS/WZe9RbjIZ9ScDxwz/xwkrXAJNaxr7FAkvJjc1aAy+umCHOfjn/65OkO5AR+8Tj8UGGSDKxF2h828aRIk+cLc7oU= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789054431407158500 These three families still name tcg_env directly, so they cannot be reached from a _var entry point. Thread a TCGv_ptr base per operand through expand_2s_{i32,i64,vec}, expand_2sh_vec, expand_cmp_{i32,i64,vec} and do_gvec_shifts, and split expand_2i_ool out of tcg_gen_gvec_2i_ool the way expand_2_ool already is, so the out-of-line fallback is reachable too. Add tcg_gen_gvec_{2s,shls,shrs,sars,dup_i32,cmp}_var; the existing entry points become wrappers passing tcg_env and generate identical code. Note that the operand swap in tcg_gen_gvec_cmp_var, used when a condition has no helper, now has to swap the bases along with the offsets. Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- include/tcg/tcg-op-gvec-common.h | 21 +++ tcg/tcg-op-gvec.c | 256 +++++++++++++++++++++---------- 2 files changed, 192 insertions(+), 85 deletions(-) diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-com= mon.h index 99a6685e8a5..fa28ebdde0f 100644 --- a/include/tcg/tcg-op-gvec-common.h +++ b/include/tcg/tcg-op-gvec-common.h @@ -237,6 +237,10 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, /* Similarly, expand (env+dofs) =3D op(env+aofs, c). */ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, int64_t c, const GVecGen2i *op); +/* Expand (dbase+dofs) =3D op(abase+aofs, s), length @oprsz. */ +void tcg_gen_gvec_2s_var(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, TCGv_i64 c, const GVecGen2s *op); /* Similarly, expand (env+dofs) =3D op(env+aofs, s). */ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, TCGv_i64 c, const GVecGen2s *op); @@ -433,6 +437,8 @@ void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs,= uint32_t s, =20 void tcg_gen_gvec_dup_imm_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, uint32_t oprsz, uint32_t maxsz, uint64_t imm= ); +void tcg_gen_gvec_dup_i32_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + uint32_t oprsz, uint32_t maxsz, TCGv_i32 in); =20 void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); @@ -445,6 +451,16 @@ void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, = uint32_t aofs, void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); =20 +void tcg_gen_gvec_shls_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrs_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sars_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -471,6 +487,11 @@ void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, = uint32_t aofs, void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); =20 +void tcg_gen_gvec_cmp_var(TCGCond cond, unsigned vece, + TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 191ac0fa864..fc1a70434c5 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -162,23 +162,31 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, =20 /* Generate a call to a gvec-style helper with two vector operands and one scalar operand. */ +static void expand_2i_ool(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, TCGv_i64 c, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_2i *fn) +{ + TCGv_ptr a0, a1; + TCGv_i32 desc =3D tcg_constant_i32(simd_desc(oprsz, maxsz, data)); + + a0 =3D tcg_temp_ebb_new_ptr(); + a1 =3D tcg_temp_ebb_new_ptr(); + + tcg_gen_addi_ptr(a0, dbase, dofs); + tcg_gen_addi_ptr(a1, abase, aofs); + + fn(a0, a1, c, desc); + + tcg_temp_free_ptr(a0); + tcg_temp_free_ptr(a1); +} + void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz, int32_t data, gen_helper_gvec_2i *fn) { - TCGv_ptr a0, a1; - TCGv_i32 desc =3D tcg_constant_i32(simd_desc(oprsz, maxsz, data)); - - a0 =3D tcg_temp_ebb_new_ptr(); - a1 =3D tcg_temp_ebb_new_ptr(); - - tcg_gen_addi_ptr(a0, tcg_env, dofs); - tcg_gen_addi_ptr(a1, tcg_env, aofs); - - fn(a0, a1, c, desc); - - tcg_temp_free_ptr(a0); - tcg_temp_free_ptr(a1); + expand_2i_ool(tcg_env, dofs, tcg_env, aofs, c, oprsz, maxsz, data, fn); } =20 /* Generate a call to a gvec-style helper with three vector operands. */ @@ -783,7 +791,8 @@ static void expand_2i_i32(uint32_t dofs, uint32_t aofs,= uint32_t oprsz, tcg_temp_free_i32(t1); } =20 -static void expand_2s_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, +static void expand_2s_i32(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, TCGv_i32 c, bool scalar_first, void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -792,13 +801,13 @@ static void expand_2s_i32(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, tcg_env, aofs + i); + tcg_gen_ld_i32(t0, abase, aofs + i); if (scalar_first) { fni(t1, c, t0); } else { fni(t1, t0, c); } - tcg_gen_st_i32(t1, tcg_env, dofs + i); + tcg_gen_st_i32(t1, dbase, dofs + i); } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -949,7 +958,8 @@ static void expand_2i_i64(uint32_t dofs, uint32_t aofs,= uint32_t oprsz, tcg_temp_free_i64(t1); } =20 -static void expand_2s_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, +static void expand_2s_i64(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, TCGv_i64 c, bool scalar_first, void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -958,13 +968,13 @@ static void expand_2s_i64(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, tcg_env, aofs + i); + tcg_gen_ld_i64(t0, abase, aofs + i); if (scalar_first) { fni(t1, c, t0); } else { fni(t1, t0, c); } - tcg_gen_st_i64(t1, tcg_env, dofs + i); + tcg_gen_st_i64(t1, dbase, dofs + i); } tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -1114,7 +1124,8 @@ static void expand_2i_vec(unsigned vece, uint32_t dof= s, uint32_t aofs, } } =20 -static void expand_2s_vec(unsigned vece, uint32_t dofs, uint32_t aofs, +static void expand_2s_vec(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, uint32_t tysz, TCGType type, TCGv_vec c, bool scalar_first, void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_v= ec)) @@ -1123,13 +1134,13 @@ static void expand_2s_vec(unsigned vece, uint32_t d= ofs, uint32_t aofs, TCGv_vec t0 =3D tcg_temp_new_vec(type); TCGv_vec t1 =3D tcg_temp_new_vec(type); =20 - tcg_gen_ld_vec(t0, tcg_env, aofs + i); + tcg_gen_ld_vec(t0, abase, aofs + i); if (scalar_first) { fni(vece, t1, c, t0); } else { fni(vece, t1, t0, c); } - tcg_gen_st_vec(t1, tcg_env, dofs + i); + tcg_gen_st_vec(t1, dbase, dofs + i); } } =20 @@ -1375,14 +1386,18 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, } } =20 -/* Expand a vector operation with two vectors and a scalar. */ -void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, - uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g) +/* + * Expand a vector operation with two vectors and a scalar, + * (dbase+dofs) =3D op(abase+aofs, c). + */ +void tcg_gen_gvec_2s_var(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g) { TCGType type; =20 check_size_align(oprsz, maxsz, dofs | aofs); - check_overlap_2(tcg_env, dofs, tcg_env, aofs, maxsz); + check_overlap_2(dbase, dofs, abase, aofs, maxsz); =20 type =3D 0; if (g->fniv) { @@ -1403,7 +1418,8 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. */ some =3D QEMU_ALIGN_DOWN(oprsz, 32); - expand_2s_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, + expand_2s_vec(g->vece, dbase, dofs, abase, aofs, + some, 32, TCG_TYPE_V256, t_vec, g->scalar_first, g->fniv); if (some =3D=3D oprsz) { break; @@ -1415,12 +1431,14 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, /* fallthru */ =20 case TCG_TYPE_V128: - expand_2s_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, + expand_2s_vec(g->vece, dbase, dofs, abase, aofs, + oprsz, 16, TCG_TYPE_V128, t_vec, g->scalar_first, g->fniv); break; =20 case TCG_TYPE_V64: - expand_2s_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, + expand_2s_vec(g->vece, dbase, dofs, abase, aofs, + oprsz, 8, TCG_TYPE_V64, t_vec, g->scalar_first, g->fniv); break; =20 @@ -1433,25 +1451,33 @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, TCGv_i64 t64 =3D tcg_temp_new_i64(); =20 tcg_gen_dup_i64(g->vece, t64, c); - expand_2s_i64(dofs, aofs, oprsz, t64, g->scalar_first, g->fni8); + expand_2s_i64(dbase, dofs, abase, aofs, oprsz, t64, + g->scalar_first, g->fni8); tcg_temp_free_i64(t64); } else if (g->fni4 && check_size_impl(oprsz, 4)) { TCGv_i32 t32 =3D tcg_temp_new_i32(); =20 tcg_gen_extrl_i64_i32(t32, c); tcg_gen_dup_i32(g->vece, t32, t32); - expand_2s_i32(dofs, aofs, oprsz, t32, g->scalar_first, g->fni4); + expand_2s_i32(dbase, dofs, abase, aofs, oprsz, t32, + g->scalar_first, g->fni4); tcg_temp_free_i32(t32); } else { - tcg_gen_gvec_2i_ool(dofs, aofs, c, oprsz, maxsz, 0, g->fno); + expand_2i_ool(dbase, dofs, abase, aofs, c, oprsz, maxsz, 0, g->fno= ); return; } =20 if (oprsz < maxsz) { - expand_clr(tcg_env, dofs + oprsz, maxsz - oprsz); + expand_clr(dbase, dofs + oprsz, maxsz - oprsz); } } =20 +void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, TCGv_i64 c, const GVecGen2s *g) +{ + tcg_gen_gvec_2s_var(tcg_env, dofs, tcg_env, aofs, oprsz, maxsz, c, g); +} + /* Expand a vector three-operand operation. */ void tcg_gen_gvec_3_var(TCGv_ptr dbase, uint32_t dofs, TCGv_ptr abase, uint32_t aofs, @@ -1775,12 +1801,18 @@ void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs,= uint32_t aofs, tcg_gen_gvec_mov_var(vece, tcg_env, dofs, tcg_env, aofs, oprsz, maxsz); } =20 +void tcg_gen_gvec_dup_i32_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + uint32_t oprsz, uint32_t maxsz, TCGv_i32 in) +{ + check_size_align(oprsz, maxsz, dofs); + tcg_debug_assert(vece <=3D MO_32); + do_dup(vece, dbase, dofs, oprsz, maxsz, in, NULL, 0); +} + void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz, uint32_t maxsz, TCGv_i32 in) { - check_size_align(oprsz, maxsz, dofs); - tcg_debug_assert(vece <=3D MO_32); - do_dup(vece, tcg_env, dofs, oprsz, maxsz, in, NULL, 0); + tcg_gen_gvec_dup_i32_var(vece, tcg_env, dofs, oprsz, maxsz, in); } =20 void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz, @@ -3311,7 +3343,8 @@ typedef struct { TCGOpcode v_list[2]; } GVecGen2sh; =20 -static void expand_2sh_vec(unsigned vece, uint32_t dofs, uint32_t aofs, +static void expand_2sh_vec(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, uint32_t tysz, TCGType type, TCGv_i32 shift, void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_= i32)) @@ -3320,21 +3353,22 @@ static void expand_2sh_vec(unsigned vece, uint32_t = dofs, uint32_t aofs, TCGv_vec t0 =3D tcg_temp_new_vec(type); TCGv_vec t1 =3D tcg_temp_new_vec(type); =20 - tcg_gen_ld_vec(t0, tcg_env, aofs + i); + tcg_gen_ld_vec(t0, abase, aofs + i); fni(vece, t1, t0, shift); - tcg_gen_st_vec(t1, tcg_env, dofs + i); + tcg_gen_st_vec(t1, dbase, dofs + i); } } =20 static void -do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, +do_gvec_shifts(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g) { TCGType type; uint32_t some; =20 check_size_align(oprsz, maxsz, dofs | aofs); - check_overlap_2(tcg_env, dofs, tcg_env, aofs, maxsz); + check_overlap_2(dbase, dofs, abase, aofs, maxsz); =20 /* If the backend has a scalar expansion, great. */ type =3D choose_vector_type(g->s_list, vece, oprsz, vece =3D=3D MO_64); @@ -3343,7 +3377,7 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t= aofs, TCGv_i32 shift, switch (type) { case TCG_TYPE_V256: some =3D QEMU_ALIGN_DOWN(oprsz, 32); - expand_2sh_vec(vece, dofs, aofs, some, 32, + expand_2sh_vec(vece, dbase, dofs, abase, aofs, some, 32, TCG_TYPE_V256, shift, g->fniv_s); if (some =3D=3D oprsz) { break; @@ -3354,11 +3388,11 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32= _t aofs, TCGv_i32 shift, maxsz -=3D some; /* fallthru */ case TCG_TYPE_V128: - expand_2sh_vec(vece, dofs, aofs, oprsz, 16, + expand_2sh_vec(vece, dbase, dofs, abase, aofs, oprsz, 16, TCG_TYPE_V128, shift, g->fniv_s); break; case TCG_TYPE_V64: - expand_2sh_vec(vece, dofs, aofs, oprsz, 8, + expand_2sh_vec(vece, dbase, dofs, abase, aofs, oprsz, 8, TCG_TYPE_V64, shift, g->fniv_s); break; default: @@ -3386,7 +3420,8 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t= aofs, TCGv_i32 shift, switch (type) { case TCG_TYPE_V256: some =3D QEMU_ALIGN_DOWN(oprsz, 32); - expand_2s_vec(vece, dofs, aofs, some, 32, TCG_TYPE_V256, + expand_2s_vec(vece, dbase, dofs, abase, aofs, + some, 32, TCG_TYPE_V256, v_shift, false, g->fniv_v); if (some =3D=3D oprsz) { break; @@ -3397,11 +3432,13 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32= _t aofs, TCGv_i32 shift, maxsz -=3D some; /* fallthru */ case TCG_TYPE_V128: - expand_2s_vec(vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, + expand_2s_vec(vece, dbase, dofs, abase, aofs, + oprsz, 16, TCG_TYPE_V128, v_shift, false, g->fniv_v); break; case TCG_TYPE_V64: - expand_2s_vec(vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, + expand_2s_vec(vece, dbase, dofs, abase, aofs, + oprsz, 8, TCG_TYPE_V64, v_shift, false, g->fniv_v); break; default: @@ -3414,11 +3451,13 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32= _t aofs, TCGv_i32 shift, =20 /* Otherwise fall back to integral... */ if (vece =3D=3D MO_32 && check_size_impl(oprsz, 4)) { - expand_2s_i32(dofs, aofs, oprsz, shift, false, g->fni4); + expand_2s_i32(dbase, dofs, abase, aofs, oprsz, shift, + false, g->fni4); } else if (vece =3D=3D MO_64 && check_size_impl(oprsz, 8)) { TCGv_i64 sh64 =3D tcg_temp_ebb_new_i64(); tcg_gen_extu_i32_i64(sh64, shift); - expand_2s_i64(dofs, aofs, oprsz, sh64, false, g->fni8); + expand_2s_i64(dbase, dofs, abase, aofs, oprsz, sh64, + false, g->fni8); tcg_temp_free_i64(sh64); } else { TCGv_ptr a0 =3D tcg_temp_ebb_new_ptr(); @@ -3427,8 +3466,8 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t= aofs, TCGv_i32 shift, =20 tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT); tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0)); - tcg_gen_addi_ptr(a0, tcg_env, dofs); - tcg_gen_addi_ptr(a1, tcg_env, aofs); + tcg_gen_addi_ptr(a0, dbase, dofs); + tcg_gen_addi_ptr(a1, abase, aofs); =20 g->fno[vece](a0, a1, desc); =20 @@ -3440,12 +3479,13 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32= _t aofs, TCGv_i32 shift, =20 clear_tail: if (oprsz < maxsz) { - expand_clr(tcg_env, dofs + oprsz, maxsz - oprsz); + expand_clr(dbase, dofs + oprsz, maxsz - oprsz); } } =20 -void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_shls_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) { static const GVecGen2sh g =3D { .fni4 =3D tcg_gen_shl_i32, @@ -3463,11 +3503,19 @@ void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs= , uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); + do_gvec_shifts(vece, dbase, dofs, abase, aofs, shift, oprsz, maxsz, &g= ); } =20 -void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_shls_var(vece, tcg_env, dofs, tcg_env, aofs, + shift, oprsz, maxsz); +} + +void tcg_gen_gvec_shrs_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) { static const GVecGen2sh g =3D { .fni4 =3D tcg_gen_shr_i32, @@ -3485,11 +3533,19 @@ void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs= , uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); + do_gvec_shifts(vece, dbase, dofs, abase, aofs, shift, oprsz, maxsz, &g= ); } =20 -void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_shrs_var(vece, tcg_env, dofs, tcg_env, aofs, + shift, oprsz, maxsz); +} + +void tcg_gen_gvec_sars_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) { static const GVecGen2sh g =3D { .fni4 =3D tcg_gen_sar_i32, @@ -3507,7 +3563,14 @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs,= uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); + do_gvec_shifts(vece, dbase, dofs, abase, aofs, shift, oprsz, maxsz, &g= ); +} + +void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_sars_var(vece, tcg_env, dofs, tcg_env, aofs, + shift, oprsz, maxsz); } =20 void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -3529,7 +3592,8 @@ void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs,= uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); + do_gvec_shifts(vece, tcg_env, dofs, tcg_env, aofs, shift, + oprsz, maxsz, &g); } =20 void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -3861,7 +3925,9 @@ void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs,= uint32_t aofs, } =20 /* Expand OPSZ bytes worth of three-operand operations using i32 elements.= */ -static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, +static void expand_cmp_i32(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, uint32_t oprsz, TCGCond cond) { TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); @@ -3869,16 +3935,18 @@ static void expand_cmp_i32(uint32_t dofs, uint32_t = aofs, uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, tcg_env, aofs + i); - tcg_gen_ld_i32(t1, tcg_env, bofs + i); + tcg_gen_ld_i32(t0, abase, aofs + i); + tcg_gen_ld_i32(t1, bbase, bofs + i); tcg_gen_negsetcond_i32(cond, t0, t0, t1); - tcg_gen_st_i32(t0, tcg_env, dofs + i); + tcg_gen_st_i32(t0, dbase, dofs + i); } tcg_temp_free_i32(t1); tcg_temp_free_i32(t0); } =20 -static void expand_cmp_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, +static void expand_cmp_i64(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, uint32_t oprsz, TCGCond cond) { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); @@ -3886,17 +3954,19 @@ static void expand_cmp_i64(uint32_t dofs, uint32_t = aofs, uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, tcg_env, aofs + i); - tcg_gen_ld_i64(t1, tcg_env, bofs + i); + tcg_gen_ld_i64(t0, abase, aofs + i); + tcg_gen_ld_i64(t1, bbase, bofs + i); tcg_gen_negsetcond_i64(cond, t0, t0, t1); - tcg_gen_st_i64(t0, tcg_env, dofs + i); + tcg_gen_st_i64(t0, dbase, dofs + i); } tcg_temp_free_i64(t1); tcg_temp_free_i64(t0); } =20 -static void expand_cmp_vec(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t tysz, +static void expand_cmp_vec(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t tysz, TCGType type, TCGCond cond) { for (uint32_t i =3D 0; i < oprsz; i +=3D tysz) { @@ -3904,16 +3974,18 @@ static void expand_cmp_vec(unsigned vece, uint32_t = dofs, uint32_t aofs, TCGv_vec t1 =3D tcg_temp_new_vec(type); TCGv_vec t2 =3D tcg_temp_new_vec(type); =20 - tcg_gen_ld_vec(t0, tcg_env, aofs + i); - tcg_gen_ld_vec(t1, tcg_env, bofs + i); + tcg_gen_ld_vec(t0, abase, aofs + i); + tcg_gen_ld_vec(t1, bbase, bofs + i); tcg_gen_cmp_vec(cond, vece, t2, t0, t1); - tcg_gen_st_vec(t2, tcg_env, dofs + i); + tcg_gen_st_vec(t2, dbase, dofs + i); } } =20 -void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, - uint32_t aofs, uint32_t bofs, - uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_cmp_var(TCGCond cond, unsigned vece, + TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode cmp_list[] =3D { INDEX_op_cmp_vec, 0 }; static gen_helper_gvec_3 * const eq_fn[4] =3D { @@ -3954,10 +4026,10 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, uint32_t some; =20 check_size_align(oprsz, maxsz, dofs | aofs | bofs); - check_overlap_3(tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, maxsz); + check_overlap_3(dbase, dofs, abase, aofs, bbase, bofs, maxsz); =20 if (cond =3D=3D TCG_COND_NEVER || cond =3D=3D TCG_COND_ALWAYS) { - do_dup(MO_8, tcg_env, dofs, oprsz, maxsz, + do_dup(MO_8, dbase, dofs, oprsz, maxsz, NULL, NULL, -(cond =3D=3D TCG_COND_ALWAYS)); return; } @@ -3975,7 +4047,8 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, ui= nt32_t dofs, * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. */ some =3D QEMU_ALIGN_DOWN(oprsz, 32); - expand_cmp_vec(vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, co= nd); + expand_cmp_vec(vece, dbase, dofs, abase, aofs, bbase, bofs, + some, 32, TCG_TYPE_V256, cond); if (some =3D=3D oprsz) { break; } @@ -3986,28 +4059,33 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, maxsz -=3D some; /* fallthru */ case TCG_TYPE_V128: - expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, c= ond); + expand_cmp_vec(vece, dbase, dofs, abase, aofs, bbase, bofs, + oprsz, 16, TCG_TYPE_V128, cond); break; case TCG_TYPE_V64: - expand_cmp_vec(vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, con= d); + expand_cmp_vec(vece, dbase, dofs, abase, aofs, bbase, bofs, + oprsz, 8, TCG_TYPE_V64, cond); break; =20 case 0: if (vece =3D=3D MO_64 && check_size_impl(oprsz, 8)) { - expand_cmp_i64(dofs, aofs, bofs, oprsz, cond); + expand_cmp_i64(dbase, dofs, abase, aofs, bbase, bofs, oprsz, c= ond); } else if (vece =3D=3D MO_32 && check_size_impl(oprsz, 4)) { - expand_cmp_i32(dofs, aofs, bofs, oprsz, cond); + expand_cmp_i32(dbase, dofs, abase, aofs, bbase, bofs, oprsz, c= ond); } else { gen_helper_gvec_3 * const *fn =3D fns[cond]; =20 if (fn =3D=3D NULL) { uint32_t tmp; + TCGv_ptr tmpb; tmp =3D aofs, aofs =3D bofs, bofs =3D tmp; + tmpb =3D abase, abase =3D bbase, bbase =3D tmpb; cond =3D tcg_swap_cond(cond); fn =3D fns[cond]; assert(fn !=3D NULL); } - tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn[vece]= ); + expand_3_ool(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, 0, fn[vece]); oprsz =3D maxsz; } break; @@ -4018,10 +4096,18 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, = uint32_t dofs, tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { - expand_clr(tcg_env, dofs + oprsz, maxsz - oprsz); + expand_clr(dbase, dofs + oprsz, maxsz - oprsz); } } =20 +void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, + uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_cmp_var(cond, vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + static void expand_cmps_vec(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t tysz, TCGType type, TCGCond cond, TCGv_vec c) --=20 2.34.1 From nobody Sat Sep 26 20:50:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, OBFU_UNSUB_UL=1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789054547353158500 target/hexagon is about to address its HVX register file through a runtime base pointer rather than a constant offset from env, in order to share one register file between several vCPUs. Split the other gvec op families it needs like tcg_gen_gvec_{add,sub,mov,and,etc}. Add tcg_gen_gvec_{ssadd,sssub,usadd,ussub,mul}_var and tcg_gen_gvec_{shri,sari}_var, plus the tcg_gen_gvec_2i_var plumbing the immediate-shift forms are built on. Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- include/tcg/tcg-op-gvec-common.h | 31 ++++++ tcg/tcg-op-gvec.c | 177 ++++++++++++++++++++++--------- 2 files changed, 160 insertions(+), 48 deletions(-) diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-com= mon.h index fa28ebdde0f..6d3c2bae57a 100644 --- a/include/tcg/tcg-op-gvec-common.h +++ b/include/tcg/tcg-op-gvec-common.h @@ -234,6 +234,10 @@ void tcg_gen_gvec_2_var(TCGv_ptr dbase, uint32_t dofs, /* Similarly, expand (env+dofs) =3D op(env+aofs). */ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, const GVecGen2 *op); +/* Expand (dbase+dofs) =3D op(abase+aofs, c), clearing @oprsz..@maxsz. */ +void tcg_gen_gvec_2i_var(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, int64_t c, const GVecGen2i *op); /* Similarly, expand (env+dofs) =3D op(env+aofs, c). */ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, uint32_t maxsz, int64_t c, const GVecGen2i *op); @@ -315,6 +319,10 @@ void tcg_gen_gvec_sub_var(unsigned vece, TCGv_ptr dbas= e, uint32_t dofs, TCGv_ptr abase, uint32_t aofs, TCGv_ptr bbase, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_mul_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); =20 void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); @@ -336,6 +344,23 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, u= int32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); =20 /* Saturated arithmetic. */ +void tcg_gen_gvec_ssadd_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sssub_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_usadd_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_ussub_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -442,8 +467,14 @@ void tcg_gen_gvec_dup_i32_var(unsigned vece, TCGv_ptr = dbase, uint32_t dofs, =20 void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shri_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sari_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index fc1a70434c5..0d649cc13b2 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -771,7 +771,8 @@ static void expand_2_i32(TCGv_ptr dbase, uint32_t dofs,= TCGv_ptr abase, tcg_temp_free_i32(t1); } =20 -static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz, +static void expand_2i_i32(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, int32_t c, bool load_dest, void (*fni)(TCGv_i32, TCGv_i32, int32_t)) { @@ -780,12 +781,12 @@ static void expand_2i_i32(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, tcg_env, aofs + i); + tcg_gen_ld_i32(t0, abase, aofs + i); if (load_dest) { - tcg_gen_ld_i32(t1, tcg_env, dofs + i); + tcg_gen_ld_i32(t1, dbase, dofs + i); } fni(t1, t0, c); - tcg_gen_st_i32(t1, tcg_env, dofs + i); + tcg_gen_st_i32(t1, dbase, dofs + i); } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -938,7 +939,8 @@ static void expand_2_i64(TCGv_ptr dbase, uint32_t dofs,= TCGv_ptr abase, tcg_temp_free_i64(t1); } =20 -static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz, +static void expand_2i_i64(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, int64_t c, bool load_dest, void (*fni)(TCGv_i64, TCGv_i64, int64_t)) { @@ -947,12 +949,12 @@ static void expand_2i_i64(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, tcg_env, aofs + i); + tcg_gen_ld_i64(t0, abase, aofs + i); if (load_dest) { - tcg_gen_ld_i64(t1, tcg_env, dofs + i); + tcg_gen_ld_i64(t1, dbase, dofs + i); } fni(t1, t0, c); - tcg_gen_st_i64(t1, tcg_env, dofs + i); + tcg_gen_st_i64(t1, dbase, dofs + i); } tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -1106,7 +1108,8 @@ static void expand_2_vec(unsigned vece, TCGv_ptr dbas= e, uint32_t dofs, =20 /* Expand OPSZ bytes worth of two-vector operands and an immediate operand using host vectors. */ -static void expand_2i_vec(unsigned vece, uint32_t dofs, uint32_t aofs, +static void expand_2i_vec(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, uint32_t tysz, TCGType type, int64_t c, bool load_dest, void (*fni)(unsigned, TCGv_vec, TCGv_vec, int64_= t)) @@ -1115,12 +1118,12 @@ static void expand_2i_vec(unsigned vece, uint32_t d= ofs, uint32_t aofs, TCGv_vec t0 =3D tcg_temp_new_vec(type); TCGv_vec t1 =3D tcg_temp_new_vec(type); =20 - tcg_gen_ld_vec(t0, tcg_env, aofs + i); + tcg_gen_ld_vec(t0, abase, aofs + i); if (load_dest) { - tcg_gen_ld_vec(t1, tcg_env, dofs + i); + tcg_gen_ld_vec(t1, dbase, dofs + i); } fni(vece, t1, t0, c); - tcg_gen_st_vec(t1, tcg_env, dofs + i); + tcg_gen_st_vec(t1, dbase, dofs + i); } } =20 @@ -1318,8 +1321,9 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, } =20 /* Expand a vector operation with two vectors and an immediate. */ -void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, - uint32_t maxsz, int64_t c, const GVecGen2i *g) +void tcg_gen_gvec_2i_var(TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, int64_t c, const GVecGen2i *g) { const TCGOpcode *this_list =3D g->opt_opc ? : vecop_list_empty; const TCGOpcode *hold_list =3D tcg_swap_vecop_list(this_list); @@ -1327,7 +1331,7 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, uint32_t some; =20 check_size_align(oprsz, maxsz, dofs | aofs); - check_overlap_2(tcg_env, dofs, tcg_env, aofs, maxsz); + check_overlap_2(dbase, dofs, abase, aofs, maxsz); =20 type =3D 0; if (g->fniv) { @@ -1340,8 +1344,8 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, ui= nt32_t oprsz, * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. */ some =3D QEMU_ALIGN_DOWN(oprsz, 32); - expand_2i_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, - c, g->load_dest, g->fniv); + expand_2i_vec(g->vece, dbase, dofs, abase, aofs, some, 32, + TCG_TYPE_V256, c, g->load_dest, g->fniv); if (some =3D=3D oprsz) { break; } @@ -1351,26 +1355,29 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, maxsz -=3D some; /* fallthru */ case TCG_TYPE_V128: - expand_2i_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, - c, g->load_dest, g->fniv); + expand_2i_vec(g->vece, dbase, dofs, abase, aofs, oprsz, 16, + TCG_TYPE_V128, c, g->load_dest, g->fniv); break; case TCG_TYPE_V64: - expand_2i_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, - c, g->load_dest, g->fniv); + expand_2i_vec(g->vece, dbase, dofs, abase, aofs, oprsz, 8, + TCG_TYPE_V64, c, g->load_dest, g->fniv); break; =20 case 0: if (g->fni8 && check_size_impl(oprsz, 8)) { - expand_2i_i64(dofs, aofs, oprsz, c, g->load_dest, g->fni8); + expand_2i_i64(dbase, dofs, abase, aofs, oprsz, c, + g->load_dest, g->fni8); } else if (g->fni4 && check_size_impl(oprsz, 4)) { - expand_2i_i32(dofs, aofs, oprsz, c, g->load_dest, g->fni4); + expand_2i_i32(dbase, dofs, abase, aofs, oprsz, c, + g->load_dest, g->fni4); } else { if (g->fno) { - tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno); + expand_2_ool(dbase, dofs, abase, aofs, oprsz, maxsz, + c, g->fno); } else { TCGv_i64 tcg_c =3D tcg_constant_i64(c); - tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz, - maxsz, c, g->fnoi); + expand_2i_ool(dbase, dofs, abase, aofs, tcg_c, oprsz, + maxsz, c, g->fnoi); } oprsz =3D maxsz; } @@ -1382,10 +1389,16 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, = uint32_t oprsz, tcg_swap_vecop_list(hold_list); =20 if (oprsz < maxsz) { - expand_clr(tcg_env, dofs + oprsz, maxsz - oprsz); + expand_clr(dbase, dofs + oprsz, maxsz - oprsz); } } =20 +void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, int64_t c, const GVecGen2i *g) +{ + tcg_gen_gvec_2i_var(tcg_env, dofs, tcg_env, aofs, oprsz, maxsz, c, g); +} + /* * Expand a vector operation with two vectors and a scalar, * (dbase+dofs) =3D op(abase+aofs, c). @@ -2279,8 +2292,10 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, = uint32_t aofs, =20 static const TCGOpcode vecop_list_mul[] =3D { INDEX_op_mul_vec, 0 }; =20 -void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_mul_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const GVecGen3 g[4] =3D { { .fniv =3D tcg_gen_mul_vec, @@ -2305,7 +2320,15 @@ void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, = uint32_t aofs, }; =20 tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_mul_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bofs, + oprsz, maxsz); } =20 void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, @@ -2344,8 +2367,10 @@ void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs,= uint32_t aofs, tcg_gen_gvec_muls(vece, dofs, aofs, tmp, oprsz, maxsz); } =20 -void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_ssadd_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_ssadd_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2367,11 +2392,21 @@ void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dof= s, uint32_t aofs, .vece =3D MO_64 }, }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_ssadd_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + +void tcg_gen_gvec_sssub_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_sssub_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2393,7 +2428,15 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs= , uint32_t aofs, .vece =3D MO_64 }, }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_sssub_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); } =20 static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) @@ -2410,8 +2453,10 @@ static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a= , TCGv_i64 b) tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d); } =20 -void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_usadd_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_usadd_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2435,11 +2480,21 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dof= s, uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); } =20 -void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, +void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_usadd_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); +} + +void tcg_gen_gvec_ussub_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_ussub_vec, 0 }; static const GVecGen3 g[4] =3D { @@ -2463,7 +2518,15 @@ void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs= , uint32_t aofs, .vece =3D MO_64 } }; tcg_debug_assert(vece <=3D MO_64); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &g[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &g[vece]); +} + +void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_ussub_var(vece, tcg_env, dofs, tcg_env, aofs, + tcg_env, bofs, oprsz, maxsz); } =20 void tcg_gen_gvec_smin_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, @@ -3131,8 +3194,9 @@ void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, i= nt32_t c) tcg_gen_andi_i32(d, d, mask); } =20 -void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_shri_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_shri_vec, 0 }; static const GVecGen2i g[4] =3D { @@ -3162,12 +3226,20 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs= , uint32_t aofs, tcg_debug_assert(vece <=3D MO_64); tcg_debug_assert(shift >=3D 0 && shift < (8 << vece)); if (shift =3D=3D 0) { - tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + tcg_gen_gvec_mov_var(vece, dbase, dofs, abase, aofs, oprsz, maxsz); } else { - tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); + tcg_gen_gvec_2i_var(dbase, dofs, abase, aofs, oprsz, maxsz, + shift, &g[vece]); } } =20 +void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_shri_var(vece, tcg_env, dofs, tcg_env, aofs, + shift, oprsz, maxsz); +} + void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) { uint64_t s_mask =3D dup_const(MO_8, 0x80 >> c); @@ -3224,8 +3296,9 @@ void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, i= nt32_t c) tcg_temp_free_i32(s); } =20 -void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz) +void tcg_gen_gvec_sari_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_sari_vec, 0 }; static const GVecGen2i g[4] =3D { @@ -3255,12 +3328,20 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs= , uint32_t aofs, tcg_debug_assert(vece <=3D MO_64); tcg_debug_assert(shift >=3D 0 && shift < (8 << vece)); if (shift =3D=3D 0) { - tcg_gen_gvec_mov(vece, dofs, aofs, oprsz, maxsz); + tcg_gen_gvec_mov_var(vece, dbase, dofs, abase, aofs, oprsz, maxsz); } else { - tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, shift, &g[vece]); + tcg_gen_gvec_2i_var(dbase, dofs, abase, aofs, oprsz, maxsz, + shift, &g[vece]); } } =20 +void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz) +{ + tcg_gen_gvec_sari_var(vece, tcg_env, dofs, tcg_env, aofs, + shift, oprsz, maxsz); +} + void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c) { uint64_t mask =3D dup_const(MO_8, 0xff << c); --=20 2.34.1 From nobody Sat Sep 26 20:50:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Thu, 10 Sep 2026 08:32:39 -0700 (PDT) X-Received: by 2002:a05:6870:8a0f:b0:475:e0a7:9f2f with SMTP id 586e51a60fabf-475e0a7aa39mr25457322fac.29.1789054358824; Thu, 10 Sep 2026 08:32:38 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , marco.liebel@oss.qualcomm.com, Helge Deller , Brian Cain , Paolo Bonzini , Laurent Vivier Subject: [PATCH 4/9] target/hexagon: raise an exception for HVX with SSR:XE clear Date: Thu, 10 Sep 2026 08:32:16 -0700 Message-Id: <20260910153221.1674285-5-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260910153221.1674285-1-brian.cain@oss.qualcomm.com> References: <20260910153221.1674285-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=PIaaavqC c=1 sm=1 tr=0 ts=6aa2cd98 cx=c_pps a=zPxD6eHSjdtQ/OcAcrOFGw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=zEVancPc-5b3c_FCZogA:9 a=QEXdDO2ut3YA:10 a=y8BKWJGFn5sdPF1Y92-H:22 X-Proofpoint-GUID: hQDEH40hijQ7pNcL0VKJWqUeSQjE5Ok9 X-Proofpoint-ORIG-GUID: hQDEH40hijQ7pNcL0VKJWqUeSQjE5Ok9 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTEwMDE4NyBTYWx0ZWRfXyybCo+DWZjdB V8kc7+54KI1z1qrgFrmNBxRk3mU55Z32GBF7Rjt3LZZWRS2438nxgYX4vMbFeuYqWWZAsMcKKGW YShTCCoH4LhjzLWxrPBvt154x6mrZuE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTEwMDE4NyBTYWx0ZWRfX6CxFcW3Mor0j OQQKfbM1ZXfmV5ryZ9R9zb9aTieRJB1zYSm9x81Dz1ibpxrdTUdOrY3gS5xKPmGJVROvqmYM96i nchJNfM+zWTGOCR1agTVEi9XJjJrNQvclKxQtn4RqDN+Q9nbE74kESEqRaiAlb7O3I2ky/Q57df ToEcfD/hoYouT0014DHrdvNxYtOTrQxr06BXT9p0Al6skIVqYCj6v/m27vcvDjuHMvrzpioVK7g ZLmtAqIMFFASj5rvgJ5NBkw5HFxgedvA1TQtr6ZaqjYFwQLMgQ4DfcpnKWGNffoAwbGIbnc2eTc cWTXe1TSF41CYPYI5YG4RAdSu+tZplGYmGEoDKWDkRIF3GEkjWYbxHahpkZvtsVvcHh/FZC19sa cANRE7LQrQtnbuWceL4rr0JDdzL3sIfR/uCWoOPdGrl6mvveuTszQSDSIbA8bjZF4EKjEBKQMpz htIHorxlS7256G8uX8Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-10_05,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 suspectscore=0 malwarescore=0 adultscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609100187 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789054486802158500 SSR:XE gates access to the HVX coprocessor: executing an HVX instruction while it is clear must raise a precise exception with cause 0x16, NO_COPROC_ENABLE. Carry SSR:XE in a TB flag and emit the exception for the first HVX packet of a TB when the coprocessor is disabled. Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- target/hexagon/cpu.h | 1 + target/hexagon/translate.h | 2 ++ target/hexagon/cpu.c | 2 ++ target/hexagon/translate.c | 11 +++++++++++ 4 files changed, 16 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 8a4a81dc26c..32cdcfe8529 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -207,6 +207,7 @@ struct ArchCPU { FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) FIELD(TB_FLAGS, MMU_INDEX, 1, 3) FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1) +FIELD(TB_FLAGS, HVX_COPROC_ENABLED, 5, 1) =20 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, uint32_t exception, diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index d8628383f1d..b87a2b20e2f 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -89,6 +89,8 @@ typedef struct DisasContext { TCGv branch_taken; TCGv dczero_addr; bool pcycle_enabled; + bool hvx_coproc_enabled; + bool hvx_check_emitted; uint32_t num_cycles; } DisasContext; =20 diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 4a7b76e3bcc..1109a8d914c 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -331,6 +331,8 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState = *cs) hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, cpu_mmu_index(env_cpu(env), false)); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1); + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED, + GET_SSR_FIELD(SSR_XE, env->t_sreg[HEX_SREG_SSR]= )); #else hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, MMU_USER_IDX); #endif diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 5d3d67e5d3e..b44cf48d757 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -718,6 +718,14 @@ static void gen_start_packet(DisasContext *ctx) i =3D find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + = 1); } } + +#ifndef CONFIG_USER_ONLY + if (ctx->pkt.pkt_has_hvx && !ctx->hvx_coproc_enabled && + !ctx->hvx_check_emitted) { + gen_precise_exception(HEX_CAUSE_NO_COPROC_ENABLE, ctx->pkt.pc); + ctx->hvx_check_emitted =3D true; + } +#endif } =20 bool is_gather_store_insn(DisasContext *ctx) @@ -1235,6 +1243,9 @@ static void hexagon_tr_init_disas_context(DisasContex= tBase *dcbase, #ifndef CONFIG_USER_ONLY ctx->num_cycles =3D 0; ctx->pcycle_enabled =3D FIELD_EX32(hex_flags, TB_FLAGS, PCYCLE_ENABLED= ); + ctx->hvx_coproc_enabled =3D + FIELD_EX32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED); + ctx->hvx_check_emitted =3D false; #endif } =20 --=20 2.34.1 From nobody Sat Sep 26 20:50:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789054428; cv=none; d=zohomail.com; s=zohoarc; b=YjPHAgGGKFRmZgbN5gFZZfS5/zGxly2sKOE9kowRj+dFpkKOgB4qdRmlWEmcX1n694kJYb4ZL+F0RfgItKtK5kzMjr8vXRt1wnDLwqoNS+NywQOLtds8tJDicDD/DkvEHllIwUCm8PecJa4SSRAFmac+canjCUdIZKF/cfyoBWQ= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789054430930158500 The HVX register file belongs to an extension context, not a hw thread. A core has a number of contexts, and each thread's SSR:XA selects the one bound to it. Group the regs into HexagonHVXContext and reach them through CPUHexagonState::hvx. Later patches move the storage into an object that can be shared by vCPUs. Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- target/hexagon/cpu.h | 10 ++++++++-- linux-user/hexagon/cpu_loop.c | 2 ++ target/hexagon/cpu.c | 15 ++++++++------ target/hexagon/gdbstub.c | 16 +++++++-------- target/hexagon/genptr.c | 4 ++-- target/hexagon/op_helper.c | 37 ++++++++++++++++++----------------- target/hexagon/translate.c | 14 ++++++------- target/hexagon/hex_common.py | 5 +++-- 8 files changed, 58 insertions(+), 45 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 32cdcfe8529..c983a9791e1 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -120,6 +120,11 @@ typedef struct { /* Maximum number of vector temps in a packet */ #define VECTOR_TEMPS_MAX 4 =20 +typedef struct HexagonHVXContext { + MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16); + MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); +} HexagonHVXContext; + typedef struct CPUArchState { target_ulong gpr[TOTAL_PER_THREAD_REGS]; target_ulong pred[NUM_PREGS]; @@ -159,11 +164,12 @@ typedef struct CPUArchState { target_ulong llsc_val; uint64_t llsc_val_i64; =20 - MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16); + HexagonHVXContext *hvx; + HexagonHVXContext hvx_ctx QEMU_ALIGNED(16); + MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); =20 - MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); =20 /* Temporaries used within instructions */ diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index e4ef97a1184..ccfb1da86f5 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -33,6 +33,8 @@ void cpu_loop(CPUHexagonState *env) target_ulong syscallnum; target_ulong ret; =20 + env->hvx =3D &env->hvx_ctx; + for (;;) { cpu_exec_start(cs); trapnr =3D cpu_exec(cs); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1109a8d914c..68c50cbcb45 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -182,7 +182,7 @@ static void print_vreg(FILE *f, CPUHexagonState *env, i= nt regnum, if (skip_if_zero) { bool nonzero_found =3D false; for (int i =3D 0; i < MAX_VEC_SIZE_BYTES; i++) { - if (env->VRegs[regnum].ub[i] !=3D 0) { + if (env->hvx->VRegs[regnum].ub[i] !=3D 0) { nonzero_found =3D true; break; } @@ -193,9 +193,10 @@ static void print_vreg(FILE *f, CPUHexagonState *env, = int regnum, } =20 qemu_fprintf(f, " v%d =3D ( ", regnum); - qemu_fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1= ]); + qemu_fprintf(f, "0x%02x", + env->hvx->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]); for (int i =3D MAX_VEC_SIZE_BYTES - 2; i >=3D 0; i--) { - qemu_fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]); + qemu_fprintf(f, ", 0x%02x", env->hvx->VRegs[regnum].ub[i]); } qemu_fprintf(f, " )\n"); } @@ -211,7 +212,7 @@ static void print_qreg(FILE *f, CPUHexagonState *env, i= nt regnum, if (skip_if_zero) { bool nonzero_found =3D false; for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 8; i++) { - if (env->QRegs[regnum].ub[i] !=3D 0) { + if (env->hvx->QRegs[regnum].ub[i] !=3D 0) { nonzero_found =3D true; break; } @@ -223,9 +224,9 @@ static void print_qreg(FILE *f, CPUHexagonState *env, i= nt regnum, =20 qemu_fprintf(f, " q%d =3D ( ", regnum); qemu_fprintf(f, "0x%02x", - env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]); + env->hvx->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]); for (int i =3D MAX_VEC_SIZE_BYTES / 8 - 2; i >=3D 0; i--) { - qemu_fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]); + qemu_fprintf(f, ", 0x%02x", env->hvx->QRegs[regnum].ub[i]); } qemu_fprintf(f, " )\n"); } @@ -419,6 +420,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) mcc->parent_phases.hold(obj, type); } =20 + env->hvx =3D &env->hvx_ctx; + set_default_nan_mode(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_sta= tus); /* Default NaN value: sign bit set, all frac bits set */ diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index b9856cfc978..5e480726b03 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -80,8 +80,8 @@ static int gdb_get_vreg(CPUHexagonState *env, GByteArray = *mem_buf, int n) { int total =3D 0; int i; - for (i =3D 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) { - total +=3D gdb_get_reg32(mem_buf, env->VRegs[n].uw[i]); + for (i =3D 0; i < ARRAY_SIZE(env->hvx->VRegs[n].uw); i++) { + total +=3D gdb_get_reg32(mem_buf, env->hvx->VRegs[n].uw[i]); } return total; } @@ -90,8 +90,8 @@ static int gdb_get_qreg(CPUHexagonState *env, GByteArray = *mem_buf, int n) { int total =3D 0; int i; - for (i =3D 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) { - total +=3D gdb_get_reg32(mem_buf, env->QRegs[n].uw[i]); + for (i =3D 0; i < ARRAY_SIZE(env->hvx->QRegs[n].uw); i++) { + total +=3D gdb_get_reg32(mem_buf, env->hvx->QRegs[n].uw[i]); } return total; } @@ -116,8 +116,8 @@ int hexagon_hvx_gdb_read_register(CPUState *cs, GByteAr= ray *mem_buf, int n) static int gdb_put_vreg(CPUHexagonState *env, uint8_t *mem_buf, int n) { int i; - for (i =3D 0; i < ARRAY_SIZE(env->VRegs[n].uw); i++) { - env->VRegs[n].uw[i] =3D ldl_le_p(mem_buf); + for (i =3D 0; i < ARRAY_SIZE(env->hvx->VRegs[n].uw); i++) { + env->hvx->VRegs[n].uw[i] =3D ldl_le_p(mem_buf); mem_buf +=3D 4; } return MAX_VEC_SIZE_BYTES; @@ -126,8 +126,8 @@ static int gdb_put_vreg(CPUHexagonState *env, uint8_t *= mem_buf, int n) static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n) { int i; - for (i =3D 0; i < ARRAY_SIZE(env->QRegs[n].uw); i++) { - env->QRegs[n].uw[i] =3D ldl_le_p(mem_buf); + for (i =3D 0; i < ARRAY_SIZE(env->hvx->QRegs[n].uw); i++) { + env->hvx->QRegs[n].uw[i] =3D ldl_le_p(mem_buf); mem_buf +=3D 4; } return MAX_VEC_SIZE_BYTES / 8; diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 9f53fcb6b95..257836be227 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -1433,7 +1433,7 @@ static void gen_asr_r_svw_trun(DisasContext *ctx, TCG= v RdV, =20 static intptr_t vreg_src_off(DisasContext *ctx, int num) { - intptr_t offset =3D offsetof(CPUHexagonState, VRegs[num]); + intptr_t offset =3D offsetof(CPUHexagonState, hvx_ctx.VRegs[num]); =20 if (test_bit(num, ctx->vregs_select)) { offset =3D ctx_future_vreg_off(ctx, num, 1, false); @@ -1473,7 +1473,7 @@ static intptr_t get_result_qreg(DisasContext *ctx, in= t qnum) if (ctx->need_commit) { return offsetof(CPUHexagonState, future_QRegs[qnum]); } else { - return offsetof(CPUHexagonState, QRegs[qnum]); + return offsetof(CPUHexagonState, hvx_ctx.QRegs[qnum]); } } =20 diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 7ad99ced7ab..cb9bc7e4317 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1408,7 +1408,8 @@ void HELPER(vhist)(CPUHexagonState *env) unsigned char regno =3D value >> 3; unsigned char element =3D value & 7; =20 - env->VRegs[regno].uh[(sizeof(MMVector) / 16) * lane + element]= ++; + env->hvx->VRegs[regno] + .uh[(sizeof(MMVector) / 16) * lane + element]++; } } } @@ -1424,7 +1425,7 @@ void HELPER(vhistq)(CPUHexagonState *env) unsigned char element =3D value & 7; =20 if (fGETQBIT(env->qtmp, sizeof(MMVector) / 8 * lane + i)) { - env->VRegs[regno].uh[ + env->hvx->VRegs[regno].uh[ (sizeof(MMVector) / 16) * lane + element]++; } } @@ -1441,8 +1442,8 @@ void HELPER(vwhist256)(CPUHexagonState *env) unsigned int vindex =3D (bucket >> 3) & 0x1F; unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); =20 - env->VRegs[vindex].uh[elindex] =3D - env->VRegs[vindex].uh[elindex] + weight; + env->hvx->VRegs[vindex].uh[elindex] =3D + env->hvx->VRegs[vindex].uh[elindex] + weight; } } =20 @@ -1457,8 +1458,8 @@ void HELPER(vwhist256q)(CPUHexagonState *env) unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); =20 if (fGETQBIT(env->qtmp, 2 * i)) { - env->VRegs[vindex].uh[elindex] =3D - env->VRegs[vindex].uh[elindex] + weight; + env->hvx->VRegs[vindex].uh[elindex] =3D + env->hvx->VRegs[vindex].uh[elindex] + weight; } } } @@ -1473,8 +1474,8 @@ void HELPER(vwhist256_sat)(CPUHexagonState *env) unsigned int vindex =3D (bucket >> 3) & 0x1F; unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); =20 - env->VRegs[vindex].uh[elindex] =3D - fVSATUH(env->VRegs[vindex].uh[elindex] + weight); + env->hvx->VRegs[vindex].uh[elindex] =3D + fVSATUH(env->hvx->VRegs[vindex].uh[elindex] + weight); } } =20 @@ -1489,8 +1490,8 @@ void HELPER(vwhist256q_sat)(CPUHexagonState *env) unsigned int elindex =3D ((i >> 0) & (~7)) | ((bucket >> 0) & 7); =20 if (fGETQBIT(env->qtmp, 2 * i)) { - env->VRegs[vindex].uh[elindex] =3D - fVSATUH(env->VRegs[vindex].uh[elindex] + weight); + env->hvx->VRegs[vindex].uh[elindex] =3D + fVSATUH(env->hvx->VRegs[vindex].uh[elindex] + weight); } } } @@ -1505,8 +1506,8 @@ void HELPER(vwhist128)(CPUHexagonState *env) unsigned int vindex =3D (bucket >> 3) & 0x1F; unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); =20 - env->VRegs[vindex].uw[elindex] =3D - env->VRegs[vindex].uw[elindex] + weight; + env->hvx->VRegs[vindex].uw[elindex] =3D + env->hvx->VRegs[vindex].uw[elindex] + weight; } } =20 @@ -1521,8 +1522,8 @@ void HELPER(vwhist128q)(CPUHexagonState *env) unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); =20 if (fGETQBIT(env->qtmp, 2 * i)) { - env->VRegs[vindex].uw[elindex] =3D - env->VRegs[vindex].uw[elindex] + weight; + env->hvx->VRegs[vindex].uw[elindex] =3D + env->hvx->VRegs[vindex].uw[elindex] + weight; } } } @@ -1538,8 +1539,8 @@ void HELPER(vwhist128m)(CPUHexagonState *env, int32_t= uiV) unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); =20 if ((bucket & 1) =3D=3D uiV) { - env->VRegs[vindex].uw[elindex] =3D - env->VRegs[vindex].uw[elindex] + weight; + env->hvx->VRegs[vindex].uw[elindex] =3D + env->hvx->VRegs[vindex].uw[elindex] + weight; } } } @@ -1555,8 +1556,8 @@ void HELPER(vwhist128qm)(CPUHexagonState *env, int32_= t uiV) unsigned int elindex =3D ((i >> 1) & (~3)) | ((bucket >> 1) & 3); =20 if (((bucket & 1) =3D=3D uiV) && fGETQBIT(env->qtmp, 2 * i)) { - env->VRegs[vindex].uw[elindex] =3D - env->VRegs[vindex].uw[elindex] + weight; + env->hvx->VRegs[vindex].uw[elindex] =3D + env->hvx->VRegs[vindex].uw[elindex] + weight; } } } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index b44cf48d757..b05ac91846a 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -87,7 +87,7 @@ intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnu= m, intptr_t offset; =20 if (!ctx->need_commit) { - return offsetof(CPUHexagonState, VRegs[regnum]); + return offsetof(CPUHexagonState, hvx_ctx.VRegs[regnum]); } =20 /* See if it is already allocated */ @@ -697,7 +697,7 @@ static void gen_start_packet(DisasContext *ctx) while (i < NUM_VREGS) { const intptr_t VdV_off =3D ctx_future_vreg_off(ctx, i, 1, true); - intptr_t src_off =3D offsetof(CPUHexagonState, VRegs[i]); + intptr_t src_off =3D offsetof(CPUHexagonState, hvx_ctx.VRegs[i= ]); tcg_gen_gvec_mov(MO_64, VdV_off, src_off, sizeof(MMVector), @@ -710,7 +710,7 @@ static void gen_start_packet(DisasContext *ctx) while (i < NUM_VREGS) { const intptr_t VdV_off =3D ctx_tmp_vreg_off(ctx, i, 1, true); - intptr_t src_off =3D offsetof(CPUHexagonState, VRegs[i]); + intptr_t src_off =3D offsetof(CPUHexagonState, hvx_ctx.VRegs[i= ]); tcg_gen_gvec_mov(MO_64, VdV_off, src_off, sizeof(MMVector), @@ -1012,12 +1012,12 @@ static void gen_commit_hvx(DisasContext *ctx) /* * for (i =3D 0; i < ctx->vreg_log_idx; i++) { * int rnum =3D ctx->vreg_log[i]; - * env->VRegs[rnum] =3D env->future_VRegs[rnum]; + * env->hvx->VRegs[rnum] =3D env->future_VRegs[rnum]; * } */ for (i =3D 0; i < ctx->vreg_log_idx; i++) { int rnum =3D ctx->vreg_log[i]; - intptr_t dstoff =3D offsetof(CPUHexagonState, VRegs[rnum]); + intptr_t dstoff =3D offsetof(CPUHexagonState, hvx_ctx.VRegs[rnum]); intptr_t srcoff =3D ctx_future_vreg_off(ctx, rnum, 1, false); size_t size =3D sizeof(MMVector); =20 @@ -1027,12 +1027,12 @@ static void gen_commit_hvx(DisasContext *ctx) /* * for (i =3D 0; i < ctx->qreg_log_idx; i++) { * int rnum =3D ctx->qreg_log[i]; - * env->QRegs[rnum] =3D env->future_QRegs[rnum]; + * env->hvx->QRegs[rnum] =3D env->future_QRegs[rnum]; * } */ for (i =3D 0; i < ctx->qreg_log_idx; i++) { int rnum =3D ctx->qreg_log[i]; - intptr_t dstoff =3D offsetof(CPUHexagonState, QRegs[rnum]); + intptr_t dstoff =3D offsetof(CPUHexagonState, hvx_ctx.QRegs[rnum]); intptr_t srcoff =3D offsetof(CPUHexagonState, future_QRegs[rnum]); size_t size =3D sizeof(MMQReg); =20 diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index c180c19b092..ea3163132d9 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -1050,7 +1050,7 @@ def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ const intptr_t {self.hvx_off()} =3D - offsetof(CPUHexagonState, QRegs[{self.reg_num}]); + offsetof(CPUHexagonState, hvx_ctx.QRegs[{self.reg_num}]); """)) if not skip_qemu_helper(tag): f.write(code_fmt(f"""\ @@ -1073,7 +1073,8 @@ def decl_tcg(self, f, tag, regno): const intptr_t {self.hvx_off()} =3D get_result_qreg(ctx, {self.reg_num}); tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - offsetof(CPUHexagonState, QRegs[{self.reg_num= }]), + offsetof(CPUHexagonState, + hvx_ctx.QRegs[{self.reg_num}]), sizeof(MMQReg), sizeof(MMQReg)); """)) if not skip_qemu_helper(tag): --=20 2.34.1 From nobody Sat Sep 26 20:50:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789054503; cv=none; d=zohomail.com; s=zohoarc; b=cjgXz545d/lOrFlaZMnfJnXqrabxnkIfaMg7gIQr3qosw+fgBp14Izg5BssLWwJXzaraIMNzf4J7WsA8D9OzWptXqfRfAn/60J7R4uOOX1boOQIqsIUdSZar8Ky636HiHp60AcQU4UYXE/YRaLK/WbeNCXodnAO2z3jsMvHKers= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789054505202158500 An HVX register operand was a bare offset from env. That works only while the register file was part of CPUHexagonState. When it moves to an HVX context shared between hardware threads, its address is not a translation-time constant. While here, fold the repeated helper-argument pointer setup in hex_common.py into Hvx.decl_tcg_ptr(). Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- target/hexagon/gen_tcg_hvx.h | 608 +++++++++++++++++++--------------- target/hexagon/genptr.h | 8 + target/hexagon/mmvec/macros.h | 14 +- target/hexagon/translate.h | 5 +- target/hexagon/genptr.c | 102 +++--- target/hexagon/translate.c | 58 ++-- target/hexagon/hex_common.py | 181 +++++----- 7 files changed, 563 insertions(+), 413 deletions(-) diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h index 2a342cdee69..f399291dc66 100644 --- a/target/hexagon/gen_tcg_hvx.h +++ b/target/hexagon/gen_tcg_hvx.h @@ -49,8 +49,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vhistq(tcg_env); \ @@ -65,8 +65,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vwhist256q(tcg_env); \ @@ -81,8 +81,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vwhist256q_sat(tcg_env); \ @@ -97,8 +97,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ gen_helper_vwhist128q(tcg_env); \ @@ -114,8 +114,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ if (ctx->pre_commit) { \ intptr_t dstoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_mov(MO_64, dstoff, QvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, QvV_base, QvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ } else { \ TCGv tcgv_uiV =3D tcg_constant_tl(uiV); \ assert_vhist_tmp(ctx); \ @@ -125,19 +125,20 @@ static inline void assert_vhist_tmp(DisasContext *ctx) =20 =20 #define fGEN_TCG_V6_vassign(SHORTCODE) \ - tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vassign_tmp(SHORTCODE) \ - tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vcombine_tmp(SHORTCODE) \ do { \ - tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), VuV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, VvV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off + sizeof(MMVector)= , \ + VuV_base, VuV_off, sizeof(MMVector), \ + sizeof(MMVector)); \ } while (0) =20 /* @@ -148,18 +149,20 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_V6_vcombine(SHORTCODE) \ do { \ if (VddV_off !=3D VuV_off) { \ - tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), VuV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, \ + VvV_off, sizeof(MMVector), sizeof(MMVecto= r)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, \ + VddV_off + sizeof(MMVector), VuV_base, \ + VuV_off, sizeof(MMVector), sizeof(MMVecto= r)); \ } else { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ - tcg_gen_gvec_mov(MO_64, tmpoff, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), tmpoff, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, tcg_env, tmpoff, VuV_base, VuV_off= , \ + sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, VddV_off, VvV_base, \ + VvV_off, sizeof(MMVector), sizeof(MMVecto= r)); \ + tcg_gen_gvec_mov_var(MO_64, VddV_base, \ + VddV_off + sizeof(MMVector), tcg_env, tmp= off, \ + sizeof(MMVector), sizeof(MMVector)); \ } \ } while (0) =20 @@ -170,8 +173,8 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGLabel *false_label =3D gen_new_label(); \ tcg_gen_andi_tl(lsb, PsV, 1); \ tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \ - tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)); \ gen_set_label(false_label); \ } while (0) =20 @@ -186,231 +189,276 @@ static inline void assert_vhist_tmp(DisasContext *c= tx) =20 /* Vector add - various forms */ #define fGEN_TCG_V6_vaddb(SHORTCODE) \ - tcg_gen_gvec_add(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_add_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, VvV_b= ase, \ + VvV_off, sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vaddh(SHORTCYDE) \ - tcg_gen_gvec_add(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_add_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vaddw(SHORTCODE) \ - tcg_gen_gvec_add(MO_32, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_add_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vaddb_dv(SHORTCODE) \ - tcg_gen_gvec_add(MO_8, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_add_var(MO_8, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 #define fGEN_TCG_V6_vaddh_dv(SHORTCYDE) \ - tcg_gen_gvec_add(MO_16, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_add_var(MO_16, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 #define fGEN_TCG_V6_vaddw_dv(SHORTCODE) \ - tcg_gen_gvec_add(MO_32, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_add_var(MO_32, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 /* Vector sub - various forms */ #define fGEN_TCG_V6_vsubb(SHORTCODE) \ - tcg_gen_gvec_sub(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_sub_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, VvV_b= ase, \ + VvV_off, sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vsubh(SHORTCODE) \ - tcg_gen_gvec_sub(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_sub_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vsubw(SHORTCODE) \ - tcg_gen_gvec_sub(MO_32, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_sub_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vsubb_dv(SHORTCODE) \ - tcg_gen_gvec_sub(MO_8, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_sub_var(MO_8, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 #define fGEN_TCG_V6_vsubh_dv(SHORTCODE) \ - tcg_gen_gvec_sub(MO_16, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_sub_var(MO_16, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 #define fGEN_TCG_V6_vsubw_dv(SHORTCODE) \ - tcg_gen_gvec_sub(MO_32, VddV_off, VuuV_off, VvvV_off, \ - sizeof(MMVector) * 2, sizeof(MMVector) * 2) + tcg_gen_gvec_sub_var(MO_32, VddV_base, VddV_off, VuuV_base, VuuV_off, \ + VvvV_base, VvvV_off, sizeof(MMVector) * 2, \ + sizeof(MMVector) * 2) =20 #define fGEN_TCG_V6_vaddbsat(SHORTCODE) \ - tcg_gen_gvec_ssadd(MO_8, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ssadd_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddhsat(SHORTCODE) \ - tcg_gen_gvec_ssadd(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ssadd_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddwsat(SHORTCODE) \ - tcg_gen_gvec_ssadd(MO_32, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ssadd_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddubsat(SHORTCODE) \ - tcg_gen_gvec_usadd(MO_8, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_usadd_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vadduhsat(SHORTCODE) \ - tcg_gen_gvec_usadd(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_usadd_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vadduwsat(SHORTCODE) \ - tcg_gen_gvec_usadd(MO_32, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_usadd_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 -#define fGEN_TCG_PAIR_ADDSUB(OP, VECE, DST, SRC_A, SRC_B) \ - tcg_gen_gvec_##OP(VECE, DST, SRC_A, SRC_B, \ - 2 * VECTOR_SIZE_BYTE, 2 * VECTOR_SIZE_BYTE) +#define fGEN_TCG_PAIR_ADDSUB(OP, VECE, DBASE, DST, ABASE, SRC_A, BBASE, SR= C_B) \ + tcg_gen_gvec_##OP##_var(VECE, DBASE, DST, ABASE, SRC_A, BBASE, SRC_B, \ + 2 * VECTOR_SIZE_BYTE, 2 * VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vaddbsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ssadd, MO_8, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ssadd, MO_8, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vaddhsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ssadd, MO_16, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ssadd, MO_16, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vaddwsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ssadd, MO_32, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ssadd, MO_32, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vaddubsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(usadd, MO_8, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(usadd, MO_8, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vadduhsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(usadd, MO_16, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(usadd, MO_16, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vadduwsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(usadd, MO_32, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(usadd, MO_32, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsubbsat(SHORTCODE) \ - tcg_gen_gvec_sssub(MO_8, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_sssub_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubhsat(SHORTCODE) \ - tcg_gen_gvec_sssub(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_sssub_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubwsat(SHORTCODE) \ - tcg_gen_gvec_sssub(MO_32, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_sssub_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsububsat(SHORTCODE) \ - tcg_gen_gvec_ussub(MO_8, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ussub_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubuhsat(SHORTCODE) \ - tcg_gen_gvec_ussub(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ussub_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubuwsat(SHORTCODE) \ - tcg_gen_gvec_ussub(MO_32, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_ussub_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vsubbsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(sssub, MO_8, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(sssub, MO_8, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsubhsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(sssub, MO_16, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(sssub, MO_16, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsubwsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(sssub, MO_32, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(sssub, MO_32, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsububsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ussub, MO_8, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ussub, MO_8, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsubuhsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ussub, MO_16, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ussub, MO_16, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vsubuwsat_dv(SHORTCODE) \ - fGEN_TCG_PAIR_ADDSUB(ussub, MO_32, VddV_off, VuuV_off, VvvV_off) + fGEN_TCG_PAIR_ADDSUB(ussub, MO_32, VddV_base, VddV_off, \ + VuuV_base, VuuV_off, VvvV_base, VvvV_off) =20 #define fGEN_TCG_V6_vmpyih(SHORTCODE) \ - tcg_gen_gvec_mul(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + tcg_gen_gvec_mul_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vabsdiffub(SHORTCODE) \ - gen_gvec_uabsdiff(MO_8, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + gen_gvec_uabsdiff_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vabsdiffuh(SHORTCODE) \ - gen_gvec_uabsdiff(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + gen_gvec_uabsdiff_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vabsdiffh(SHORTCODE) \ - gen_gvec_sabsdiff(MO_16, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + gen_gvec_sabsdiff_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_V6_vabsdiffw(SHORTCODE) \ - gen_gvec_sabsdiff(MO_32, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) + gen_gvec_sabsdiff_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE) =20 #define fGEN_TCG_VEC_AVG(VECE, SHIFT_FN) \ do { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ - tcg_gen_gvec_and(MO_64, tmpoff, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - SHIFT_FN(VECE, VdV_off, VdV_off, 1, \ + tcg_gen_gvec_and_var(MO_64, tcg_env, tmpoff, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + tcg_gen_gvec_xor_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + SHIFT_FN(VECE, VdV_base, VdV_off, VdV_base, VdV_off, 1, \ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - tcg_gen_gvec_add(VECE, VdV_off, tmpoff, VdV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + tcg_gen_gvec_add_var(VECE, VdV_base, VdV_off, tcg_env, tmpoff, \ + VdV_base, VdV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vavgub(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavguh(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavguw(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavgb(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVG(MO_8, tcg_gen_gvec_sari_var) =20 #define fGEN_TCG_V6_vavgh(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVG(MO_16, tcg_gen_gvec_sari_var) =20 #define fGEN_TCG_V6_vavgw(SHORTCODE) \ - fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVG(MO_32, tcg_gen_gvec_sari_var) =20 #define fGEN_TCG_VEC_AVGRND(VECE, SHIFT_FN) \ do { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ - tcg_gen_gvec_or(MO_64, tmpoff, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - SHIFT_FN(VECE, VdV_off, VdV_off, 1, \ + tcg_gen_gvec_or_var(MO_64, tcg_env, tmpoff, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + tcg_gen_gvec_xor_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + SHIFT_FN(VECE, VdV_base, VdV_off, VdV_base, VdV_off, 1, \ VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ - tcg_gen_gvec_sub(VECE, VdV_off, tmpoff, VdV_off, \ - VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ + tcg_gen_gvec_sub_var(VECE, VdV_base, VdV_off, tcg_env, tmpoff, \ + VdV_base, VdV_off, \ + VECTOR_SIZE_BYTE, VECTOR_SIZE_BYTE); \ } while (0) =20 #define fGEN_TCG_V6_vavgubrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavguhrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavguwrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_shri) + fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_shri_var) =20 #define fGEN_TCG_V6_vavgbrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVGRND(MO_8, tcg_gen_gvec_sari_var) =20 #define fGEN_TCG_V6_vavghrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVGRND(MO_16, tcg_gen_gvec_sari_var) =20 #define fGEN_TCG_V6_vavgwrnd(SHORTCODE) \ - fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_sari) + fGEN_TCG_VEC_AVGRND(MO_32, tcg_gen_gvec_sari_var) =20 /* Vector shift right - various forms */ #define fGEN_TCG_V6_vasrh(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ - tcg_gen_gvec_sars(MO_16, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_sars_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vasrh_acc(SHORTCODE) \ @@ -418,18 +466,19 @@ static inline void assert_vhist_tmp(DisasContext *ctx) intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ - tcg_gen_gvec_sars(MO_16, tmpoff, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_sars_var(MO_16, tcg_env, tmpoff, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_add_var(MO_16, VxV_base, VxV_off, VxV_base, VxV_off, \ + tcg_env, tmpoff, sizeof(MMVector), \ + sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vasrw(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ - tcg_gen_gvec_sars(MO_32, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_sars_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vasrw_acc(SHORTCODE) \ @@ -437,34 +486,35 @@ static inline void assert_vhist_tmp(DisasContext *ctx) intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ - tcg_gen_gvec_sars(MO_32, tmpoff, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_sars_var(MO_32, tcg_env, tmpoff, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_add_var(MO_32, VxV_base, VxV_off, VxV_base, VxV_off, \ + tcg_env, tmpoff, sizeof(MMVector), \ + sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vlsrb(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 7); \ - tcg_gen_gvec_shrs(MO_8, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shrs_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vlsrh(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ - tcg_gen_gvec_shrs(MO_16, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shrs_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vlsrw(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ - tcg_gen_gvec_shrs(MO_32, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shrs_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 /* Vector shift left - various forms */ @@ -472,16 +522,16 @@ static inline void assert_vhist_tmp(DisasContext *ctx) do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 7); \ - tcg_gen_gvec_shls(MO_8, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shls_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vaslh(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ - tcg_gen_gvec_shls(MO_16, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shls_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vaslh_acc(SHORTCODE) \ @@ -489,18 +539,19 @@ static inline void assert_vhist_tmp(DisasContext *ctx) intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 15); \ - tcg_gen_gvec_shls(MO_16, tmpoff, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shls_var(MO_16, tcg_env, tmpoff, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_add_var(MO_16, VxV_base, VxV_off, VxV_base, VxV_off, \ + tcg_env, tmpoff, sizeof(MMVector), \ + sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vaslw(SHORTCODE) \ do { \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ - tcg_gen_gvec_shls(MO_32, VdV_off, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shls_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off,= \ + shift, sizeof(MMVector), sizeof(MMVector)); \ } while (0) =20 #define fGEN_TCG_V6_vaslw_acc(SHORTCODE) \ @@ -508,95 +559,109 @@ static inline void assert_vhist_tmp(DisasContext *ct= x) intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ TCGv shift =3D tcg_temp_new(); \ tcg_gen_andi_tl(shift, RtV, 31); \ - tcg_gen_gvec_shls(MO_32, tmpoff, VuV_off, shift, \ - sizeof(MMVector), sizeof(MMVector)); \ - tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \ - sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_shls_var(MO_32, tcg_env, tmpoff, VuV_base, VuV_off, \ + shift, sizeof(MMVector), sizeof(MMVector)); \ + tcg_gen_gvec_add_var(MO_32, VxV_base, VxV_off, VxV_base, VxV_off, \ + tcg_env, tmpoff, sizeof(MMVector), \ + sizeof(MMVector)); \ } while (0) =20 /* Vector max - various forms */ #define fGEN_TCG_V6_vmaxw(SHORTCODE) \ - tcg_gen_gvec_smax(MO_32, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smax_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vmaxh(SHORTCODE) \ - tcg_gen_gvec_smax(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smax_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vmaxuh(SHORTCODE) \ - tcg_gen_gvec_umax(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_umax_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vmaxb(SHORTCODE) \ - tcg_gen_gvec_smax(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smax_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vmaxub(SHORTCODE) \ - tcg_gen_gvec_umax(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_umax_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 /* Vector min - various forms */ #define fGEN_TCG_V6_vminw(SHORTCODE) \ - tcg_gen_gvec_smin(MO_32, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smin_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vminh(SHORTCODE) \ - tcg_gen_gvec_smin(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smin_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vminuh(SHORTCODE) \ - tcg_gen_gvec_umin(MO_16, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_umin_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vminb(SHORTCODE) \ - tcg_gen_gvec_smin(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_smin_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) #define fGEN_TCG_V6_vminub(SHORTCODE) \ - tcg_gen_gvec_umin(MO_8, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_umin_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 /* Vector logical ops */ #define fGEN_TCG_V6_vxor(SHORTCODE) \ - tcg_gen_gvec_xor(MO_64, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_xor_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vand(SHORTCODE) \ - tcg_gen_gvec_and(MO_64, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_and_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)) =20 #define fGEN_TCG_V6_vor(SHORTCODE) \ - tcg_gen_gvec_or(MO_64, VdV_off, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_or_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, VvV_b= ase, \ + VvV_off, sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vnot(SHORTCODE) \ - tcg_gen_gvec_not(MO_64, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_not_var(MO_64, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 /* Q register logical ops */ #define fGEN_TCG_V6_pred_or(SHORTCODE) \ - tcg_gen_gvec_or(MO_64, QdV_off, QsV_off, QtV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_or_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, QtV_b= ase, \ + QtV_off, sizeof(MMQReg), sizeof(MMQReg)) =20 #define fGEN_TCG_V6_pred_and(SHORTCODE) \ - tcg_gen_gvec_and(MO_64, QdV_off, QsV_off, QtV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_and_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, \ + QtV_base, QtV_off, sizeof(MMQReg), sizeof(MMQReg)) =20 #define fGEN_TCG_V6_pred_xor(SHORTCODE) \ - tcg_gen_gvec_xor(MO_64, QdV_off, QsV_off, QtV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_xor_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, \ + QtV_base, QtV_off, sizeof(MMQReg), sizeof(MMQReg)) =20 #define fGEN_TCG_V6_pred_or_n(SHORTCODE) \ - tcg_gen_gvec_orc(MO_64, QdV_off, QsV_off, QtV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_orc_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, \ + QtV_base, QtV_off, sizeof(MMQReg), sizeof(MMQReg)) =20 #define fGEN_TCG_V6_pred_and_n(SHORTCODE) \ - tcg_gen_gvec_andc(MO_64, QdV_off, QsV_off, QtV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_andc_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, \ + QtV_base, QtV_off, sizeof(MMQReg), sizeof(MMQReg= )) =20 #define fGEN_TCG_V6_pred_not(SHORTCODE) \ - tcg_gen_gvec_not(MO_64, QdV_off, QsV_off, \ - sizeof(MMQReg), sizeof(MMQReg)) + tcg_gen_gvec_not_var(MO_64, QdV_base, QdV_off, QsV_base, QsV_off, \ + sizeof(MMQReg), sizeof(MMQReg)) =20 /* Vector compares */ #define fGEN_TCG_VEC_CMP(COND, TYPE, SIZE) \ do { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ - tcg_gen_gvec_cmp(COND, TYPE, tmpoff, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - vec_to_qvec(SIZE, QdV_off, tmpoff); \ + tcg_gen_gvec_cmp_var(COND, TYPE, tcg_env, tmpoff, VuV_base, VuV_of= f, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)); \ + vec_to_qvec(SIZE, QdV_base, QdV_off, tcg_env, tmpoff); \ } while (0) =20 #define fGEN_TCG_V6_vgtw(SHORTCODE) \ @@ -624,100 +689,102 @@ static inline void assert_vhist_tmp(DisasContext *c= tx) do { \ intptr_t tmpoff =3D offsetof(CPUHexagonState, vtmp); \ intptr_t qoff =3D offsetof(CPUHexagonState, qtmp); \ - tcg_gen_gvec_cmp(COND, TYPE, tmpoff, VuV_off, VvV_off, \ - sizeof(MMVector), sizeof(MMVector)); \ - vec_to_qvec(SIZE, qoff, tmpoff); \ - OP(MO_64, QxV_off, QxV_off, qoff, sizeof(MMQReg), sizeof(MMQReg));= \ + tcg_gen_gvec_cmp_var(COND, TYPE, tcg_env, tmpoff, VuV_base, VuV_of= f, \ + VvV_base, VvV_off, sizeof(MMVector), \ + sizeof(MMVector)); \ + vec_to_qvec(SIZE, tcg_env, qoff, tcg_env, tmpoff); \ + OP(MO_64, QxV_base, QxV_off, QxV_base, QxV_off, tcg_env, qoff, \ + sizeof(MMQReg), sizeof(MMQReg)); \ } while (0) =20 #define fGEN_TCG_V6_vgtw_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgtw_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgtw_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_32, 4, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_vgtuw_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgtuw_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgtuw_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_32, 4, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_vgth_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgth_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgth_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_16, 2, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_vgtuh_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgtuh_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgtuh_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_16, 2, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_vgtb_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgtb_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgtb_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GT, MO_8, 1, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_vgtub_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_vgtub_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_vgtub_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_GTU, MO_8, 1, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_veqw_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_veqw_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_veqw_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_32, 4, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_veqh_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_veqh_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_veqh_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_16, 2, tcg_gen_gvec_xor_var) =20 #define fGEN_TCG_V6_veqb_and(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_and) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_and_var) #define fGEN_TCG_V6_veqb_or(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_or) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_or_var) #define fGEN_TCG_V6_veqb_xor(SHORTCODE) \ - fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_xor) + fGEN_TCG_VEC_CMP_OP(TCG_COND_EQ, MO_8, 1, tcg_gen_gvec_xor_var) =20 /* Vector splat - various forms */ #define fGEN_TCG_V6_lvsplatw(SHORTCODE) \ - tcg_gen_gvec_dup_i32(MO_32, VdV_off, \ - sizeof(MMVector), sizeof(MMVector), RtV) + tcg_gen_gvec_dup_i32_var(MO_32, VdV_base, VdV_off, sizeof(MMVector), \ + sizeof(MMVector), RtV) =20 #define fGEN_TCG_V6_lvsplath(SHORTCODE) \ - tcg_gen_gvec_dup_i32(MO_16, VdV_off, \ - sizeof(MMVector), sizeof(MMVector), RtV) + tcg_gen_gvec_dup_i32_var(MO_16, VdV_base, VdV_off, sizeof(MMVector), \ + sizeof(MMVector), RtV) =20 #define fGEN_TCG_V6_lvsplatb(SHORTCODE) \ - tcg_gen_gvec_dup_i32(MO_8, VdV_off, \ - sizeof(MMVector), sizeof(MMVector), RtV) + tcg_gen_gvec_dup_i32_var(MO_8, VdV_base, VdV_off, sizeof(MMVector), \ + sizeof(MMVector), RtV) =20 /* Vector absolute value - various forms */ #define fGEN_TCG_V6_vabsb(SHORTCODE) \ - tcg_gen_gvec_abs(MO_8, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_abs_var(MO_8, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vabsh(SHORTCODE) \ - tcg_gen_gvec_abs(MO_16, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_abs_var(MO_16, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 #define fGEN_TCG_V6_vabsw(SHORTCODE) \ - tcg_gen_gvec_abs(MO_32, VdV_off, VuV_off, \ - sizeof(MMVector), sizeof(MMVector)) + tcg_gen_gvec_abs_var(MO_32, VdV_base, VdV_off, VuV_base, VuV_off, \ + sizeof(MMVector), sizeof(MMVector)) =20 /* Vector loads */ #define fGEN_TCG_V6_vL32b_pi(SHORTCODE) SHORTCODE @@ -743,14 +810,14 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_V6_vL32b_nt_tmp_ppu(SHORTCODE) SHORTCODE =20 /* Predicated vector loads */ -#define fGEN_TCG_PRED_VEC_LOAD(GET_EA, PRED, DSTOFF, INC) \ +#define fGEN_TCG_PRED_VEC_LOAD(GET_EA, PRED, DST, INC) \ do { \ TCGv LSB =3D tcg_temp_new(); \ TCGLabel *false_label =3D gen_new_label(); \ GET_EA; \ PRED; \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ - gen_vreg_load(ctx, DSTOFF, EA, true); \ + gen_vreg_load(ctx, DST##_base, DST##_off, EA, true); \ INC; \ gen_set_label(false_label); \ } while (0) @@ -758,12 +825,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_PRED_VEC_LOAD_pred_pi \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ fEA_REG(RxV), \ - VdV_off, \ + VdV, \ fPM_I(RxV, siV * sizeof(MMVector))) #define fGEN_TCG_PRED_VEC_LOAD_npred_pi \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - VdV_off, \ + VdV, \ fPM_I(RxV, siV * sizeof(MMVector))) =20 #define fGEN_TCG_V6_vL32b_pred_pi(SHORTCODE) \ @@ -794,12 +861,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_PRED_VEC_LOAD_pred_ai \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - VdV_off, \ + VdV, \ do {} while (0)) #define fGEN_TCG_PRED_VEC_LOAD_npred_ai \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - VdV_off, \ + VdV, \ do {} while (0)) =20 #define fGEN_TCG_V6_vL32b_pred_ai(SHORTCODE) \ @@ -830,12 +897,12 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_PRED_VEC_LOAD_pred_ppu \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLD(PvV), \ fEA_REG(RxV), \ - VdV_off, \ + VdV, \ fPM_M(RxV, MuV)) #define fGEN_TCG_PRED_VEC_LOAD_npred_ppu \ fGEN_TCG_PRED_VEC_LOAD(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - VdV_off, \ + VdV, \ fPM_M(RxV, MuV)) =20 #define fGEN_TCG_V6_vL32b_pred_ppu(SHORTCODE) \ @@ -878,7 +945,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_NEWVAL_VEC_STORE(GET_EA, INC) \ do { \ GET_EA; \ - gen_vreg_store(ctx, EA, OsN_off, insn->slot, true); \ + gen_vreg_store(ctx, EA, OsN_base, OsN_off, insn->slot, true); \ INC; \ } while (0) =20 @@ -908,14 +975,15 @@ static inline void assert_vhist_tmp(DisasContext *ctx) fGEN_TCG_NEWVAL_VEC_STORE_ppu =20 /* Predicated vector stores */ -#define fGEN_TCG_PRED_VEC_STORE(GET_EA, PRED, SRCOFF, ALIGN, INC) \ +#define fGEN_TCG_PRED_VEC_STORE(GET_EA, PRED, SRC, ALIGN, INC) \ do { \ TCGv LSB =3D tcg_temp_new(); \ TCGLabel *false_label =3D gen_new_label(); \ GET_EA; \ PRED; \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ - gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \ + gen_vreg_store(ctx, EA, SRC##_base, SRC##_off, insn->slot, \ + ALIGN); \ INC; \ gen_set_label(false_label); \ } while (0) @@ -923,22 +991,22 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_PRED_VEC_STORE_pred_pi(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_REG(RxV), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ fPM_I(RxV, siV * sizeof(MMVector))) #define fGEN_TCG_PRED_VEC_STORE_npred_pi(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ fPM_I(RxV, siV * sizeof(MMVector))) #define fGEN_TCG_PRED_VEC_STORE_new_pred_pi \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_REG(RxV), \ - OsN_off, true, \ + OsN, true, \ fPM_I(RxV, siV * sizeof(MMVector))) #define fGEN_TCG_PRED_VEC_STORE_new_npred_pi \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - OsN_off, true, \ + OsN, true, \ fPM_I(RxV, siV * sizeof(MMVector))) =20 #define fGEN_TCG_V6_vS32b_pred_pi(SHORTCODE) \ @@ -965,22 +1033,22 @@ static inline void assert_vhist_tmp(DisasContext *ct= x) #define fGEN_TCG_PRED_VEC_STORE_pred_ai(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ do { } while (0)) #define fGEN_TCG_PRED_VEC_STORE_npred_ai(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ do { } while (0)) #define fGEN_TCG_PRED_VEC_STORE_new_pred_ai \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - OsN_off, true, \ + OsN, true, \ do { } while (0)) #define fGEN_TCG_PRED_VEC_STORE_new_npred_ai \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_RI(RtV, siV * sizeof(MMVector)), \ - OsN_off, true, \ + OsN, true, \ do { } while (0)) =20 #define fGEN_TCG_V6_vS32b_pred_ai(SHORTCODE) \ @@ -1007,22 +1075,22 @@ static inline void assert_vhist_tmp(DisasContext *c= tx) #define fGEN_TCG_PRED_VEC_STORE_pred_ppu(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_REG(RxV), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ fPM_M(RxV, MuV)) #define fGEN_TCG_PRED_VEC_STORE_npred_ppu(ALIGN) \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - VsV_off, ALIGN, \ + VsV, ALIGN, \ fPM_M(RxV, MuV)) #define fGEN_TCG_PRED_VEC_STORE_new_pred_ppu \ fGEN_TCG_PRED_VEC_STORE(fLSBOLD(PvV), \ fEA_REG(RxV), \ - OsN_off, true, \ + OsN, true, \ fPM_M(RxV, MuV)) #define fGEN_TCG_PRED_VEC_STORE_new_npred_ppu \ fGEN_TCG_PRED_VEC_STORE(fLSBOLDNOT(PvV), \ fEA_REG(RxV), \ - OsN_off, true, \ + OsN, true, \ fPM_M(RxV, MuV)) =20 #define fGEN_TCG_V6_vS32b_pred_ppu(SHORTCODE) \ diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index f498398367c..238ee089cba 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -59,6 +59,14 @@ TCGv gen_get_half(TCGv result, int N, TCGv src, bool sig= n); void gen_set_half(int N, TCGv result, TCGv src); void gen_set_half_i64(int N, TCGv_i64 result, TCGv src); void probe_noshuf_load(TCGv va, int s, int mi); +void gen_gvec_sabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); +void gen_gvec_uabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); void gen_gvec_sabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); void gen_gvec_uabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index b36f833b1de..df695d0731c 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -286,26 +286,28 @@ fV_AL_CHECK(EA, fVECSIZE() - 1); \ } while (0) #ifdef QEMU_GENERATE -#define fLOADMMV(EA, DST) gen_vreg_load(ctx, DST##_off, EA, true) +#define fLOADMMV(EA, DST) gen_vreg_load(ctx, DST##_base, DST##_off, EA, tr= ue) #endif #ifdef QEMU_GENERATE -#define fLOADMMVU(EA, DST) gen_vreg_load(ctx, DST##_off, EA, false) +#define fLOADMMVU(EA, DST) gen_vreg_load(ctx, DST##_base, DST##_off, EA, f= alse) #endif #ifdef QEMU_GENERATE #define fSTOREMMV(EA, SRC) \ - gen_vreg_store(ctx, EA, SRC##_off, insn->slot, true) + gen_vreg_store(ctx, EA, SRC##_base, SRC##_off, insn->slot, true) #endif #ifdef QEMU_GENERATE #define fSTOREMMVQ(EA, SRC, MASK) \ - gen_vreg_masked_store(ctx, EA, SRC##_off, MASK##_off, insn->slot, fals= e) + gen_vreg_masked_store(ctx, EA, SRC##_base, SRC##_off, \ + MASK##_base, MASK##_off, insn->slot, false) #endif #ifdef QEMU_GENERATE #define fSTOREMMVNQ(EA, SRC, MASK) \ - gen_vreg_masked_store(ctx, EA, SRC##_off, MASK##_off, insn->slot, true) + gen_vreg_masked_store(ctx, EA, SRC##_base, SRC##_off, \ + MASK##_base, MASK##_off, insn->slot, true) #endif #ifdef QEMU_GENERATE #define fSTOREMMVU(EA, SRC) \ - gen_vreg_store(ctx, EA, SRC##_off, insn->slot, false) + gen_vreg_store(ctx, EA, SRC##_base, SRC##_off, insn->slot, false) #endif #define fVFOREACH(WIDTH, VAR) for (VAR =3D 0; VAR < fVELEM(WIDTH); VAR++) #define fVARRAY_ELEMENT_ACCESS(ARRAY, TYPE, INDEX) \ diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index b87a2b20e2f..a65be7b2e04 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -91,6 +91,7 @@ typedef struct DisasContext { bool pcycle_enabled; bool hvx_coproc_enabled; bool hvx_check_emitted; + TCGv_ptr hvx_base; uint32_t num_cycles; } DisasContext; =20 @@ -192,9 +193,9 @@ static inline void ctx_log_reg_read_pair(DisasContext *= ctx, int rnum) } =20 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, - int num, bool alloc_ok); + int num, bool alloc_ok, TCGv_ptr *base); intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, - int num, bool alloc_ok); + int num, bool alloc_ok, TCGv_ptr *base); =20 static inline void ctx_start_hvx_insn(DisasContext *ctx) { diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 257836be227..dd8ae8c5541 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -56,8 +56,10 @@ static void gen_sabsdiff_vec(unsigned vece, TCGv_vec d, = TCGv_vec a, TCGv_vec b) tcg_gen_sub_vec(vece, d, d, t); } =20 -void gen_gvec_sabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void gen_gvec_sabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_sub_vec, INDEX_op_smin_vec, INDEX_op_smax_vec, 0 @@ -75,7 +77,15 @@ void gen_gvec_sabsdiff(unsigned vece, uint32_t dofs, uin= t32_t aofs, }; =20 tcg_debug_assert(vece =3D=3D MO_16 || vece =3D=3D MO_32); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &ops[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &ops[vece]); +} + +void gen_gvec_sabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + gen_gvec_sabsdiff_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bof= s, + oprsz, maxsz); } =20 static void gen_uabsdiff_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_v= ec b) @@ -87,8 +97,10 @@ static void gen_uabsdiff_vec(unsigned vece, TCGv_vec d, = TCGv_vec a, TCGv_vec b) tcg_gen_sub_vec(vece, d, d, t); } =20 -void gen_gvec_uabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +void gen_gvec_uabsdiff_var(unsigned vece, TCGv_ptr dbase, uint32_t dofs, + TCGv_ptr abase, uint32_t aofs, + TCGv_ptr bbase, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz) { static const TCGOpcode vecop_list[] =3D { INDEX_op_sub_vec, INDEX_op_umin_vec, INDEX_op_umax_vec, 0 @@ -105,7 +117,15 @@ void gen_gvec_uabsdiff(unsigned vece, uint32_t dofs, u= int32_t aofs, }; =20 tcg_debug_assert(vece =3D=3D MO_8 || vece =3D=3D MO_16); - tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &ops[vece]); + tcg_gen_gvec_3_var(dbase, dofs, abase, aofs, bbase, bofs, + oprsz, maxsz, &ops[vece]); +} + +void gen_gvec_uabsdiff(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + gen_gvec_uabsdiff_var(vece, tcg_env, dofs, tcg_env, aofs, tcg_env, bof= s, + oprsz, maxsz); } =20 TCGv gen_read_reg(TCGv result, int num) @@ -1431,54 +1451,56 @@ static void gen_asr_r_svw_trun(DisasContext *ctx, T= CGv RdV, gen_set_label(done); } =20 -static intptr_t vreg_src_off(DisasContext *ctx, int num) +static intptr_t vreg_src_off(DisasContext *ctx, int num, TCGv_ptr *base) { - intptr_t offset =3D offsetof(CPUHexagonState, hvx_ctx.VRegs[num]); + intptr_t offset =3D offsetof(HexagonHVXContext, VRegs[num]); =20 + *base =3D ctx->hvx_base; if (test_bit(num, ctx->vregs_select)) { - offset =3D ctx_future_vreg_off(ctx, num, 1, false); + offset =3D ctx_future_vreg_off(ctx, num, 1, false, base); } if (test_bit(num, ctx->vregs_updated_tmp)) { - offset =3D ctx_tmp_vreg_off(ctx, num, 1, false); + offset =3D ctx_tmp_vreg_off(ctx, num, 1, false, base); } return offset; } =20 -static void gen_vreg_write(DisasContext *ctx, intptr_t srcoff, int num, - VRegWriteType type) +static void gen_vreg_write(DisasContext *ctx, TCGv_ptr srcbase, + intptr_t srcoff, int num, VRegWriteType type) { + TCGv_ptr dstbase; intptr_t dstoff; =20 if (type !=3D EXT_TMP) { - dstoff =3D ctx_future_vreg_off(ctx, num, 1, true); - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, - sizeof(MMVector), sizeof(MMVector)); + dstoff =3D ctx_future_vreg_off(ctx, num, 1, true, &dstbase); } else { - dstoff =3D ctx_tmp_vreg_off(ctx, num, 1, false); - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, - sizeof(MMVector), sizeof(MMVector)); + dstoff =3D ctx_tmp_vreg_off(ctx, num, 1, false, &dstbase); } + tcg_gen_gvec_mov_var(MO_64, dstbase, dstoff, srcbase, srcoff, + sizeof(MMVector), sizeof(MMVector)); } =20 -static void gen_vreg_write_pair(DisasContext *ctx, intptr_t srcoff, int nu= m, - VRegWriteType type) +static void gen_vreg_write_pair(DisasContext *ctx, TCGv_ptr srcbase, + intptr_t srcoff, int num, VRegWriteType ty= pe) { - gen_vreg_write(ctx, srcoff, num ^ 0, type); + gen_vreg_write(ctx, srcbase, srcoff, num ^ 0, type); srcoff +=3D sizeof(MMVector); - gen_vreg_write(ctx, srcoff, num ^ 1, type); + gen_vreg_write(ctx, srcbase, srcoff, num ^ 1, type); } =20 -static intptr_t get_result_qreg(DisasContext *ctx, int qnum) +static intptr_t get_result_qreg(DisasContext *ctx, int qnum, TCGv_ptr *bas= e) { if (ctx->need_commit) { + *base =3D tcg_env; return offsetof(CPUHexagonState, future_QRegs[qnum]); } else { - return offsetof(CPUHexagonState, hvx_ctx.QRegs[qnum]); + *base =3D ctx->hvx_base; + return offsetof(HexagonHVXContext, QRegs[qnum]); } } =20 -static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src, - bool aligned) +static void gen_vreg_load(DisasContext *ctx, TCGv_ptr dstbase, + intptr_t dstoff, TCGv src, bool aligned) { TCGv_i64 tmp =3D tcg_temp_new_i64(); if (aligned) { @@ -1487,12 +1509,12 @@ static void gen_vreg_load(DisasContext *ctx, intptr= _t dstoff, TCGv src, for (int i =3D 0; i < sizeof(MMVector) / 8; i++) { tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_LE | MO_UQ); tcg_gen_addi_tl(src, src, 8); - tcg_gen_st_i64(tmp, tcg_env, dstoff + i * 8); + tcg_gen_st_i64(tmp, dstbase, dstoff + i * 8); } } =20 -static void gen_vreg_store(DisasContext *ctx, TCGv EA, intptr_t srcoff, - int slot, bool aligned) +static void gen_vreg_store(DisasContext *ctx, TCGv EA, TCGv_ptr srcbase, + intptr_t srcoff, int slot, bool aligned) { intptr_t dstoff =3D offsetof(CPUHexagonState, vstore[slot].data); intptr_t maskoff =3D offsetof(CPUHexagonState, vstore[slot].mask); @@ -1513,13 +1535,16 @@ static void gen_vreg_store(DisasContext *ctx, TCGv = EA, intptr_t srcoff, tcg_gen_movi_tl(hex_vstore_size[slot], sizeof(MMVector)); =20 /* Copy the data to the vstore buffer */ - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMVector), sizeof(MMVec= tor)); + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, srcbase, srcoff, + sizeof(MMVector), sizeof(MMVector)); /* Set the mask to all 1's */ tcg_gen_gvec_dup_imm(MO_64, maskoff, sizeof(MMQReg), sizeof(MMQReg), ~= 0LL); } =20 -static void gen_vreg_masked_store(DisasContext *ctx, TCGv EA, intptr_t src= off, - intptr_t bitsoff, int slot, bool invert) +static void gen_vreg_masked_store(DisasContext *ctx, TCGv EA, + TCGv_ptr srcbase, intptr_t srcoff, + TCGv_ptr bitsbase, intptr_t bitsoff, + int slot, bool invert) { intptr_t dstoff =3D offsetof(CPUHexagonState, vstore[slot].data); intptr_t maskoff =3D offsetof(CPUHexagonState, vstore[slot].mask); @@ -1530,16 +1555,19 @@ static void gen_vreg_masked_store(DisasContext *ctx= , TCGv EA, intptr_t srcoff, tcg_gen_movi_tl(hex_vstore_size[slot], sizeof(MMVector)); =20 /* Copy the data to the vstore buffer */ - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, sizeof(MMVector), sizeof(MMVec= tor)); + tcg_gen_gvec_mov_var(MO_64, tcg_env, dstoff, srcbase, srcoff, + sizeof(MMVector), sizeof(MMVector)); /* Copy the mask */ - tcg_gen_gvec_mov(MO_64, maskoff, bitsoff, sizeof(MMQReg), sizeof(MMQRe= g)); + tcg_gen_gvec_mov_var(MO_64, tcg_env, maskoff, bitsbase, bitsoff, + sizeof(MMQReg), sizeof(MMQReg)); if (invert) { tcg_gen_gvec_not(MO_64, maskoff, maskoff, sizeof(MMQReg), sizeof(MMQReg)); } } =20 -static void vec_to_qvec(size_t size, intptr_t dstoff, intptr_t srcoff) +static void vec_to_qvec(size_t size, TCGv_ptr dstbase, intptr_t dstoff, + TCGv_ptr srcbase, intptr_t srcoff) { TCGv_i64 tmp =3D tcg_temp_new_i64(); TCGv_i64 word =3D tcg_temp_new_i64(); @@ -1549,7 +1577,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff,= intptr_t srcoff) TCGv_i64 ones =3D tcg_constant_i64(~0); =20 for (int i =3D 0; i < sizeof(MMVector) / 8; i++) { - tcg_gen_ld_i64(tmp, tcg_env, srcoff + i * 8); + tcg_gen_ld_i64(tmp, srcbase, srcoff + i * 8); tcg_gen_movi_i64(mask, 0); =20 for (int j =3D 0; j < 8; j +=3D size) { @@ -1558,7 +1586,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff,= intptr_t srcoff) tcg_gen_deposit_i64(mask, mask, bits, j, size); } =20 - tcg_gen_st8_i64(mask, tcg_env, dstoff + i); + tcg_gen_st8_i64(mask, dstbase, dstoff + i); } } =20 diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index b05ac91846a..b9ebe4c3e77 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -82,14 +82,18 @@ static const char * const hexagon_prednames[] =3D { }; =20 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, - int num, bool alloc_ok) + int num, bool alloc_ok, TCGv_ptr *base) { intptr_t offset; =20 if (!ctx->need_commit) { - return offsetof(CPUHexagonState, hvx_ctx.VRegs[regnum]); + /* Short circuit: the write goes straight to the register file. */ + *base =3D ctx->hvx_base; + return offsetof(HexagonHVXContext, VRegs[regnum]); } =20 + *base =3D tcg_env; + /* See if it is already allocated */ for (int i =3D 0; i < ctx->future_vregs_idx; i++) { if (ctx->future_vregs_num[i] =3D=3D regnum) { @@ -108,10 +112,12 @@ intptr_t ctx_future_vreg_off(DisasContext *ctx, int r= egnum, } =20 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, - int num, bool alloc_ok) + int num, bool alloc_ok, TCGv_ptr *base) { intptr_t offset; =20 + *base =3D tcg_env; + /* See if it is already allocated */ for (int i =3D 0; i < ctx->tmp_vregs_idx; i++) { if (ctx->tmp_vregs_num[i] =3D=3D regnum) { @@ -691,30 +697,39 @@ static void gen_start_packet(DisasContext *ctx) } } =20 + ctx->hvx_base =3D NULL; + if (ctx->pkt.pkt_has_hvx) { + ctx->hvx_base =3D tcg_temp_new_ptr(); + tcg_gen_ld_ptr(ctx->hvx_base, tcg_env, + offsetof(CPUHexagonState, hvx)); + } + /* Preload the predicated HVX registers into future_VRegs and tmp_VReg= s */ if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) { i =3D find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); while (i < NUM_VREGS) { + TCGv_ptr VdV_base; const intptr_t VdV_off =3D - ctx_future_vreg_off(ctx, i, 1, true); - intptr_t src_off =3D offsetof(CPUHexagonState, hvx_ctx.VRegs[i= ]); - tcg_gen_gvec_mov(MO_64, VdV_off, - src_off, - sizeof(MMVector), - sizeof(MMVector)); + ctx_future_vreg_off(ctx, i, 1, true, &VdV_base); + intptr_t src_off =3D offsetof(HexagonHVXContext, VRegs[i]); + tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, + ctx->hvx_base, src_off, + sizeof(MMVector), + sizeof(MMVector)); i =3D find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i= + 1); } } if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) { i =3D find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); while (i < NUM_VREGS) { + TCGv_ptr VdV_base; const intptr_t VdV_off =3D - ctx_tmp_vreg_off(ctx, i, 1, true); - intptr_t src_off =3D offsetof(CPUHexagonState, hvx_ctx.VRegs[i= ]); - tcg_gen_gvec_mov(MO_64, VdV_off, - src_off, - sizeof(MMVector), - sizeof(MMVector)); + ctx_tmp_vreg_off(ctx, i, 1, true, &VdV_base); + intptr_t src_off =3D offsetof(HexagonHVXContext, VRegs[i]); + tcg_gen_gvec_mov_var(MO_64, VdV_base, VdV_off, + ctx->hvx_base, src_off, + sizeof(MMVector), + sizeof(MMVector)); i =3D find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + = 1); } } @@ -1017,11 +1032,13 @@ static void gen_commit_hvx(DisasContext *ctx) */ for (i =3D 0; i < ctx->vreg_log_idx; i++) { int rnum =3D ctx->vreg_log[i]; - intptr_t dstoff =3D offsetof(CPUHexagonState, hvx_ctx.VRegs[rnum]); - intptr_t srcoff =3D ctx_future_vreg_off(ctx, rnum, 1, false); + intptr_t dstoff =3D offsetof(HexagonHVXContext, VRegs[rnum]); + TCGv_ptr srcbase; + intptr_t srcoff =3D ctx_future_vreg_off(ctx, rnum, 1, false, &srcb= ase); size_t size =3D sizeof(MMVector); =20 - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); + tcg_gen_gvec_mov_var(MO_64, ctx->hvx_base, dstoff, srcbase, srcoff, + size, size); } =20 /* @@ -1032,11 +1049,12 @@ static void gen_commit_hvx(DisasContext *ctx) */ for (i =3D 0; i < ctx->qreg_log_idx; i++) { int rnum =3D ctx->qreg_log[i]; - intptr_t dstoff =3D offsetof(CPUHexagonState, hvx_ctx.QRegs[rnum]); + intptr_t dstoff =3D offsetof(HexagonHVXContext, QRegs[rnum]); intptr_t srcoff =3D offsetof(CPUHexagonState, future_QRegs[rnum]); size_t size =3D sizeof(MMQReg); =20 - tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); + tcg_gen_gvec_mov_var(MO_64, ctx->hvx_base, dstoff, tcg_env, srcoff, + size, size); } =20 if (pkt_has_hvx_store(&ctx->pkt)) { diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index ea3163132d9..2f5aa415ddf 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -434,6 +434,14 @@ def is_hvx_reg(self): return True def hvx_off(self): return f"{self.reg_tcg()}_off" + def hvx_base(self): + return f"{self.reg_tcg()}_base" + def decl_tcg_ptr(self, f): + ptr =3D self.reg_tcg() + f.write(code_fmt(f"""\ + TCGv_ptr {ptr} =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr({ptr}, {self.hvx_base()}, {self.hvx_off()}); + """)) def helper_proto_type(self): return "ptr" def helper_arg_type(self): @@ -778,18 +786,17 @@ class VRegDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; const intptr_t {self.hvx_off()} =3D - {vreg_offset_func(tag)}(ctx, {self.reg_num}, 1, true); + {vreg_offset_func(tag)}(ctx, {self.reg_num}, 1, + true, &{self.hvx_base()}); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_zero(self, f): f.write(code_fmt(f"""\ - tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, - sizeof(MMVector), sizeof(MMVector), 0); + tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, + {self.hvx_off()}, sizeof(MMVector), sizeof(MMVector), = 0); """)) def gen_write(self, f, tag): pass @@ -809,13 +816,12 @@ class VRegSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ - const intptr_t {self.hvx_off()} =3D vreg_src_off(ctx, {self.re= g_num}); + TCGv_ptr {self.hvx_base()}; + const intptr_t {self.hvx_off()} =3D + vreg_src_off(ctx, {self.reg_num}, &{self.hvx_base()}); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()})= */ @@ -830,8 +836,10 @@ def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) if skip_qemu_helper(tag): f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; const intptr_t {self.hvx_off()} =3D - ctx_future_vreg_off(ctx, {self.reg_num}, 1, true); + ctx_future_vreg_off(ctx, {self.reg_num}, 1, + true, &{self.hvx_base()}); """)) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ @@ -846,21 +854,24 @@ class VRegReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; + TCGv_ptr {self.reg_tcg()}_srcbase; const intptr_t {self.hvx_off()} =3D - {vreg_offset_func(tag)}(ctx, {self.reg_num}, 1, true); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - vreg_src_off(ctx, {self.reg_num}), - sizeof(MMVector), sizeof(MMVector)); + {vreg_offset_func(tag)}(ctx, {self.reg_num}, 1, + true, &{self.hvx_base()}); + const intptr_t {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num}, &{self.reg_tcg()}_srcbas= e); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, {self.hvx_off()= }, + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_zero(self, f): f.write(code_fmt(f"""\ - tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, - sizeof(MMVector), sizeof(MMVector), 0); + tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, + {self.hvx_off()}, sizeof(MMVector), sizeof(MMVector), = 0); """)) def gen_write(self, f, tag): pass @@ -884,15 +895,21 @@ class VRegTmp(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()} =3D tcg_env; const intptr_t {self.hvx_off()} =3D offsetof(CPUHexagonState, = vtmp); """)) if not skip_qemu_helper(tag): + self.decl_tcg_ptr(f) f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - vreg_src_off(ctx, {self.reg_num}), - sizeof(MMVector), sizeof(MMVector)); + TCGv_ptr {self.reg_tcg()}_srcbase; + const intptr_t {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num}, + &{self.reg_tcg()}_srcbase); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, + {self.hvx_off()}, + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); """)) def gen_zero(self, f): f.write(code_fmt(f"""\ @@ -901,8 +918,8 @@ def gen_zero(self, f): """)) def gen_write(self, f, tag): f.write(code_fmt(f"""\ - gen_vreg_write(ctx, {self.hvx_off()}, {self.reg_num}, - {hvx_newv(tag)}); + gen_vreg_write(ctx, {self.hvx_base()}, {self.hvx_off()}, + {self.reg_num}, {hvx_newv(tag)}); """)) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ @@ -924,17 +941,16 @@ class VRegPairDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; const intptr_t {self.hvx_off()} =3D - {vreg_offset_func(tag)}(ctx, {self.reg_num}, 2, true); + {vreg_offset_func(tag)}(ctx, {self.reg_num}, 2, + true, &{self.hvx_base()}); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_zero(self, f): f.write(code_fmt(f"""\ - tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, + tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_o= ff()}, sizeof(MMVectorPair), sizeof(MMVectorPair), 0); """)) def gen_write(self, f, tag): @@ -955,20 +971,27 @@ class VRegPairSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()} =3D tcg_env; + TCGv_ptr {self.reg_tcg()}_srcbase; const intptr_t {self.hvx_off()} =3D offsetof(CPUHexagonState, {self.reg_tcg()}); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - vreg_src_off(ctx, {self.reg_num}), - sizeof(MMVector), sizeof(MMVector)); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()} + sizeof(MMVector), - vreg_src_off(ctx, {self.reg_num} ^ 1), - sizeof(MMVector), sizeof(MMVector)); + intptr_t {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num}, &{self.reg_tcg()}_srcbas= e); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, {self.hvx_off()= }, + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); + {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num} ^ 1, + &{self.reg_tcg()}_srcbase); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, + {self.hvx_off()} + sizeof(MMVector), + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name= ()}) */ @@ -982,29 +1005,36 @@ class VRegPairReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()} =3D tcg_env; + TCGv_ptr {self.reg_tcg()}_srcbase; const intptr_t {self.hvx_off()} =3D offsetof(CPUHexagonState, {self.reg_tcg()}); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - vreg_src_off(ctx, {self.reg_num}), - sizeof(MMVector), sizeof(MMVector)); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()} + sizeof(MMVector), - vreg_src_off(ctx, {self.reg_num} ^ 1), - sizeof(MMVector), sizeof(MMVector)); + intptr_t {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num}, &{self.reg_tcg()}_srcbas= e); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, {self.hvx_off()= }, + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); + {self.reg_tcg()}_srcoff =3D + vreg_src_off(ctx, {self.reg_num} ^ 1, + &{self.reg_tcg()}_srcbase); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, + {self.hvx_off()} + sizeof(MMVector), + {self.reg_tcg()}_srcbase, + {self.reg_tcg()}_srcoff, + sizeof(MMVector), sizeof(MMVector)); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_zero(self, f): f.write(code_fmt(f"""\ - tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()}, + tcg_gen_gvec_dup_imm_var(MO_64, {self.hvx_base()}, {self.hvx_o= ff()}, sizeof(MMVectorPair), sizeof(MMVectorPair), 0); """)) def gen_write(self, f, tag): f.write(code_fmt(f"""\ - gen_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num}, - {hvx_newv(tag)}); + gen_vreg_write_pair(ctx, {self.hvx_base()}, {self.hvx_off()}, + {self.reg_num}, {hvx_newv(tag)}); """)) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ @@ -1026,14 +1056,12 @@ class QRegDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; const intptr_t {self.hvx_off()} =3D - get_result_qreg(ctx, {self.reg_num}); + get_result_qreg(ctx, {self.reg_num}, &{self.hvx_base()}); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def gen_write(self, f, tag): pass def helper_hvx_desc(self, f): @@ -1049,14 +1077,12 @@ class QRegSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()} =3D ctx->hvx_base; const intptr_t {self.hvx_off()} =3D - offsetof(CPUHexagonState, hvx_ctx.QRegs[{self.reg_num}]); + offsetof(HexagonHVXContext, QRegs[{self.reg_num}]); """)) if not skip_qemu_helper(tag): - f.write(code_fmt(f"""\ - TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); - """)) + self.decl_tcg_ptr(f) def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */ @@ -1070,18 +1096,17 @@ class QRegReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ + TCGv_ptr {self.hvx_base()}; const intptr_t {self.hvx_off()} =3D - get_result_qreg(ctx, {self.reg_num}); - tcg_gen_gvec_mov(MO_64, {self.hvx_off()}, - offsetof(CPUHexagonState, - hvx_ctx.QRegs[{self.reg_num}]), - sizeof(MMQReg), sizeof(MMQReg)); + get_result_qreg(ctx, {self.reg_num}, &{self.hvx_base()}); + tcg_gen_gvec_mov_var(MO_64, {self.hvx_base()}, {self.hvx_off()= }, + ctx->hvx_base, + offsetof(HexagonHVXContext, + QRegs[{self.reg_num}]), + sizeof(MMQReg), sizeof(MMQReg)); """)) if not skip_qemu_helper(tag): - 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789054431064158500 Each DSP ordinarily has fewer HVX contexts than hw threads. The thread's SSR:XA selects the one it's bound to. Add a hexagon-hvx-context device holding the register file. The machine creates as many as the config table specifies, linked to every vCPU. The CPU picks among the links at run time. The linux-user side keeps one context per CPU, w/o need for a device. SSR:XA is not consulted yet, the CPU always uses context 0. Signed-off-by: Brian Cain --- include/hw/hexagon/hexagon.h | 1 + include/hw/hexagon/hexagon_hvx_context.h | 27 ++++++++ target/hexagon/cpu.h | 9 ++- hw/hexagon/hex-subsys.c | 36 ++++++++++ hw/hexagon/hexagon_hvx_context.c | 83 ++++++++++++++++++++++++ linux-user/hexagon/cpu_loop.c | 2 +- linux-user/main.c | 3 + target/hexagon/cpu.c | 19 +++++- hw/hexagon/meson.build | 1 + 9 files changed, 175 insertions(+), 6 deletions(-) create mode 100644 include/hw/hexagon/hexagon_hvx_context.h create mode 100644 hw/hexagon/hexagon_hvx_context.c diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 3d7b3cb12dc..0ee6fd8d033 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -162,6 +162,7 @@ struct HexagonCommonMachineState { DeviceState *qtimer; DeviceState *glob_regs; DeviceState *tlb; + unsigned num_hvx_ctx; }; =20 #endif diff --git a/include/hw/hexagon/hexagon_hvx_context.h b/include/hw/hexagon/= hexagon_hvx_context.h new file mode 100644 index 00000000000..ab85816a7ff --- /dev/null +++ b/include/hw/hexagon/hexagon_hvx_context.h @@ -0,0 +1,27 @@ +/* + * Hexagon HVX Extension Context QOM Object + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEXAGON_HVX_CONTEXT_H +#define HEXAGON_HVX_CONTEXT_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" +#include "target/hexagon/cpu.h" + +#define TYPE_HEXAGON_HVX_CONTEXT "hexagon-hvx-context" +OBJECT_DECLARE_SIMPLE_TYPE(HexagonHVXContextState, HEXAGON_HVX_CONTEXT) + +struct HexagonHVXContextState { + SysBusDevice parent_obj; + + /* Physical context number, as SSR:XA maps to it. */ + uint32_t index; + + HexagonHVXContext regs; +}; + +#endif /* HEXAGON_HVX_CONTEXT_H */ diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index c983a9791e1..867390e84d2 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -29,6 +29,7 @@ =20 typedef struct HexagonTLBState HexagonTLBState; typedef struct HexagonGlobalRegState HexagonGlobalRegState; +typedef struct HexagonHVXContextState HexagonHVXContextState; =20 #include "cpu-qom.h" #include "exec/cpu-common.h" @@ -49,6 +50,7 @@ typedef struct HexagonGlobalRegState HexagonGlobalRegStat= e; #define REG_WRITES_MAX 32 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ #define VSTORES_MAX 2 +#define HVX_CONTEXTS_MAX 8 #define MAX_TLB_ENTRIES 1024 #define THREADS_MAX 8 =20 @@ -165,7 +167,6 @@ typedef struct CPUArchState { uint64_t llsc_val_i64; =20 HexagonHVXContext *hvx; - HexagonHVXContext hvx_ctx QEMU_ALIGNED(16); =20 MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); @@ -201,7 +202,11 @@ struct ArchCPU { =20 CPUHexagonState env; HexagonCPUConfig cfg; -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + HexagonHVXContext hvx_ctx QEMU_ALIGNED(16); +#else + HexagonHVXContextState *hvx_ctx[HVX_CONTEXTS_MAX]; + HexagonHVXContext hvx_fallback QEMU_ALIGNED(16); HexagonTLBState *tlb; uint32_t boot_addr; HexagonGlobalRegState *globalregs; diff --git a/hw/hexagon/hex-subsys.c b/hw/hexagon/hex-subsys.c index 4e3a418340e..0efcb40d8a3 100644 --- a/hw/hexagon/hex-subsys.c +++ b/hw/hexagon/hex-subsys.c @@ -7,8 +7,10 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "hw/hexagon/hex-subsys.h" #include "hw/hexagon/hexagon_globalreg.h" +#include "hw/hexagon/hexagon_hvx_context.h" #include "hw/hexagon/hexagon_tlb.h" #include "hw/intc/hex-l2vic.h" #include "hw/timer/qct-qtimer.h" @@ -98,6 +100,33 @@ static DeviceState *tlb_create(HexagonCommonMachineStat= e *hms, return tlb; } =20 +/* + * Create the core's HVX extension contexts. There are fewer of them than + * there are hardware threads, and SSR:XA picks which one a thread uses, so + * they belong to the subsystem rather than to any one CPU. + */ +static void hvx_contexts_create(HexagonCommonMachineState *hms, + const struct hexagon_machine_config *m_cfg) +{ + unsigned n =3D m_cfg->cfgtable.ext_contexts; + unsigned i; + + if (n > HVX_CONTEXTS_MAX) { + error_report("machine declares %u HVX contexts, only %u are usable= ", + n, HVX_CONTEXTS_MAX); + exit(1); + } + for (i =3D 0; i < n; i++) { + DeviceState *ctx =3D qdev_new(TYPE_HEXAGON_HVX_CONTEXT); + g_autofree char *name =3D g_strdup_printf("hvx-context[%u]", i); + + object_property_add_child(OBJECT(hms), name, OBJECT(ctx)); + qdev_prop_set_uint32(ctx, "index", i); + sysbus_realize_and_unref(SYS_BUS_DEVICE(ctx), &error_fatal); + } + hms->num_hvx_ctx =3D n; +} + static DeviceState *cluster_create(HexagonCommonMachineState *hms) { DeviceState *cluster =3D qdev_new(TYPE_CPU_CLUSTER); @@ -140,6 +169,7 @@ void hex_subsys_create(HexagonCommonMachineState *hms, hms->qtimer =3D qtimer_create(hms, m_cfg); hms->glob_regs =3D globalreg_create(hms, m_cfg, rev); hms->tlb =3D tlb_create(hms, m_cfg); + hvx_contexts_create(hms, m_cfg); } =20 void hex_subsys_add_cpu(HexagonCommonMachineState *hms, DeviceState *cpu) @@ -151,6 +181,12 @@ void hex_subsys_add_cpu(HexagonCommonMachineState *hms= , DeviceState *cpu) &error_fatal); object_property_set_link(OBJECT(cpu), "l2vic", OBJECT(hms->l2vic), &error_fatal); + for (unsigned i =3D 0; i < hms->num_hvx_ctx; i++) { + g_autofree char *name =3D g_strdup_printf("hvx-context[%u]", i); + Object *ctx =3D object_resolve_path_component(OBJECT(hms), name); + + object_property_set_link(OBJECT(cpu), name, ctx, &error_fatal); + } } =20 void hex_subsys_realize_cluster(HexagonCommonMachineState *hms) diff --git a/hw/hexagon/hexagon_hvx_context.c b/hw/hexagon/hexagon_hvx_cont= ext.c new file mode 100644 index 00000000000..d17aee0f1d0 --- /dev/null +++ b/hw/hexagon/hexagon_hvx_context.c @@ -0,0 +1,83 @@ +/* + * Hexagon HVX Extension Context QOM Object + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/hexagon/hexagon_hvx_context.h" +#include "hw/core/qdev-properties.h" +#include "migration/vmstate.h" + +static void hexagon_hvx_context_reset_hold(Object *obj, ResetType type) +{ + HexagonHVXContextState *s =3D HEXAGON_HVX_CONTEXT(obj); + + memset(&s->regs, 0, sizeof(s->regs)); +} + +/* gvec needs VRegs/QRegs 16-aligned within the struct. */ +QEMU_BUILD_BUG_ON(offsetof(HexagonHVXContextState, regs) % 16 !=3D 0); + +static const VMStateDescription vmstate_mmvector =3D { + .name =3D "hexagon_mmvector", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]){ + VMSTATE_UINT64_ARRAY(ud, MMVector, MAX_VEC_SIZE_BYTES / 8), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_mmqreg =3D { + .name =3D "hexagon_mmqreg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]){ + VMSTATE_UINT64_ARRAY(ud, MMQReg, MAX_VEC_SIZE_BYTES / 8 / 8), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_hexagon_hvx_context =3D { + .name =3D "hexagon_hvx_context", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]){ + VMSTATE_STRUCT_ARRAY(regs.VRegs, HexagonHVXContextState, NUM_VREGS, + 1, vmstate_mmvector, MMVector), + VMSTATE_STRUCT_ARRAY(regs.QRegs, HexagonHVXContextState, NUM_QREGS, + 1, vmstate_mmqreg, MMQReg), + VMSTATE_END_OF_LIST() + } +}; + +static const Property hexagon_hvx_context_properties[] =3D { + DEFINE_PROP_UINT32("index", HexagonHVXContextState, index, 0), +}; + +static void hexagon_hvx_context_class_init(ObjectClass *klass, const void = *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.hold =3D hexagon_hvx_context_reset_hold; + dc->vmsd =3D &vmstate_hexagon_hvx_context; + dc->user_creatable =3D false; + device_class_set_props(dc, hexagon_hvx_context_properties); +} + +static const TypeInfo hexagon_hvx_context_info =3D { + .name =3D TYPE_HEXAGON_HVX_CONTEXT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(HexagonHVXContextState), + .class_init =3D hexagon_hvx_context_class_init, +}; + +static void hexagon_hvx_context_register_types(void) +{ + type_register_static(&hexagon_hvx_context_info); +} + +type_init(hexagon_hvx_context_register_types) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index ccfb1da86f5..c8fa6080a4e 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -33,7 +33,7 @@ void cpu_loop(CPUHexagonState *env) target_ulong syscallnum; target_ulong ret; =20 - env->hvx =3D &env->hvx_ctx; + env->hvx =3D &HEXAGON_CPU(cs)->hvx_ctx; =20 for (;;) { cpu_exec_start(cs); diff --git a/linux-user/main.c b/linux-user/main.c index 60a695b7ca3..918b4930b07 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -244,6 +244,9 @@ CPUArchState *cpu_copy(CPUArchState *env) =20 new_cpu->tcg_cflags =3D cpu->tcg_cflags; memcpy(new_env, env, sizeof(CPUArchState)); +#if defined(TARGET_HEXAGON) + HEXAGON_CPU(new_cpu)->hvx_ctx =3D HEXAGON_CPU(cpu)->hvx_ctx; +#endif #if defined(TARGET_I386) || defined(TARGET_X86_64) new_env->gdt.base =3D target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENT= RIES, PROT_READ | PROT_WRITE, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 68c50cbcb45..a62191cf3fb 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -43,6 +43,7 @@ #include "exec/page-protection.h" #include "exec/target_page.h" #include "hw/hexagon/hexagon_globalreg.h" +#include "hw/hexagon/hexagon_hvx_context.h" #endif =20 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) @@ -412,15 +413,17 @@ static void hexagon_cpu_reset_hold(Object *obj, Reset= Type type) CPUState *cs =3D CPU(obj); HexagonCPUClass *mcc =3D HEXAGON_CPU_GET_CLASS(obj); CPUHexagonState *env =3D cpu_env(cs); -#ifndef CONFIG_USER_ONLY HexagonCPU *cpu =3D HEXAGON_CPU(cs); -#endif =20 if (mcc->parent_phases.hold) { mcc->parent_phases.hold(obj, type); } =20 - env->hvx =3D &env->hvx_ctx; +#ifdef CONFIG_USER_ONLY + env->hvx =3D &cpu->hvx_ctx; +#else + env->hvx =3D cpu->hvx_ctx[0] ? &cpu->hvx_ctx[0]->regs : &cpu->hvx_fall= back; +#endif =20 set_default_nan_mode(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_sta= tus); @@ -547,7 +550,17 @@ static void hexagon_cpu_init(Object *obj) { #ifndef CONFIG_USER_ONLY HexagonCPU *cpu =3D HEXAGON_CPU(obj); + int i; + qdev_init_gpio_in(DEVICE(cpu), hexagon_cpu_set_irq, 8); + + for (i =3D 0; i < HVX_CONTEXTS_MAX; i++) { + object_property_add_link(obj, "hvx-context[*]", + TYPE_HEXAGON_HVX_CONTEXT, + (Object **)&cpu->hvx_ctx[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } #endif } =20 diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build index 720a5d54dcc..c4b257dfa28 100644 --- a/hw/hexagon/meson.build +++ b/hw/hexagon/meson.build @@ -1,6 +1,7 @@ hexagon_ss =3D ss.source_set() hexagon_ss.add(files('hexagon_tlb.c')) hexagon_ss.add(files('hexagon_globalreg.c')) +hexagon_ss.add(files('hexagon_hvx_context.c')) hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hex-subsys.c')) hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c')) hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c')) --=20 2.34.1 From nobody Sat Sep 26 20:50:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1789054440530158500 Assign env->hvx to the right context when SSR:XA changes. Signed-off-by: Brian Cain --- target/hexagon/cpu_helper.h | 1 + target/hexagon/cpu.c | 5 +++ target/hexagon/cpu_helper.c | 72 +++++++++++++++++++++++++++++++++++++ target/hexagon/machine.c | 12 +++++++ 4 files changed, 90 insertions(+) diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index 12512efd74f..afb4df59f80 100644 --- a/target/hexagon/cpu_helper.h +++ b/target/hexagon/cpu_helper.h @@ -15,6 +15,7 @@ void hexagon_peek_memory_range(CPUHexagonState *env, uint= 32_t start_addr, uint32_t length, uintptr_t retaddr); uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index); void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old); +unsigned hexagon_hvx_select_context(CPUHexagonState *env, uint32_t ssr); int get_cpu_mode(const CPUHexagonState *env); int get_exe_mode(const CPUHexagonState *env); void clear_wait_mode(CPUHexagonState *env); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index a62191cf3fb..472e7535d4f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -320,6 +320,9 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState = *cs) CPUHexagonState *env =3D cpu_env(cs); vaddr pc =3D env->gpr[HEX_REG_PC]; uint32_t hex_flags =3D 0; +#ifndef CONFIG_USER_ONLY + HexagonCPU *cpu; +#endif =20 if (pc =3D=3D env->gpr[HEX_REG_SA0]) { hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); @@ -330,10 +333,12 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUStat= e *cs) } =20 #ifndef CONFIG_USER_ONLY + cpu =3D env_archcpu(env); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, cpu_mmu_index(env_cpu(env), false)); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, HVX_COPROC_ENABLED, + cpu->hvx_ctx[0] && GET_SSR_FIELD(SSR_XE, env->t_sreg[HEX_SREG_SSR]= )); #else hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, MMU_USER_IDX); diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 9ce260d7448..1b06b41da5d 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -11,6 +11,7 @@ #include "hw/core/boards.h" #include "hw/hexagon/hexagon.h" #include "hw/hexagon/hexagon_globalreg.h" +#include "hw/hexagon/hexagon_hvx_context.h" #include "hex_interrupts.h" #include "hex_mmu.h" #include "system/runstate.h" @@ -246,6 +247,65 @@ void hexagon_resume_threads(CPUHexagonState *current_e= nv, uint32_t mask) } } =20 +static unsigned hexagon_hvx_context_count(HexagonCPU *cpu) +{ + unsigned n; + + for (n =3D 0; n < HVX_CONTEXTS_MAX; n++) { + if (!cpu->hvx_ctx[n]) { + break; + } + } + return n; +} + +static unsigned hexagon_hvx_context_index(HexagonCPU *cpu, uint8_t xa) +{ + unsigned n =3D hexagon_hvx_context_count(cpu); + + if (n =3D=3D 0) { + return 0; + } + return xa % n; +} + +/* + * Diagnostic only. Called separately from hexagon_hvx_select_context() + * so migration post_load, where other CPUs' env->hvx may still be stale, + * doesn't trip a false positive. + */ +static void hexagon_hvx_check_overcommit(CPUHexagonState *env, unsigned id= x) +{ + CPUState *cs; + unsigned users =3D 0; + + CPU_FOREACH(cs) { + CPUHexagonState *other =3D cpu_env(cs); + + if (other->hvx =3D=3D env->hvx && + GET_SSR_FIELD(SSR_XE, other->t_sreg[HEX_SREG_SSR])) { + users++; + } + } + + if (users > 1) { + qemu_log_mask(LOG_GUEST_ERROR, + "HVX context %u is enabled for %u hardware threads " + "at once, which is undefined\n", idx, users); + } +} + +unsigned hexagon_hvx_select_context(CPUHexagonState *env, uint32_t ssr) +{ + HexagonCPU *cpu =3D env_archcpu(env); + unsigned idx =3D hexagon_hvx_context_index(cpu, GET_SSR_FIELD(SSR_XA, = ssr)); + + if (cpu->hvx_ctx[0]) { + env->hvx =3D &cpu->hvx_ctx[idx]->regs; + } + return idx; +} + void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old) { bool old_EX, old_UM, old_GM, old_IE; @@ -269,6 +329,18 @@ void hexagon_modify_ssr(CPUHexagonState *env, uint32_t= new, uint32_t old) hex_mmu_mode_change(env); } =20 + bool xa_changed =3D GET_SSR_FIELD(SSR_XA, new) !=3D GET_SSR_FIELD(SSR_= XA, old); + bool xe_changed =3D GET_SSR_FIELD(SSR_XE, new) !=3D GET_SSR_FIELD(SSR_= XE, old); + + if (xa_changed || xe_changed) { + unsigned idx =3D xa_changed + ? hexagon_hvx_select_context(env, new) + : hexagon_hvx_context_index(env_archcpu(env), + GET_SSR_FIELD(SSR_XA, new)); + + hexagon_hvx_check_overcommit(env, idx); + } + old_asid =3D GET_SSR_FIELD(SSR_ASID, old); new_asid =3D GET_SSR_FIELD(SSR_ASID, new); if (new_asid !=3D old_asid) { diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c index bf4646f4a8b..179b6f53a2a 100644 --- a/target/hexagon/machine.c +++ b/target/hexagon/machine.c @@ -7,11 +7,23 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" #include "cpu.h" +#include "cpu_helper.h" + +static int hexagon_cpu_post_load(void *opaque, int version_id) +{ + HexagonCPU *cpu =3D opaque; + CPUHexagonState *env =3D &cpu->env; + + hexagon_hvx_select_context(env, env->t_sreg[HEX_SREG_SSR]); + + return 0; +} =20 const VMStateDescription vmstate_hexagon_cpu =3D { .name =3D "cpu", .version_id =3D 2, .minimum_version_id =3D 2, + .post_load =3D hexagon_cpu_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(env.gpr, HexagonCPU, TOTAL_PER_THREAD_REGS), VMSTATE_UINT32_ARRAY(env.pred, HexagonCPU, NUM_PREGS), --=20 2.34.1 From nobody Sat Sep 26 20:50:53 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1789054575; cv=none; d=zohomail.com; s=zohoarc; b=lfOR+HgI4j+27ycLPu2hyHpmlzGDfevXvwHcoYDzSNyAbtOBLq+gc+ZPaiZq4p5w9umqmMhojunePXGFmpmbR3WAFm8ygaIxFKAdNf8Gadja2LupXZuZgqxStrG+riVEmOktNvL70KuUI/j8YH9CR0ft1tl4V7tU8K7bEGlvYYo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1789054575; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tZMgSw0+Q91bACgsnDdC8hHrp5qT6Ry60fg8WAP88z8=; b=G5WbbriZKHpjfWISmIOXoNKGx1pTsWhNUSpbngbF1xyD5kmNTOFU0DOX6KCTT0XxmXuqKNPD8j21O9A5COJGOiXYk6ddwNONENl+PJA3KUPmsaC2V5cZLUpQvA+CnxgHWIyBem1m4bPRvAi6czBEKkt5YL5V4rxrBOwNHeCZd2Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1789054575844785.7369391457112; Thu, 10 Sep 2026 08:36:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x4goV-0003vQ-Vf; Thu, 10 Sep 2026 11:35:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4gll-0002KX-3E for qemu-devel@nongnu.org; Thu, 10 Sep 2026 11:32:59 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x4glj-0005QG-KG for qemu-devel@nongnu.org; Thu, 10 Sep 2026 11:32:56 -0400 Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68AF4XoV107121 for ; Thu, 10 Sep 2026 15:32:54 GMT Received: from mail-ot1-f72.google.com (mail-ot1-f72.google.com [209.85.210.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4gksh8srxf-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 10 Sep 2026 15:32:54 +0000 (GMT) Received: by mail-ot1-f72.google.com with SMTP id 46e09a7af769-7e9e2db9914so1350273a34.1 for ; Thu, 10 Sep 2026 08:32:54 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. 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Signed-off-by: Brian Cain Reviewed-by: Marco Liebel --- tests/functional/hexagon/test_arch_tests.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/functional/hexagon/test_arch_tests.py b/tests/functional= /hexagon/test_arch_tests.py index 5d7ce487436..f73c1f42bf0 100755 --- a/tests/functional/hexagon/test_arch_tests.py +++ b/tests/functional/hexagon/test_arch_tests.py @@ -98,6 +98,13 @@ def test_user_mode(self) -> None: """ self.run_uart_test("test_user_mode") =20 + def test_hvx_context(self) -> None: + """Tests the HVX coprocessor context: SSR XA context selection + and isolation, vsplat/store, and the NO_COPROC_ENABLE exception + raised when SSR:XE is clear. + """ + self.run_uart_test("test_hvx_context") + =20 if __name__ =3D=3D "__main__": QemuSystemTest.main() --=20 2.34.1