[PATCH v8 0/7] riscv: add initial sdext support

Daniel Henrique Barboza posted 7 patches 2 weeks, 5 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260907114615.1609913-1-daniel.barboza@oss.qualcomm.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu@processmission.com>
There is a newer version of this series
include/exec/translation-block.h              |   4 +-
target/riscv/cpu.c                            |   7 +
target/riscv/cpu.h                            |   9 ++
target/riscv/cpu_bits.h                       |  33 +++++
target/riscv/cpu_cfg_fields.h.inc             |   1 +
target/riscv/helper.h                         |   3 +
target/riscv/insn32.decode                    |   1 +
target/riscv/machine.c                        |  20 +++
target/riscv/tcg/cpu_helper.c                 |  91 +++++++++++++
target/riscv/tcg/csr.c                        | 126 ++++++++++++++++++
target/riscv/tcg/debug.c                      |  59 +++++++-
.../tcg/insn_trans/trans_privileged.c.inc     |  24 ++++
target/riscv/tcg/op_helper.c                  |  70 ++++++++++
target/riscv/tcg/tcg-cpu.c                    |  19 +++
target/riscv/tcg/translate.c                  |  15 ++-
tests/tcg/riscv64/Makefile.softmmu-target     |   5 +
tests/tcg/riscv64/test-sdext-sigill.S         |  83 ++++++++++++
17 files changed, 564 insertions(+), 6 deletions(-)
create mode 100644 tests/tcg/riscv64/test-sdext-sigill.S
[PATCH v8 0/7] riscv: add initial sdext support
Posted by Daniel Henrique Barboza 2 weeks, 5 days ago
Greetings,

This version is a simple rebase with master, where a trivial conflict
with tests/tcg/riscv64/Makefile.softmmu-target was solved, and with my
S-o-Bs on patches 1-6. 

No other changes made.  Patches based on master.

Changes from v7:
- Added my S-o-B in patches 1-6
- Patch 7:
  - fixed conflict with Makefile.softmmu-target
- v7 link: https://lore.kernel.org/qemu-devel/20260831141007.353854-1-daniel.barboza@oss.qualcomm.com/

Chao Liu (6):
  target/riscv: add sdext debug CSRs state
  target/riscv: add sdext Debug Mode helpers
  target/riscv: add dret instruction
  target/riscv: add sdext enter Debug Mode on ebreak
  target/riscv: add sdext single-step support
  target/riscv: add sdtrig trigger action=debug mode

Daniel Henrique Barboza (1):
  tests/tcg/riscv64: add sdext "not on Debug mode" sigill tests

 include/exec/translation-block.h              |   4 +-
 target/riscv/cpu.c                            |   7 +
 target/riscv/cpu.h                            |   9 ++
 target/riscv/cpu_bits.h                       |  33 +++++
 target/riscv/cpu_cfg_fields.h.inc             |   1 +
 target/riscv/helper.h                         |   3 +
 target/riscv/insn32.decode                    |   1 +
 target/riscv/machine.c                        |  20 +++
 target/riscv/tcg/cpu_helper.c                 |  91 +++++++++++++
 target/riscv/tcg/csr.c                        | 126 ++++++++++++++++++
 target/riscv/tcg/debug.c                      |  59 +++++++-
 .../tcg/insn_trans/trans_privileged.c.inc     |  24 ++++
 target/riscv/tcg/op_helper.c                  |  70 ++++++++++
 target/riscv/tcg/tcg-cpu.c                    |  19 +++
 target/riscv/tcg/translate.c                  |  15 ++-
 tests/tcg/riscv64/Makefile.softmmu-target     |   5 +
 tests/tcg/riscv64/test-sdext-sigill.S         |  83 ++++++++++++
 17 files changed, 564 insertions(+), 6 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-sdext-sigill.S

-- 
2.43.0
Re: [PATCH v8 0/7] riscv: add initial sdext support
Posted by Daniel Henrique Barboza 2 weeks, 3 days ago
Hello!

It seems like after the tcg/tests meson infrastructure work we shouldn't
add TCG tests the way we were doing before.

With this series as is, on top of a recent master:

$ make -C build -j 16 check-tcg
(...)
$ grep 'sdext'  /local/mnt/workspace/qemu/build/meson-logs/testlog.txt
$

If I change to the new meson infrastructure:

$ make -C build -j 16 check-tcg
(...)
$ grep  'sdext'  /local/mnt/workspace/qemu/build/meson-logs/testlog.txt
test:         tcg+tcg-riscv64-softmmu - qemu:riscv64-softmmu-test-sdext-sigill
command:      MESON_TEST_ITERATION=1 ASAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1 MSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stacktrace=1 MALLOC_PERTURB_=171 RUST_BACKTRACE=1 UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stacktrace=1 /usr/bin/env QEMU=/local/mnt/workspace/qemu/build/qemu-system-riscv64 /local/mnt/workspace/qemu/build/qemu-system-riscv64 -cpu rv64,sdtrig=true,sdext=true -M virt -display none -serial stdio 
-semihosting -bios tests/tcg/riscv64-softmmu-test-sdext-sigill.test


We want to run the test with 'check-tcg' (and seems like it also runs with
'check' too) so I'll re-send the patches with the relevant test changes.

Cheers,
Daniel


On 9/7/2026 8:46 AM, Daniel Henrique Barboza wrote:
> Greetings,
> 
> This version is a simple rebase with master, where a trivial conflict
> with tests/tcg/riscv64/Makefile.softmmu-target was solved, and with my
> S-o-Bs on patches 1-6.
> 
> No other changes made.  Patches based on master.
> 
> Changes from v7:
> - Added my S-o-B in patches 1-6
> - Patch 7:
>    - fixed conflict with Makefile.softmmu-target
> - v7 link: https://lore.kernel.org/qemu-devel/20260831141007.353854-1-daniel.barboza@oss.qualcomm.com/
> 
> Chao Liu (6):
>    target/riscv: add sdext debug CSRs state
>    target/riscv: add sdext Debug Mode helpers
>    target/riscv: add dret instruction
>    target/riscv: add sdext enter Debug Mode on ebreak
>    target/riscv: add sdext single-step support
>    target/riscv: add sdtrig trigger action=debug mode
> 
> Daniel Henrique Barboza (1):
>    tests/tcg/riscv64: add sdext "not on Debug mode" sigill tests
> 
>   include/exec/translation-block.h              |   4 +-
>   target/riscv/cpu.c                            |   7 +
>   target/riscv/cpu.h                            |   9 ++
>   target/riscv/cpu_bits.h                       |  33 +++++
>   target/riscv/cpu_cfg_fields.h.inc             |   1 +
>   target/riscv/helper.h                         |   3 +
>   target/riscv/insn32.decode                    |   1 +
>   target/riscv/machine.c                        |  20 +++
>   target/riscv/tcg/cpu_helper.c                 |  91 +++++++++++++
>   target/riscv/tcg/csr.c                        | 126 ++++++++++++++++++
>   target/riscv/tcg/debug.c                      |  59 +++++++-
>   .../tcg/insn_trans/trans_privileged.c.inc     |  24 ++++
>   target/riscv/tcg/op_helper.c                  |  70 ++++++++++
>   target/riscv/tcg/tcg-cpu.c                    |  19 +++
>   target/riscv/tcg/translate.c                  |  15 ++-
>   tests/tcg/riscv64/Makefile.softmmu-target     |   5 +
>   tests/tcg/riscv64/test-sdext-sigill.S         |  83 ++++++++++++
>   17 files changed, 564 insertions(+), 6 deletions(-)
>   create mode 100644 tests/tcg/riscv64/test-sdext-sigill.S
>