[v9] riscv: add initial sdext support

[PATCH v9 0/7] riscv: add initial sdext support

Daniel Henrique Barboza posted 7 patches 2 weeks, 3 days ago

Diff against v1 v2 v3 v4 v5 v6 v7 v8
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git fetch https://github.com/patchew-project/qemu tags/patchew/20260909144841.1766921-1-daniel.barboza@oss.qualcomm.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Chao Liu <chao.liu@processmission.com>

include/exec/translation-block.h              |   4 +-
target/riscv/cpu.c                            |   7 +
target/riscv/cpu.h                            |   9 ++
target/riscv/cpu_bits.h                       |  33 +++++
target/riscv/cpu_cfg_fields.h.inc             |   1 +
target/riscv/helper.h                         |   3 +
target/riscv/insn32.decode                    |   1 +
target/riscv/machine.c                        |  20 +++
target/riscv/tcg/cpu_helper.c                 |  91 +++++++++++++
target/riscv/tcg/csr.c                        | 126 ++++++++++++++++++
target/riscv/tcg/debug.c                      |  59 +++++++-
.../tcg/insn_trans/trans_privileged.c.inc     |  24 ++++
target/riscv/tcg/op_helper.c                  |  70 ++++++++++
target/riscv/tcg/tcg-cpu.c                    |  19 +++
target/riscv/tcg/translate.c                  |  15 ++-
tests/tcg/riscv64/system/meson.build          |   8 ++
tests/tcg/riscv64/test-sdext-sigill.S         |  83 ++++++++++++
17 files changed, 567 insertions(+), 6 deletions(-)
create mode 100644 tests/tcg/riscv64/test-sdext-sigill.S

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[PATCH v9 0/7] riscv: add initial sdext support

Posted by Daniel Henrique Barboza 2 weeks, 3 days ago

Hi there!

In this new version I changed patch 7 to use the new meson tcg tests
framework.

No other changes made.  Patches based on master.

Changes from v8:
- patch 7:
  - use the new meson infrastructure for test-sdext-sigill.S
- v8 link: https://lore.kernel.org/qemu-devel/20260907114615.1609913-1-daniel.barboza@oss.qualcomm.com/

Chao Liu (6):
  target/riscv: add sdext debug CSRs state
  target/riscv: add sdext Debug Mode helpers
  target/riscv: add dret instruction
  target/riscv: add sdext enter Debug Mode on ebreak
  target/riscv: add sdext single-step support
  target/riscv: add sdtrig trigger action=debug mode

Daniel Henrique Barboza (1):
  tests/tcg/riscv64: add sdext "not on Debug mode" sigill tests

 include/exec/translation-block.h              |   4 +-
 target/riscv/cpu.c                            |   7 +
 target/riscv/cpu.h                            |   9 ++
 target/riscv/cpu_bits.h                       |  33 +++++
 target/riscv/cpu_cfg_fields.h.inc             |   1 +
 target/riscv/helper.h                         |   3 +
 target/riscv/insn32.decode                    |   1 +
 target/riscv/machine.c                        |  20 +++
 target/riscv/tcg/cpu_helper.c                 |  91 +++++++++++++
 target/riscv/tcg/csr.c                        | 126 ++++++++++++++++++
 target/riscv/tcg/debug.c                      |  59 +++++++-
 .../tcg/insn_trans/trans_privileged.c.inc     |  24 ++++
 target/riscv/tcg/op_helper.c                  |  70 ++++++++++
 target/riscv/tcg/tcg-cpu.c                    |  19 +++
 target/riscv/tcg/translate.c                  |  15 ++-
 tests/tcg/riscv64/system/meson.build          |   8 ++
 tests/tcg/riscv64/test-sdext-sigill.S         |  83 ++++++++++++
 17 files changed, 567 insertions(+), 6 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-sdext-sigill.S

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2.43.0