[v2] hw/riscv: Socify Atlantis

[PATCH v2 00/16] hw/riscv: Socify Atlantis

Posted by Joel Stanley 3 weeks, 5 days ago

v1: https://lore.kernel.org/qemu-riscv/20260826220528.54516-1-joel@jms.id.au/

Changes in v2:

 - Reword patch 14 "hart private memory" commit message to clarify hart
   vs hart array
 - Fix indentation in patch 4 (riscv_aplic MemoryRegion)

Thanks to Daniel and Philippe for the reviews.

Original commit message:

This addresses the review given by Cedric on v1 of the Atlantis patches,
where he suggested making the machine a SoC. This is the pattern
followed by the Aspeed ARM machines, where the SoC represents the
modelled hardware, attaching its devices to a memory container, with the
SoC instantiated by a QEMU machine that provides the memory container
and the machine's RAM.

Aside from the clean abstraction that this encourages, this pattern will
be useful in adding other SoCs to the Atlantis machine, such as the RCPU
(boot microcontroller) and CPL (Cluster Power Logic microcontroller).

The series converts the RISC-V interrupt controllers to take a
MemoryRegion for mapping themselves, with no change in behaviour for
existing machines, and then cleans up the CPS device to place its
devices in the memory container provided.

The next few patches clean up the Atlantis machine to make extracting
the SoC device and mapping it in a container relatively straightforward.

Joel Stanley (15):
  hw/riscv/aia: Take a MemoryRegion for the created devices
  hw/intc/riscv_aclint: Take a MemoryRegion for the created devices
  hw/intc/riscv_imsic: Take a MemoryRegion for the created device
  hw/intc/riscv_aplic: Take a MemoryRegion for the created device
  hw/intc/sifive_plic: Take a MemoryRegion for the created device
  hw/riscv/cps: Map interrupt controllers in SoC container
  hw/riscv/atlantis: Make UART unimp region a SoC device
  hw/riscv/atlantis: Remove unused fdt_size
  hw/riscv/atlantis: Rename hart array 'soc' to 'cpus'
  hw/riscv/atlantis: Rework device tree creation
  hw/riscv/atlantis: Use local reference for system memory
  hw/riscv/atlantis: Decouple RAM size from MachineState
  hw/riscv/atlantis: Make TTAtlantisState own memory containers
  hw/riscv/atlantis: Extract an Atlantis SoC device
  hw/riscv/atlantis: Map the SoC through a memory container

Portia Stephens (1):
  hw/riscv: Add property to hart to allow private memory

 hw/riscv/aia.h                 |   2 +-
 include/hw/intc/riscv_aclint.h |   7 +-
 include/hw/intc/riscv_aplic.h  |   2 +-
 include/hw/intc/riscv_imsic.h  |   3 +-
 include/hw/intc/sifive_plic.h  |   3 +-
 include/hw/riscv/riscv_hart.h  |   2 +
 include/hw/riscv/tt_atlantis.h |  32 +++-
 hw/intc/riscv_aclint.c         |  12 +-
 hw/intc/riscv_aplic.c          |   5 +-
 hw/intc/riscv_imsic.c          |   6 +-
 hw/intc/sifive_plic.c          |   6 +-
 hw/riscv/aia.c                 |  14 +-
 hw/riscv/cps.c                 |  12 +-
 hw/riscv/k230.c                |   9 +-
 hw/riscv/microchip_pfsoc.c     |   8 +-
 hw/riscv/riscv_hart.c          |   8 +
 hw/riscv/shakti_c.c            |  10 +-
 hw/riscv/sifive_e.c            |   6 +-
 hw/riscv/sifive_u.c            |  10 +-
 hw/riscv/spike.c               |   4 +-
 hw/riscv/tt_atlantis.c         | 277 +++++++++++++++++++++------------
 hw/riscv/virt.c                |  21 ++-
 hw/riscv/xiangshan_kmh.c       |  17 +-
 23 files changed, 317 insertions(+), 159 deletions(-)

-- 
2.47.3

Re: [PATCH v2 00/16] hw/riscv: Socify Atlantis

Posted by Alistair Francis 3 weeks, 2 days ago

On Mon, 2026-08-31 at 11:44 +0930, Joel Stanley wrote:
> v1:
> https://lore.kernel.org/qemu-riscv/20260826220528.54516-1-joel@jms.id.au/
> 
> Changes in v2:
> 
>  - Reword patch 14 "hart private memory" commit message to clarify
> hart
>    vs hart array
>  - Fix indentation in patch 4 (riscv_aplic MemoryRegion)
> 
> Thanks to Daniel and Philippe for the reviews.
> 
> Original commit message:
> 
> This addresses the review given by Cedric on v1 of the Atlantis
> patches,
> where he suggested making the machine a SoC. This is the pattern
> followed by the Aspeed ARM machines, where the SoC represents the
> modelled hardware, attaching its devices to a memory container, with
> the
> SoC instantiated by a QEMU machine that provides the memory container
> and the machine's RAM.
> 
> Aside from the clean abstraction that this encourages, this pattern
> will
> be useful in adding other SoCs to the Atlantis machine, such as the
> RCPU
> (boot microcontroller) and CPL (Cluster Power Logic microcontroller).
> 
> The series converts the RISC-V interrupt controllers to take a
> MemoryRegion for mapping themselves, with no change in behaviour for
> existing machines, and then cleans up the CPS device to place its
> devices in the memory container provided.
> 
> The next few patches clean up the Atlantis machine to make extracting
> the SoC device and mapping it in a container relatively
> straightforward.
> 
> Joel Stanley (15):
>   hw/riscv/aia: Take a MemoryRegion for the created devices
>   hw/intc/riscv_aclint: Take a MemoryRegion for the created devices
>   hw/intc/riscv_imsic: Take a MemoryRegion for the created device
>   hw/intc/riscv_aplic: Take a MemoryRegion for the created device
>   hw/intc/sifive_plic: Take a MemoryRegion for the created device
>   hw/riscv/cps: Map interrupt controllers in SoC container
>   hw/riscv/atlantis: Make UART unimp region a SoC device
>   hw/riscv/atlantis: Remove unused fdt_size
>   hw/riscv/atlantis: Rename hart array 'soc' to 'cpus'
>   hw/riscv/atlantis: Rework device tree creation
>   hw/riscv/atlantis: Use local reference for system memory
>   hw/riscv/atlantis: Decouple RAM size from MachineState
>   hw/riscv/atlantis: Make TTAtlantisState own memory containers
>   hw/riscv/atlantis: Extract an Atlantis SoC device
>   hw/riscv/atlantis: Map the SoC through a memory container

Thanks!

Partially applied to riscv-to-apply.next.

I applied the first few patches, after that I hit merge conflicts with
the recent FDT changes. Should be pretty easy to fix, but I pulled in
the first patches to keep the ball moving.

Alistair

> 
> Portia Stephens (1):
>   hw/riscv: Add property to hart to allow private memory
> 
>  hw/riscv/aia.h                 |   2 +-
>  include/hw/intc/riscv_aclint.h |   7 +-
>  include/hw/intc/riscv_aplic.h  |   2 +-
>  include/hw/intc/riscv_imsic.h  |   3 +-
>  include/hw/intc/sifive_plic.h  |   3 +-
>  include/hw/riscv/riscv_hart.h  |   2 +
>  include/hw/riscv/tt_atlantis.h |  32 +++-
>  hw/intc/riscv_aclint.c         |  12 +-
>  hw/intc/riscv_aplic.c          |   5 +-
>  hw/intc/riscv_imsic.c          |   6 +-
>  hw/intc/sifive_plic.c          |   6 +-
>  hw/riscv/aia.c                 |  14 +-
>  hw/riscv/cps.c                 |  12 +-
>  hw/riscv/k230.c                |   9 +-
>  hw/riscv/microchip_pfsoc.c     |   8 +-
>  hw/riscv/riscv_hart.c          |   8 +
>  hw/riscv/shakti_c.c            |  10 +-
>  hw/riscv/sifive_e.c            |   6 +-
>  hw/riscv/sifive_u.c            |  10 +-
>  hw/riscv/spike.c               |   4 +-
>  hw/riscv/tt_atlantis.c         | 277 +++++++++++++++++++++----------
> --
>  hw/riscv/virt.c                |  21 ++-
>  hw/riscv/xiangshan_kmh.c       |  17 +-
>  23 files changed, 317 insertions(+), 159 deletions(-)

Re: [PATCH v2 00/16] hw/riscv: Socify Atlantis

Posted by Joel Stanley 3 weeks, 2 days ago

On Thu, 3 Sept 2026 at 13:41, Alistair Francis <Alistair.Francis@wdc.com> wrote:
>
> On Mon, 2026-08-31 at 11:44 +0930, Joel Stanley wrote:
> > v1:
> > https://lore.kernel.org/qemu-riscv/20260826220528.54516-1-joel@jms.id.au/
> >
> > Changes in v2:
> >
> >  - Reword patch 14 "hart private memory" commit message to clarify
> > hart
> >    vs hart array
> >  - Fix indentation in patch 4 (riscv_aplic MemoryRegion)
> >
> > Thanks to Daniel and Philippe for the reviews.
> >
> > Original commit message:
> >
> > This addresses the review given by Cedric on v1 of the Atlantis
> > patches,
> > where he suggested making the machine a SoC. This is the pattern
> > followed by the Aspeed ARM machines, where the SoC represents the
> > modelled hardware, attaching its devices to a memory container, with
> > the
> > SoC instantiated by a QEMU machine that provides the memory container
> > and the machine's RAM.
> >
> > Aside from the clean abstraction that this encourages, this pattern
> > will
> > be useful in adding other SoCs to the Atlantis machine, such as the
> > RCPU
> > (boot microcontroller) and CPL (Cluster Power Logic microcontroller).
> >
> > The series converts the RISC-V interrupt controllers to take a
> > MemoryRegion for mapping themselves, with no change in behaviour for
> > existing machines, and then cleans up the CPS device to place its
> > devices in the memory container provided.
> >
> > The next few patches clean up the Atlantis machine to make extracting
> > the SoC device and mapping it in a container relatively
> > straightforward.
> >
> > Joel Stanley (15):
> >   hw/riscv/aia: Take a MemoryRegion for the created devices
> >   hw/intc/riscv_aclint: Take a MemoryRegion for the created devices
> >   hw/intc/riscv_imsic: Take a MemoryRegion for the created device
> >   hw/intc/riscv_aplic: Take a MemoryRegion for the created device
> >   hw/intc/sifive_plic: Take a MemoryRegion for the created device
> >   hw/riscv/cps: Map interrupt controllers in SoC container
> >   hw/riscv/atlantis: Make UART unimp region a SoC device
> >   hw/riscv/atlantis: Remove unused fdt_size
> >   hw/riscv/atlantis: Rename hart array 'soc' to 'cpus'
> >   hw/riscv/atlantis: Rework device tree creation
> >   hw/riscv/atlantis: Use local reference for system memory
> >   hw/riscv/atlantis: Decouple RAM size from MachineState
> >   hw/riscv/atlantis: Make TTAtlantisState own memory containers
> >   hw/riscv/atlantis: Extract an Atlantis SoC device
> >   hw/riscv/atlantis: Map the SoC through a memory container
>
> Thanks!
>
> Partially applied to riscv-to-apply.next.
>
> I applied the first few patches, after that I hit merge conflicts with
> the recent FDT changes. Should be pretty easy to fix, but I pulled in
> the first patches to keep the ball moving.

No worries. I didn't see any of the patches when I pulled, so I sent
the full series as a v3 rebased on the device tree patches you'd
merged and pushed.

Cheers,

Joel