From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142637687284.50540638988707; Sun, 30 Aug 2026 19:17:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rYj-0003Lu-7Q; Sun, 30 Aug 2026 22:15:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rYh-0003Lc-HJ for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:15:39 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rYf-0007WP-QV for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:15:39 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-cc11a905ba5so2056497a12.2 for ; Sun, 30 Aug 2026 19:15:37 -0700 (PDT) Received: from donnager-debian.. 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Both callers pass system_memory, so there is no change in behaviour. As the controllers don't yet take a MemoryRegion the parameter is not yet passed on. Changing riscv_create_aia first avoids churn in the intermediate commits. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/aia.h | 2 +- hw/riscv/aia.c | 2 +- hw/riscv/tt_atlantis.c | 3 ++- hw/riscv/virt.c | 3 ++- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/riscv/aia.h b/hw/riscv/aia.h index 3b6d7f962506..82ab601bf188 100644 --- a/hw/riscv/aia.h +++ b/hw/riscv/aia.h @@ -13,7 +13,7 @@ =20 uint32_t imsic_num_bits(uint32_t count); =20 -DeviceState *riscv_create_aia(bool msimode, int aia_guests, +DeviceState *riscv_create_aia(MemoryRegion *mr, bool msimode, int aia_gues= ts, uint32_t m_imsic_stride, uint32_t s_imsic_stride, uint16_t num_sources, diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index c1a5982856c5..651552c8f970 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -24,7 +24,7 @@ uint32_t imsic_num_bits(uint32_t count) return ret; } =20 -DeviceState *riscv_create_aia(bool msimode, int aia_guests, +DeviceState *riscv_create_aia(MemoryRegion *mr, bool msimode, int aia_gues= ts, uint32_t m_imsic_stride, uint32_t s_imsic_stride, uint16_t num_sources, diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index babce2b680f2..d69851df0a01 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -496,7 +496,8 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); =20 - s->irqchip =3D riscv_create_aia(true, TT_IMSIC_GUESTS, + s->irqchip =3D riscv_create_aia(system_memory, + true, TT_IMSIC_GUESTS, TT_IMSIC_STRIDE, TT_IMSIC_STRIDE, TT_IRQCHIP_NUM_SOURCES, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 329ccdb5a7b6..22a607ed10bf 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1411,8 +1411,9 @@ static void virt_machine_init(MachineState *machine) s->irqchip[i] =3D virt_create_plic(s->memmap, i, base_hartid, hart_count); } else { + bool msimode =3D s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC; int imsic_bits =3D imsic_num_bits(s->aia_guests + 1); - s->irqchip[i] =3D riscv_create_aia(s->aia_type =3D=3D VIRT_AIA= _TYPE_APLIC_IMSIC, + s->irqchip[i] =3D riscv_create_aia(system_memory, msimode, s->aia_guests, IMSIC_HART_SIZE(0), IMSIC_HART_SIZE(imsic_bits), --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142611371789.1941282674908; Sun, 30 Aug 2026 19:16:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rYp-0003Mv-8b; Sun, 30 Aug 2026 22:15:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rYn-0003MZ-89 for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:15:45 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rYl-0007X2-2f for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:15:44 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-38e58034d05so2378284a91.2 for ; Sun, 30 Aug 2026 19:15:42 -0700 (PDT) Received: from donnager-debian.. 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Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). All callers pass system_memory, so there is no change in behaviour. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/riscv_aclint.h | 7 ++++--- hw/intc/riscv_aclint.c | 12 ++++++++---- hw/riscv/cps.c | 6 ++++-- hw/riscv/k230.c | 6 ++++-- hw/riscv/microchip_pfsoc.c | 5 +++-- hw/riscv/shakti_c.c | 7 ++++--- hw/riscv/sifive_e.c | 4 ++-- hw/riscv/sifive_u.c | 7 ++++--- hw/riscv/spike.c | 4 ++-- hw/riscv/tt_atlantis.c | 3 ++- hw/riscv/virt.c | 17 +++++++++++------ hw/riscv/xiangshan_kmh.c | 6 ++++-- 12 files changed, 52 insertions(+), 32 deletions(-) diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h index 0e0b98acb08a..a8c5d4eb5895 100644 --- a/include/hw/intc/riscv_aclint.h +++ b/include/hw/intc/riscv_aclint.h @@ -46,7 +46,8 @@ typedef struct RISCVAclintMTimerState { qemu_irq *timer_irqs; } RISCVAclintMTimerState; =20 -DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, +DeviceState *riscv_aclint_mtimer_create(MemoryRegion *mr, + hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, bool provide_rdtime); @@ -68,8 +69,8 @@ typedef struct RISCVAclintSwiState { qemu_irq *soft_irqs; } RISCVAclintSwiState; =20 -DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base, - uint32_t num_harts, bool sswi); +DeviceState *riscv_aclint_swi_create(MemoryRegion *mr, + hwaddr addr, uint32_t hartid_base, uint32_t num_harts, bool sswi); =20 enum { RISCV_ACLINT_DEFAULT_MTIMECMP =3D 0x0, diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 361a8d1bcb45..972c6c99b044 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -371,7 +371,8 @@ static const TypeInfo riscv_aclint_mtimer_info =3D { /* * Create ACLINT MTIMER device. */ -DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, +DeviceState *riscv_aclint_mtimer_create(MemoryRegion *mr, + hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, bool provide_rdtime) @@ -392,7 +393,8 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hw= addr size, qdev_prop_set_uint32(dev, "aperture-size", size); qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(mr, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); @@ -556,7 +558,8 @@ static const TypeInfo riscv_aclint_swi_info =3D { /* * Create ACLINT [M|S]SWI device. */ -DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base, +DeviceState *riscv_aclint_swi_create(MemoryRegion *mr, + hwaddr addr, uint32_t hartid_base, uint32_t num_harts, bool sswi) { int i; @@ -569,7 +572,8 @@ DeviceState *riscv_aclint_swi_create(hwaddr addr, uint3= 2_t hartid_base, qdev_prop_set_uint32(dev, "num-harts", num_harts); qdev_prop_set_uint32(dev, "sswi", sswi ? true : false); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(mr, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c index 86172be5b3ca..5cfb54aa27d2 100644 --- a/hw/riscv/cps.c +++ b/hw/riscv/cps.c @@ -151,9 +151,11 @@ static void riscv_cps_realize(DeviceState *dev, Error = **errp) false, false, s->aplic); /* PLIC changes msi_nonbroken to ture. We revert the change. */ msi_nonbroken =3D false; - riscv_aclint_swi_create(cm_base + AIA_CLINT_OFFSET, + riscv_aclint_swi_create(get_system_memory(), + cm_base + AIA_CLINT_OFFSET, hartid_base, MAX_HARTS, false); - riscv_aclint_mtimer_create(cm_base + AIA_CLINT_OFFSET + + riscv_aclint_mtimer_create(get_system_memory(), + cm_base + AIA_CLINT_OFFSET + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, hartid_base, diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 558f30b97e9d..1ef4260c5391 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -196,9 +196,11 @@ static void k230_soc_realize(DeviceState *dev, Error *= *errp) s->c908_plic =3D k230_create_plic(C908_CPU_HARTID, c908_cpus); =20 /* CLINT */ - riscv_aclint_swi_create(memmap[K230_DEV_CLINT].base, + riscv_aclint_swi_create(sys_mem, + memmap[K230_DEV_CLINT].base, C908_CPU_HARTID, c908_cpus, false); - riscv_aclint_mtimer_create(memmap[K230_DEV_CLINT].base + 0x4000, + riscv_aclint_mtimer_create(sys_mem, + memmap[K230_DEV_CLINT].base + 0x4000, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, C908_CPU_HARTID, c908_cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 4017129c8304..a6026776d4de 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -250,9 +250,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *d= ev, Error **errp) memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); =20 /* CLINT */ - riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base, + riscv_aclint_swi_create(system_memory, + memmap[MICROCHIP_PFSOC_CLINT].base, 0, ms->smp.cpus, false); - riscv_aclint_mtimer_create( + riscv_aclint_mtimer_create(system_memory, memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 835b1f879b7f..86ff8f8fcaab 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -127,10 +127,11 @@ static void shakti_c_soc_state_realize(DeviceState *d= ev, Error **errp) SHAKTI_C_PLIC_CONTEXT_STRIDE, shakti_c_memmap[SHAKTI_C_PLIC].size); =20 - riscv_aclint_swi_create(shakti_c_memmap[SHAKTI_C_CLINT].base, + riscv_aclint_swi_create(system_memory, + shakti_c_memmap[SHAKTI_C_CLINT].base, 0, 1, false); - riscv_aclint_mtimer_create(shakti_c_memmap[SHAKTI_C_CLINT].base + - RISCV_ACLINT_SWI_SIZE, + riscv_aclint_mtimer_create(system_memory, + shakti_c_memmap[SHAKTI_C_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, 1, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 71925583bd97..0ea444f43bc5 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -225,9 +225,9 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) SIFIVE_E_PLIC_CONTEXT_BASE, SIFIVE_E_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_E_DEV_PLIC].size); - riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base, + riscv_aclint_swi_create(sys_mem, memmap[SIFIVE_E_DEV_CLINT].base, 0, ms->smp.cpus, false); - riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base + + riscv_aclint_mtimer_create(sys_mem, memmap[SIFIVE_E_DEV_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 57a57c96e16b..58b4744318f8 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -788,10 +788,11 @@ static void sifive_u_soc_realize(DeviceState *dev, Er= ror **errp) serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ= )); sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ= )); - riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, + riscv_aclint_swi_create(system_memory, + memmap[SIFIVE_U_DEV_CLINT].base, 0, ms->smp.cpus, false); - riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base + - RISCV_ACLINT_SWI_SIZE, + riscv_aclint_mtimer_create(system_memory, + memmap[SIFIVE_U_DEV_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, CLINT_TIMEBASE_FREQ, false); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 630b65f56977..a227e0eca147 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -163,10 +163,10 @@ static void spike_board_init(MachineState *machine) sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); =20 /* Core Local Interruptor (timer and IPI) for each socket */ - riscv_aclint_swi_create( + riscv_aclint_swi_create(system_memory, memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create( + riscv_aclint_mtimer_create(system_memory, memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index d69851df0a01..3f183db5c302 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -509,7 +509,8 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) TT_IRQCHIP_NUM_MSIS, TT_IRQCHIP_NUM_PRIO_BITS); =20 - riscv_aclint_mtimer_create(s->memmap[TT_ATL_ACLINT].base, + riscv_aclint_mtimer_create(system_memory, + s->memmap[TT_ATL_ACLINT].base, TT_ACLINT_MTIME_SIZE, 0, hart_count, TT_ACLINT_MTIMECMP, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 22a607ed10bf..6e4b39315aaa 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1370,7 +1370,8 @@ static void virt_machine_init(MachineState *machine) if (virt_aclint_allowed() && s->have_aclint) { if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { /* Per-socket ACLINT MTIMER */ - riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + s->memmap[VIRT_CLINT].base + i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, @@ -1379,10 +1380,12 @@ static void virt_machine_init(MachineState *machine) RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); } else { /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ - riscv_aclint_swi_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_swi_create(system_memory, + s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, @@ -1390,16 +1393,18 @@ static void virt_machine_init(MachineState *machine) RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); - riscv_aclint_swi_create(s->memmap[VIRT_ACLINT_SSWI].base + + riscv_aclint_swi_create(system_memory, + s->memmap[VIRT_ACLINT_SSWI].base + i * s->memmap[VIRT_ACLINT_SSWI].size, base_hartid, hart_count, true); } } else if (tcg_enabled()) { /* Per-socket SiFive CLINT */ - riscv_aclint_swi_create( + riscv_aclint_swi_create(system_memory, s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT]= .size, base_hartid, hart_count, false); - riscv_aclint_mtimer_create(s->memmap[VIRT_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + s->memmap[VIRT_CLINT].base + i * s->memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_co= unt, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MT= IME, diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 384624d69ad5..94f9d02a00b9 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -116,9 +116,11 @@ static void xiangshan_kmh_soc_realize(DeviceState *dev= , Error **errp) 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 /* CLINT */ - riscv_aclint_swi_create(memmap[XIANGSHAN_KMH_CLINT].base, + riscv_aclint_swi_create(system_memory, + memmap[XIANGSHAN_KMH_CLINT].base, 0, num_harts, false); - riscv_aclint_mtimer_create(memmap[XIANGSHAN_KMH_CLINT].base + + riscv_aclint_mtimer_create(system_memory, + memmap[XIANGSHAN_KMH_CLINT].base + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP, --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). All callers pass system_memory, so there is no change in behaviour. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/riscv_imsic.h | 3 ++- hw/intc/riscv_imsic.c | 6 ++++-- hw/riscv/aia.c | 6 ++++-- hw/riscv/xiangshan_kmh.c | 5 +++-- 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/include/hw/intc/riscv_imsic.h b/include/hw/intc/riscv_imsic.h index fae999731dff..8295b1f14452 100644 --- a/include/hw/intc/riscv_imsic.h +++ b/include/hw/intc/riscv_imsic.h @@ -62,7 +62,8 @@ struct RISCVIMSICState { uint32_t num_irqs; }; =20 -DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, +DeviceState *riscv_imsic_create(MemoryRegion *mr, hwaddr addr, + uint32_t hartid, bool mmode, uint32_t num_pages, uint32_t num_ids); =20 #endif diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index d6b46cdca220..26dd10a0462c 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -495,7 +495,8 @@ type_init(riscv_imsic_register_types) /* * Create IMSIC device. */ -DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, +DeviceState *riscv_imsic_create(MemoryRegion *mr, hwaddr addr, + uint32_t hartid, bool mmode, uint32_t num_pages, uint32_t num_ids) { DeviceState *dev =3D qdev_new(TYPE_RISCV_IMSIC); @@ -518,7 +519,8 @@ DeviceState *riscv_imsic_create(hwaddr addr, uint32_t h= artid, bool mmode, qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1); =20 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(mr, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 if (!kvm_irqchip_in_kernel()) { for (i =3D 0; i < num_pages; i++) { diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index 651552c8f970..49cb14349f00 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -52,7 +52,8 @@ DeviceState *riscv_create_aia(MemoryRegion *mr, bool msim= ode, int aia_guests, /* Per-socket M-level IMSICs */ addr =3D imsic_m->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_= SHIFT); for (i =3D 0; i < hart_count; i++) { - riscv_imsic_create(addr + i * m_imsic_stride, + riscv_imsic_create(mr, + addr + i * m_imsic_stride, base_hartid + i, true, 1, num_msis); } @@ -61,7 +62,8 @@ DeviceState *riscv_create_aia(MemoryRegion *mr, bool msim= ode, int aia_guests, /* Per-socket S-level IMSICs */ addr =3D imsic_s->base + socket * (1U << IMSIC_MMIO_GROUP_MIN_SHIF= T); for (i =3D 0; i < hart_count; i++) { - riscv_imsic_create(addr + i * s_imsic_stride, + riscv_imsic_create(mr, + addr + i * s_imsic_stride, base_hartid + i, false, 1 + aia_guests, num_msis); } diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 94f9d02a00b9..9eb608f8c578 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -65,14 +65,15 @@ static DeviceState *xiangshan_kmh_create_aia(uint32_t n= um_harts) /* M-level IMSICs */ addr =3D memmap[XIANGSHAN_KMH_IMSIC_M].base; for (i =3D 0; i < num_harts; i++) { - riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), i, true, + riscv_imsic_create(get_system_memory(), + addr + i * IMSIC_HART_SIZE(0), i, true, 1, XIANGSHAN_KMH_IMSIC_NUM_IDS); } =20 /* S-level IMSICs */ addr =3D memmap[XIANGSHAN_KMH_IMSIC_S].base; for (i =3D 0; i < num_harts; i++) { - riscv_imsic_create(addr + + riscv_imsic_create(get_system_memory(), addr + i * IMSIC_HART_SIZE(XIANGSHAN_KMH_IMSIC_GUEST_B= ITS), i, false, 1 + XIANGSHAN_KMH_IMSIC_GUEST_BITS, XIANGSHAN_KMH_IMSIC_NUM_IDS); --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142596564761.1534528950542; Sun, 30 Aug 2026 19:16:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rYz-0003Ps-P3; Sun, 30 Aug 2026 22:15:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rYx-0003PI-9D for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:15:55 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rYv-0007YC-I2 for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:15:55 -0400 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-cc11a905ba5so2056619a12.2 for ; Sun, 30 Aug 2026 19:15:53 -0700 (PDT) Received: from donnager-debian.. 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Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). The mapping still only happens when the APLIC is emulated. All callers pass system_memory, so there is no change in behaviour. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/riscv_aplic.h | 2 +- hw/intc/riscv_aplic.c | 5 +++-- hw/riscv/aia.c | 6 ++++-- hw/riscv/cps.c | 6 ++++-- hw/riscv/xiangshan_kmh.c | 6 ++++-- 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h index c7a4d4ad0172..baeec76e4c3e 100644 --- a/include/hw/intc/riscv_aplic.h +++ b/include/hw/intc/riscv_aplic.h @@ -80,7 +80,7 @@ bool riscv_is_kvm_aia_aplic_imsic(bool msimode); bool riscv_use_emulated_aplic(bool msimode); void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr); =20 -DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, +DeviceState *riscv_aplic_create(MemoryRegion *mr, hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent); =20 diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 84606e9f3d88..87d7d9e49cdd 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -1109,7 +1109,7 @@ void riscv_aplic_add_child(DeviceState *parent, Devic= eState *child) /* * Create APLIC device. */ -DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, +DeviceState *riscv_aplic_create(MemoryRegion *mr, hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent) { @@ -1137,7 +1137,8 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr s= ize, sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 if (riscv_use_emulated_aplic(msimode)) { - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(mr, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 if (!msimode) { for (i =3D 0; i < num_harts; i++) { diff --git a/hw/riscv/aia.c b/hw/riscv/aia.c index 49cb14349f00..974806c425e2 100644 --- a/hw/riscv/aia.c +++ b/hw/riscv/aia.c @@ -71,7 +71,8 @@ DeviceState *riscv_create_aia(MemoryRegion *mr, bool msim= ode, int aia_guests, =20 if (!kvm_enabled()) { /* Per-socket M-level APLIC */ - aplic_m_dev =3D riscv_aplic_create(aplic_m->base + + aplic_m_dev =3D riscv_aplic_create(mr, + aplic_m->base + socket * aplic_m->size, aplic_m->size, (msimode) ? 0 : base_hartid, @@ -82,7 +83,8 @@ DeviceState *riscv_create_aia(MemoryRegion *mr, bool msim= ode, int aia_guests, } =20 /* Per-socket S-level APLIC */ - aplic_s_dev =3D riscv_aplic_create(aplic_s->base + + aplic_s_dev =3D riscv_aplic_create(mr, + aplic_s->base + socket * aplic_s->size, aplic_s->size, (msimode) ? 0 : base_hartid, diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c index 5cfb54aa27d2..d2fd9638a08d 100644 --- a/hw/riscv/cps.c +++ b/hw/riscv/cps.c @@ -135,14 +135,16 @@ static void riscv_cps_realize(DeviceState *dev, Error= **errp) for (i =3D 0; i < num_of_clusters; i++) { uint64_t cm_base =3D GLOBAL_CM_BASE + (CM_SIZE * i); uint32_t hartid_base =3D i << MHARTID_CLUSTER_SHIFT; - s->aplic =3D riscv_aplic_create(cm_base + AIA_PLIC_M_OFFSET, + s->aplic =3D riscv_aplic_create(get_system_memory(), + cm_base + AIA_PLIC_M_OFFSET, AIA_PLIC_M_SIZE, hartid_base, /* hartid_base */ MAX_HARTS, /* num_harts */ APLIC_NUM_SOURCES, APLIC_NUM_PRIO_BITS, false, true, NULL); - riscv_aplic_create(cm_base + AIA_PLIC_S_OFFSET, + riscv_aplic_create(get_system_memory(), + cm_base + AIA_PLIC_S_OFFSET, AIA_PLIC_S_SIZE, hartid_base, /* hartid_base */ MAX_HARTS, /* num_harts */ diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c index 9eb608f8c578..c5a654ab417d 100644 --- a/hw/riscv/xiangshan_kmh.c +++ b/hw/riscv/xiangshan_kmh.c @@ -80,13 +80,15 @@ static DeviceState *xiangshan_kmh_create_aia(uint32_t n= um_harts) } =20 /* M-level APLIC */ - aplic_m =3D riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_M].base, + aplic_m =3D riscv_aplic_create(get_system_memory(), + memmap[XIANGSHAN_KMH_APLIC_M].base, memmap[XIANGSHAN_KMH_APLIC_M].size, 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES, 1, true, true, NULL); =20 /* S-level APLIC */ - riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_S].base, + riscv_aplic_create(get_system_memory(), + memmap[XIANGSHAN_KMH_APLIC_S].base, memmap[XIANGSHAN_KMH_APLIC_S].size, 0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES, 1, true, false, aplic_m); --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142655027815.8180802945666; Sun, 30 Aug 2026 19:17:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rZ3-0003R3-IY; Sun, 30 Aug 2026 22:16:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rZ2-0003Qe-Bs for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:00 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rZ0-0007Ym-Kx for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:00 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-398b3d66515so1396098a91.0 for ; Sun, 30 Aug 2026 19:15:58 -0700 (PDT) Received: from donnager-debian.. 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Add a MemoryRegion parameter and map the device into it instead of calling sysbus_mmio_map(). All callers pass system_memory, so there is no change in behaviour. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/intc/sifive_plic.h | 3 ++- hw/intc/sifive_plic.c | 6 ++++-- hw/riscv/k230.c | 3 ++- hw/riscv/microchip_pfsoc.c | 3 ++- hw/riscv/shakti_c.c | 3 ++- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 3 ++- hw/riscv/virt.c | 1 + 8 files changed, 16 insertions(+), 8 deletions(-) diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h index 32973dbf281e..13fe6b2909d2 100644 --- a/include/hw/intc/sifive_plic.h +++ b/include/hw/intc/sifive_plic.h @@ -76,7 +76,8 @@ struct SiFivePLICState { qemu_irq *s_external_irqs; }; =20 -DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, +DeviceState *sifive_plic_create(MemoryRegion *mr, hwaddr addr, + char *hart_config, uint32_t num_harts, uint32_t hartid_base, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 9c84ff06a9fd..b6472443276b 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -473,7 +473,8 @@ type_init(sifive_plic_register_types) /* * Create PLIC device. */ -DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, +DeviceState *sifive_plic_create(MemoryRegion *mr, hwaddr addr, + char *hart_config, uint32_t num_harts, uint32_t hartid_base, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, @@ -499,7 +500,8 @@ DeviceState *sifive_plic_create(hwaddr addr, char *hart= _config, qdev_prop_set_uint32(dev, "context-stride", context_stride); qdev_prop_set_uint32(dev, "aperture-size", aperture_size); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + memory_region_add_subregion(mr, addr, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); =20 plic =3D SIFIVE_PLIC(dev); =20 diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c index 1ef4260c5391..6b0f0453c80b 100644 --- a/hw/riscv/k230.c +++ b/hw/riscv/k230.c @@ -134,7 +134,8 @@ static DeviceState *k230_create_plic(int base_hartid, i= nt hartid_count) plic_hart_config =3D riscv_plic_hart_config_string(hartid_count); =20 /* Per-socket PLIC */ - return sifive_plic_create(memmap[K230_DEV_PLIC].base, + return sifive_plic_create(get_system_memory(), + memmap[K230_DEV_PLIC].base, plic_hart_config, hartid_count, base_hartid, K230_PLIC_NUM_SOURCES, K230_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index a6026776d4de..1f6d9f5ae1ed 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -282,7 +282,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *de= v, Error **errp) plic_hart_config =3D riscv_plic_hart_config_string(ms->smp.cpus); =20 /* PLIC */ - s->plic =3D sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, + s->plic =3D sifive_plic_create(system_memory, + memmap[MICROCHIP_PFSOC_PLIC].base, plic_hart_config, ms->smp.cpus, 0, MICROCHIP_PFSOC_PLIC_NUM_SOURCES, MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 86ff8f8fcaab..62052bf7c61e 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -115,7 +115,8 @@ static void shakti_c_soc_state_realize(DeviceState *dev= , Error **errp) =20 sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort); =20 - sss->plic =3D sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base, + sss->plic =3D sifive_plic_create(system_memory, + shakti_c_memmap[SHAKTI_C_PLIC].base, (char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0, SHAKTI_C_PLIC_NUM_SOURCES, SHAKTI_C_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 0ea444f43bc5..81d7995ddcfb 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -214,7 +214,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); =20 /* MMIO */ - s->plic =3D sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, + s->plic =3D sifive_plic_create(sys_mem, memmap[SIFIVE_E_DEV_PLIC].base, (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0, SIFIVE_E_PLIC_NUM_SOURCES, SIFIVE_E_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 58b4744318f8..1cc6be744f08 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -772,7 +772,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) plic_hart_config =3D riscv_plic_hart_config_string(ms->smp.cpus); =20 /* MMIO */ - s->plic =3D sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, + s->plic =3D sifive_plic_create(system_memory, + memmap[SIFIVE_U_DEV_PLIC].base, plic_hart_config, ms->smp.cpus, 0, SIFIVE_U_PLIC_NUM_SOURCES, SIFIVE_U_PLIC_NUM_PRIORITIES, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6e4b39315aaa..6d061a80ca9e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1138,6 +1138,7 @@ static DeviceState *virt_create_plic(const MemMapEntr= y *memmap, int socket, =20 /* Per-socket PLIC */ return sifive_plic_create( + get_system_memory(), memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, plic_hart_config, hart_count, base_hartid, VIRT_IRQCHIP_NUM_SOURCES, --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Pass the container memory region to the interrupt controller helpers so all CPS devices live in the container. The location of devices in memory for the boston-aia machine is unchanged. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/cps.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/cps.c b/hw/riscv/cps.c index d2fd9638a08d..21daaf4943d8 100644 --- a/hw/riscv/cps.c +++ b/hw/riscv/cps.c @@ -135,7 +135,7 @@ static void riscv_cps_realize(DeviceState *dev, Error *= *errp) for (i =3D 0; i < num_of_clusters; i++) { uint64_t cm_base =3D GLOBAL_CM_BASE + (CM_SIZE * i); uint32_t hartid_base =3D i << MHARTID_CLUSTER_SHIFT; - s->aplic =3D riscv_aplic_create(get_system_memory(), + s->aplic =3D riscv_aplic_create(&s->container, cm_base + AIA_PLIC_M_OFFSET, AIA_PLIC_M_SIZE, hartid_base, /* hartid_base */ @@ -143,7 +143,7 @@ static void riscv_cps_realize(DeviceState *dev, Error *= *errp) APLIC_NUM_SOURCES, APLIC_NUM_PRIO_BITS, false, true, NULL); - riscv_aplic_create(get_system_memory(), + riscv_aplic_create(&s->container, cm_base + AIA_PLIC_S_OFFSET, AIA_PLIC_S_SIZE, hartid_base, /* hartid_base */ @@ -153,10 +153,10 @@ static void riscv_cps_realize(DeviceState *dev, Error= **errp) false, false, s->aplic); /* PLIC changes msi_nonbroken to ture. We revert the change. */ msi_nonbroken =3D false; - riscv_aclint_swi_create(get_system_memory(), + riscv_aclint_swi_create(&s->container, cm_base + AIA_CLINT_OFFSET, hartid_base, MAX_HARTS, false); - riscv_aclint_mtimer_create(get_system_memory(), + riscv_aclint_mtimer_create(&s->container, cm_base + AIA_CLINT_OFFSET + RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142674233671.4043992571683; Sun, 30 Aug 2026 19:17:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rZE-0003Z0-Sc; Sun, 30 Aug 2026 22:16:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rZC-0003Xo-J9 for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:10 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rZB-0007a2-07 for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:10 -0400 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-382ef647e20so2907782a91.1 for ; Sun, 30 Aug 2026 19:16:08 -0700 (PDT) Received: from donnager-debian.. ([180.150.112.50]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-396b186807bsm20071240a91.12.2026.08.30.19.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2026 19:16:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788142567; x=1788747367; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ZgJzq+XsYOvtH3xWP7INoFWVb96qT7YPWqEHVflcXbM=; b=UfpTiroqkX04HZ3dYHkokjkeh0boLln7jQxkb6U12ZO0OOU46yv5ux5NJYFTDALR0c VWY7sSwEddtleLSDMwE/RrZWckWfTyzVKNEE2ODPiwzneWjRaXHeI11TXKTX5CnTIntY aBiWf1VgYRcuH+l6V9ji/K78SLa/a5t4IRUjHnNy6usBtLruxd1BRB3uUrwviy8sAHE7 ugcdcuxcbP+g3o7Uk+Rt8NXdZ5b+Rms3/2QWJkKlz8AzEIUbHeKP/zKBbSileeje/b/r lfzHkjDSLrlGo0hgRjVWsTzqKynMUH6KXlbJ9lEtqXf4bWmK7/HhcYrXlLhVTkwxR7tz vt2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788142567; x=1788747367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=ZgJzq+XsYOvtH3xWP7INoFWVb96qT7YPWqEHVflcXbM=; b=YlWQlqFf6MYFU6uTKBaz9G2sNDe1CxwpRbvBmhSok1wzMikxaBbK0fHCRdLaa6my/H XhVZjP9Qydb5sce6VvwRGRc+HsP2oX+v32nax0+TDAQZ54c+soyYTfHTtVP928HJAbGK TN1Av78/XZBAEgEVRhMMhqO9zLCDI+ZnakHwERzd3VhB52HIYn3LYBEeviBliW/we0cn fOndvXvMVzLJQc0XzdOnYnJZbkd1rB2tKrU54eSD+AtsjciDHUNYRbNGYM+d3UdkcfFL 4NjwESZUXTFiahzwnWSS1xxk/vzMQ+GAV9EU533A3RTgreVTqlPyN2PHzmVmJWqH43xR FJkQ== X-Forwarded-Encrypted: i=1; AKwUvBxX2HhuerZ1W84jrtLYN66JI0/H2FHImXCta/svEmjpgzZ4BHUPbQXKoHPQuDvEQVDgfMA9D5nI6RBZ@nongnu.org X-Gm-Message-State: AFuF++kOAN2VvkhEcqOTBtK6YGJyWsAQxQgWHk/sicQmIjKFiqMPZ/8S GDEySOEb5I4YMgiVj1zYBSuQUQAbtJdiCXK9Nxmtf1tvtasjl4EYc/aV X-Gm-Gg: AYBFou1iS7o5kfhjomjrdkYKiOYRBJQPB747ruH9FXrRquDdKs2v7wjxZDaOSSZ4HgT NF54D7ow+NIYp1yxTvimV8q9SrXT235mq97X0WkiOrhbBIJzkqxhf3PtwjnMS0c1d2bF35vtwIi N8RY0JoHVdKDUsqtPwT0dn/k2u+yGaMEt9KGT5LkSyhRMn7SCBlNPXfRHCGtY8wJcNxerpx7SFd 4xZ06qIJU8MDwopPnoAYJ/fa2B4F0xuN1w8n8/PzioRn+PwPdqEdDmtjVRw7xzj+Z1QuzFW8aQ/ xniO4cjT1LbEa9Jr7s8wNvw5/Y2DECZlvgwfsZQ4mZg/hxjtrK7AWkrP2yjR/rkiXqvADOcQ89/ iHuME6xA2ChYXxhEv6IwzG6/yDGgpo5FhYVzBgqZeal2Of6XVRHk6vizA0k5VeHhTpW1GN3WhMX WyYFaXbyEMhT2I8SBUQhsiqXew255tWhKUaWNVyumqvBQbtZxq5hS7pwYSTuerOEY3/4hSk/3vl Z2GheNHC4LW6iqREH+Db1ftf7jccX5zeHxxoBS2WzUDT9XmH73b5/Kzuch7ZczmpCjL/GP8FAgP 56DDX5wslDYybCJ4QtMf X-Received: by 2002:a17:90b:1e05:b0:398:9bd5:490c with SMTP id 98e67ed59e1d1-3989bd54c4emr18003924a91.19.1788142567592; Sun, 30 Aug 2026 19:16:07 -0700 (PDT) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza Cc: Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , Portia Stephens , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/16] hw/riscv/atlantis: Make UART unimp region a SoC device Date: Mon, 31 Aug 2026 11:44:48 +0930 Message-ID: <20260831021500.82565-8-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260831021500.82565-1-joel@jms.id.au> References: <20260831021500.82565-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=joel.stan@gmail.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1788142676316158500 Content-Type: text/plain; charset="utf-8" Make the unimplemented region covering the remainder of the console UART's register space a SoC child device, mapped using a helper. This makes it easier to map it into the SoC's memory container along with the other devices in the future. While here, rename the region from uart0 to uart1. The uart0 name was a leftover from an earlier revision that used a different device for the console. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/tt_atlantis.h | 2 ++ hw/riscv/tt_atlantis.c | 19 ++++++++++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 7f7d4a5a5905..c9308aa57017 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -13,6 +13,7 @@ #include "hw/core/sysbus.h" #include "hw/i2c/designware_i2c.h" #include "hw/intc/riscv_imsic.h" +#include "hw/misc/unimp.h" #include "hw/riscv/riscv_hart.h" =20 #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") @@ -31,6 +32,7 @@ struct TTAtlantisState { RISCVHartArrayState soc; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; + UnimplementedDeviceState uart1; =20 int fdt_size; }; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 3f183db5c302..acfd0d31b368 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -409,6 +409,17 @@ static void load_fdt(TTAtlantisState *s) create_fdt_memory(s); } =20 +static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, + const char *name, hwaddr addr, uint64_t= size) +{ + qdev_prop_set_string(DEVICE(dev), "name", name); + qdev_prop_set_uint64(DEVICE(dev), "size", size); + sysbus_realize(dev, &error_abort); + + memory_region_add_subregion_overlap(memory, addr, + sysbus_mmio_get_region(dev, 0), -1= 000); +} + static void tt_atlantis_machine_done(Notifier *notifier, void *data) { TTAtlantisState *s =3D container_of(notifier, TTAtlantisState, machine= _done); @@ -560,9 +571,11 @@ static void tt_atlantis_machine_init(MachineState *mac= hine) * Create an unimplemented device region so writes don't fault * and reads return zero, which keeps Linux happy. */ - create_unimplemented_device("tt-atlantis.uart0", - s->memmap[TT_ATL_UART1].base, - s->memmap[TT_ATL_UART1].size); + object_initialize_child(OBJECT(s), "uart1", &s->uart1, + TYPE_UNIMPLEMENTED_DEVICE); + mmio_map_unimplemented(system_memory, SYS_BUS_DEVICE(&s->uart1), + "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, + s->memmap[TT_ATL_UART1].size); =20 /* I2C */ for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142703404819.4623898704307; Sun, 30 Aug 2026 19:18:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rZK-0003ag-1L; Sun, 30 Aug 2026 22:16:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rZH-0003Zc-UL for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:16 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rZG-0007af-CP for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:15 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-398a5aad413so1317783a91.3 for ; Sun, 30 Aug 2026 19:16:14 -0700 (PDT) Received: from donnager-debian.. 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Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 2 -- hw/riscv/tt_atlantis.c | 6 ++++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index c9308aa57017..d0cca3b02424 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -33,8 +33,6 @@ struct TTAtlantisState { DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; - - int fdt_size; }; =20 enum { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index acfd0d31b368..127c89be4f60 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -366,9 +366,10 @@ static void finalize_fdt(TTAtlantisState *s) static void create_fdt(TTAtlantisState *s) { MachineState *ms =3D MACHINE(s); + int fdt_size =3D 0; =20 ms->fdt =3D create_board_device_tree("Tenstorrent Atlantis RISC-V Mach= ine", - "tenstorrent,atlantis", &s->fdt_siz= e); + "tenstorrent,atlantis", &fdt_size); =20 qemu_fdt_add_subnode(ms->fdt, "/chosen"); =20 @@ -384,8 +385,9 @@ static void load_fdt(TTAtlantisState *s) MachineState *ms =3D MACHINE(s); char **node_path; Error *err =3D NULL; + int fdt_size =3D 0; =20 - ms->fdt =3D load_device_tree(ms->dtb, &s->fdt_size); + ms->fdt =3D load_device_tree(ms->dtb, &fdt_size); if (!ms->fdt) { error_report("load_device_tree() failed"); exit(1); --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17881426326721017.0921327448654; Sun, 30 Aug 2026 19:17:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rZO-0003bJ-Rf; Sun, 30 Aug 2026 22:16:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rZN-0003at-9N for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:21 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rZL-0007bF-JX for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:21 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-38511175ad3so3016536a91.2 for ; Sun, 30 Aug 2026 19:16:19 -0700 (PDT) Received: from donnager-debian.. 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Use cpus instead as an accurate description of the hart array. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/tt_atlantis.h | 2 +- hw/riscv/tt_atlantis.c | 34 +++++++++++++++++----------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index d0cca3b02424..642490d21743 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -29,7 +29,7 @@ struct TTAtlantisState { Notifier machine_done; const MemMapEntry *memmap; =20 - RISCVHartArrayState soc; + RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 127c89be4f60..35b3be072a06 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -112,13 +112,13 @@ static void create_fdt_aclint(TTAtlantisState *s, uin= t32_t *intc_phandles) uint32_t aclint_cells_size; hwaddr addr; =20 - aclint_mtimer_cells =3D g_new0(uint32_t, s->soc.num_harts * 2); + aclint_mtimer_cells =3D g_new0(uint32_t, s->cpus.num_harts * 2); =20 - for (int cpu =3D 0; cpu < s->soc.num_harts; cpu++) { + for (int cpu =3D 0; cpu < s->cpus.num_harts; cpu++) { aclint_mtimer_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu= ]); aclint_mtimer_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_TIMER); } - aclint_cells_size =3D s->soc.num_harts * sizeof(uint32_t) * 2; + aclint_cells_size =3D s->cpus.num_harts * sizeof(uint32_t) * 2; =20 addr =3D s->memmap[TT_ATL_ACLINT].base; =20 @@ -210,7 +210,7 @@ static void create_fdt_pmu(TTAtlantisState *s) { char pmu_name[] =3D "/pmu"; void *fdt =3D MACHINE(s)->fdt; - RISCVCPU *hart =3D &s->soc.harts[0]; + RISCVCPU *hart =3D &s->cpus.harts[0]; =20 qemu_fdt_add_subnode(fdt, pmu_name); qemu_fdt_setprop_string(fdt, pmu_name, "compatible", "riscv,pmu"); @@ -227,8 +227,8 @@ static void create_fdt_cpu(TTAtlantisState *s, const Me= mMapEntry *memmap, =20 fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); =20 - create_fdt_socket_cpus(fdt, s->soc.harts, 0, s->soc.num_harts, - s->soc.hartid_base, &fdt_phandle, intc_phandles, + create_fdt_socket_cpus(fdt, s->cpus.harts, 0, s->cpus.num_harts, + s->cpus.hartid_base, &fdt_phandle, intc_phandle= s, false, false); =20 create_fdt_memory(s); @@ -252,13 +252,13 @@ static void create_fdt_cpu(TTAtlantisState *s, const = MemMapEntry *memmap, create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_MAPLIC], msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, - IRQ_M_EXT, s->soc.num_harts); + IRQ_M_EXT, s->cpus.num_harts); =20 /* S-level APLIC node */ create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_SAPLIC], imsic_s_phandle, intc_phandles, aplic_s_phandle, 0, - IRQ_S_EXT, s->soc.num_harts); + IRQ_S_EXT, s->cpus.num_harts); } =20 static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, @@ -429,7 +429,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) hwaddr start_addr =3D s->memmap[TT_ATL_DDR_LO].base; hwaddr mem_size; target_ulong firmware_end_addr, kernel_start_addr; - const char *firmware_name =3D riscv_default_firmware_name(&s->soc); + const char *firmware_name =3D riscv_default_firmware_name(&s->cpus); uint64_t fdt_load_addr; uint64_t kernel_entry; RISCVBootInfo boot_info; @@ -446,7 +446,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) if (mem_size > s->memmap[TT_ATL_DDR_LO].size) { mem_size =3D s->memmap[TT_ATL_DDR_LO].size; } - riscv_boot_info_init_discontig_mem(&boot_info, &s->soc, + riscv_boot_info_init_discontig_mem(&boot_info, &s->cpus, s->memmap[TT_ATL_DDR_LO].base, mem_size); =20 @@ -476,7 +476,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* load the reset vector */ - riscv_setup_rom_reset_vec(machine, &s->soc, start_addr, + riscv_setup_rom_reset_vec(machine, &s->cpus, start_addr, s->memmap[TT_ATL_BOOTROM].base, s->memmap[TT_ATL_BOOTROM].size, kernel_entry, @@ -496,18 +496,18 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) =20 s->memmap =3D tt_atlantis_memmap; =20 - object_initialize_child(OBJECT(machine), "soc", &s->soc, + object_initialize_child(OBJECT(machine), "soc", &s->cpus, TYPE_RISCV_HART_ARRAY); - object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, + object_property_set_str(OBJECT(&s->cpus), "cpu-type", machine->cpu_typ= e, &error_abort); - object_property_set_int(OBJECT(&s->soc), "hartid-base", 0, + object_property_set_int(OBJECT(&s->cpus), "hartid-base", 0, &error_abort); - object_property_set_int(OBJECT(&s->soc), "num-harts", hart_count, + object_property_set_int(OBJECT(&s->cpus), "num-harts", hart_count, &error_abort); - object_property_set_int(OBJECT(&s->soc), "resetvec", + object_property_set_int(OBJECT(&s->cpus), "resetvec", s->memmap[TT_ATL_BOOTROM].base, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); =20 s->irqchip =3D riscv_create_aia(system_memory, true, TT_IMSIC_GUESTS, --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142639699430.67703540300056; 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Fix this for the device tree pointer by passing it directly to the functions that use it, instead of casting the TTAtlantisState to a MachineState. MachineState::smp.cpus is replaced with TTAtlantisState::cpus.num_harts, as these are equivalent after tt_atlantis_machine_init. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/tt_atlantis.c | 51 +++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 35b3be072a06..c471c7cebf12 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -80,9 +80,8 @@ static uint32_t next_phandle(void) return fdt_phandle++; } =20 -static void create_fdt_memory(TTAtlantisState *s) +static void create_fdt_memory(void *fdt, TTAtlantisState *s) { - void *fdt =3D MACHINE(s)->fdt; hwaddr size_lo =3D MACHINE(s)->ram_size; hwaddr size_hi =3D 0; =20 @@ -104,9 +103,9 @@ static void create_fdt_memory(TTAtlantisState *s) } } =20 -static void create_fdt_aclint(TTAtlantisState *s, uint32_t *intc_phandles) +static void create_fdt_aclint(void *fdt, TTAtlantisState *s, + uint32_t *intc_phandles) { - void *fdt =3D MACHINE(s)->fdt; g_autofree char *name =3D NULL; g_autofree uint32_t *aclint_mtimer_cells =3D NULL; uint32_t aclint_cells_size; @@ -206,10 +205,9 @@ static void create_fdt_one_aplic(void *fdt, qemu_fdt_setprop_cell(fdt, name, "phandle", aplic_phandle); } =20 -static void create_fdt_pmu(TTAtlantisState *s) +static void create_fdt_pmu(void *fdt, TTAtlantisState *s) { char pmu_name[] =3D "/pmu"; - void *fdt =3D MACHINE(s)->fdt; RISCVCPU *hart =3D &s->cpus.harts[0]; =20 qemu_fdt_add_subnode(fdt, pmu_name); @@ -217,32 +215,29 @@ static void create_fdt_pmu(TTAtlantisState *s) riscv_pmu_generate_fdt_node(fdt, hart->pmu_avail_ctrs, pmu_name); } =20 -static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap, +static void create_fdt_cpu(void *fdt, TTAtlantisState *s, uint32_t aplic_s_phandle, uint32_t imsic_s_phandle) { - MachineState *ms =3D MACHINE(s); - void *fdt =3D MACHINE(s)->fdt; - g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); + g_autofree uint32_t *intc_phandles =3D g_new0(uint32_t, s->cpus.num_ha= rts); + int num_harts =3D s->cpus.num_harts; =20 fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); =20 - create_fdt_socket_cpus(fdt, s->cpus.harts, 0, s->cpus.num_harts, + create_fdt_socket_cpus(fdt, s->cpus.harts, 0, num_harts, s->cpus.hartid_base, &fdt_phandle, intc_phandle= s, false, false); =20 - create_fdt_memory(s); - - create_fdt_aclint(s, intc_phandles); + create_fdt_aclint(fdt, s, intc_phandles); =20 /* M-level IMSIC node */ uint32_t msi_m_phandle =3D next_phandle(); - create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], ms->smp.cpus, + create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_MIMSIC], num_harts, intc_phandles, msi_m_phandle, IRQ_M_EXT, TT_IMSIC_GUEST_BITS); =20 /* S-level IMSIC node */ - create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], ms->smp.cpus, + create_fdt_one_imsic(fdt, &s->memmap[TT_ATL_SIMSIC], num_harts, intc_phandles, imsic_s_phandle, IRQ_S_EXT, TT_IMSIC_GUEST_BITS); =20 @@ -252,13 +247,13 @@ static void create_fdt_cpu(TTAtlantisState *s, const = MemMapEntry *memmap, create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_MAPLIC], msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, - IRQ_M_EXT, s->cpus.num_harts); + IRQ_M_EXT, num_harts); =20 /* S-level APLIC node */ create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_SAPLIC], imsic_s_phandle, intc_phandles, aplic_s_phandle, 0, - IRQ_S_EXT, s->cpus.num_harts); + IRQ_S_EXT, num_harts); } =20 static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, @@ -317,10 +312,9 @@ static void create_fdt_i2c(void *fdt, const MemMapEntr= y *mem, uint32_t irq, qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); } =20 -static void create_fdt_i2c_device(TTAtlantisState *s, int bus, +static void create_fdt_i2c_device(void *fdt, TTAtlantisState *s, int bus, const char *compat, int addr) { - void *fdt =3D MACHINE(s)->fdt; hwaddr base =3D s->memmap[TT_ATL_I2C0 + bus].base; g_autofree char *name =3D g_strdup_printf("/soc/i2c@%"HWADDR_PRIX"/sen= sor@%x", base, addr); @@ -330,14 +324,15 @@ static void create_fdt_i2c_device(TTAtlantisState *s,= int bus, qemu_fdt_setprop_cell(fdt, name, "reg", addr); } =20 -static void finalize_fdt(TTAtlantisState *s) +static void finalize_fdt(void *fdt, TTAtlantisState *s) { uint32_t aplic_s_phandle =3D next_phandle(); uint32_t imsic_s_phandle =3D next_phandle(); uint32_t periph_clk_phandle =3D next_phandle(); - void *fdt =3D MACHINE(s)->fdt; =20 - create_fdt_cpu(s, s->memmap, aplic_s_phandle, imsic_s_phandle); + create_fdt_cpu(fdt, s, aplic_s_phandle, imsic_s_phandle); + + create_fdt_memory(fdt, s); =20 /* * We want to do this, but the Linux aplic driver was broken before v6= .16 @@ -359,8 +354,8 @@ static void finalize_fdt(TTAtlantisState *s) } =20 /* I2C peripherals: qemu specific */ - create_fdt_i2c_device(s, 0, "dallas,ds1338", 0x6f); - create_fdt_i2c_device(s, 4, "ti,tmp105", 0x48); + create_fdt_i2c_device(fdt, s, 0, "dallas,ds1338", 0x6f); + create_fdt_i2c_device(fdt, s, 4, "ti,tmp105", 0x48); } =20 static void create_fdt(TTAtlantisState *s) @@ -377,7 +372,7 @@ static void create_fdt(TTAtlantisState *s) =20 qemu_fdt_add_subnode(ms->fdt, "/aliases"); =20 - create_fdt_pmu(s); + create_fdt_pmu(ms->fdt, s); } =20 static void load_fdt(TTAtlantisState *s) @@ -408,7 +403,7 @@ static void load_fdt(TTAtlantisState *s) g_strfreev(node_path); } =20 - create_fdt_memory(s); + create_fdt_memory(ms->fdt, s); } =20 static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, @@ -439,7 +434,7 @@ static void tt_atlantis_machine_done(Notifier *notifier= , void *data) * dynamic sysbus devices. Our FDT needs to be finalized. */ if (machine->dtb =3D=3D NULL) { - finalize_fdt(s); + finalize_fdt(machine->fdt, s); } =20 mem_size =3D machine->ram_size; --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142673789847.8658686201367; Sun, 30 Aug 2026 19:17:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rZY-0003gx-NB; Sun, 30 Aug 2026 22:16:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rZX-0003gh-VD for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:31 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rZW-0007cZ-9L for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:31 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-38ea87caafeso2676644a91.3 for ; Sun, 30 Aug 2026 19:16:29 -0700 (PDT) Received: from donnager-debian.. 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Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 1 + hw/riscv/tt_atlantis.c | 19 ++++++++++--------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 642490d21743..a29c67c1cfcf 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -29,6 +29,7 @@ struct TTAtlantisState { Notifier machine_done; const MemMapEntry *memmap; =20 + MemoryRegion *memory; RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index c471c7cebf12..1c75fb5d8d57 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -482,13 +482,14 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) { TTAtlantisState *s =3D TT_ATLANTIS_MACHINE(machine); =20 - MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); MemoryRegion *ram_lo =3D g_new(MemoryRegion, 1); MemoryRegion *bootrom =3D g_new(MemoryRegion, 1); ram_addr_t lo_ram_size; int hart_count =3D machine->smp.cpus; =20 + s->memory =3D get_system_memory(); + s->memmap =3D tt_atlantis_memmap; =20 object_initialize_child(OBJECT(machine), "soc", &s->cpus, @@ -504,7 +505,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); =20 - s->irqchip =3D riscv_create_aia(system_memory, + s->irqchip =3D riscv_create_aia(s->memory, true, TT_IMSIC_GUESTS, TT_IMSIC_STRIDE, TT_IMSIC_STRIDE, @@ -517,7 +518,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) TT_IRQCHIP_NUM_MSIS, TT_IRQCHIP_NUM_PRIO_BITS); =20 - riscv_aclint_mtimer_create(system_memory, + riscv_aclint_mtimer_create(s->memory, s->memmap[TT_ATL_ACLINT].base, TT_ACLINT_MTIME_SIZE, 0, hart_count, @@ -540,23 +541,23 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) =20 memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", machine-= >ram, 0, machine->ram_size); - memory_region_add_subregion(system_memory, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_HI].base, ram_hi); =20 lo_ram_size =3D MIN(machine->ram_size, s->memmap[TT_ATL_DDR_LO].size); memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", machine->= ram, 0, lo_ram_size); - memory_region_add_subregion(system_memory, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_LO].base, ram_lo); =20 /* Boot ROM */ memory_region_init_rom(bootrom, NULL, "tt-atlantis.bootrom", s->memmap[TT_ATL_BOOTROM].size, &error_fatal); - memory_region_add_subregion(system_memory, s->memmap[TT_ATL_BOOTROM].b= ase, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, bootrom); =20 /* UART1, the soc console (UART0 is for the boot microcontroller) */ - serial_mm_init(system_memory, s->memmap[TT_ATL_UART1].base, 2, + serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, qdev_get_gpio_in(s->irqchip, TT_ATL_UART1_IRQ), 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); /* @@ -570,7 +571,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) */ object_initialize_child(OBJECT(s), "uart1", &s->uart1, TYPE_UNIMPLEMENTED_DEVICE); - mmio_map_unimplemented(system_memory, SYS_BUS_DEVICE(&s->uart1), + mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->uart1), "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, s->memmap[TT_ATL_UART1].size); =20 @@ -582,7 +583,7 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) TYPE_DESIGNWARE_I2C); sbd =3D SYS_BUS_DEVICE(&s->i2c[i]); sysbus_realize(sbd, &error_fatal); - memory_region_add_subregion(system_memory, + memory_region_add_subregion(s->memory, s->memmap[TT_ATL_I2C0 + i].base, sysbus_mmio_get_region(sbd, 0)); sysbus_connect_irq(sbd, 0, --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142628595568.2215272211951; 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This allows reading the RAM size without needing a pointer to MachineState, decoupling the memory layout setup from the machine. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/tt_atlantis.h | 1 + hw/riscv/tt_atlantis.c | 20 ++++++++++++-------- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index a29c67c1cfcf..2ec283d0fd7b 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -30,6 +30,7 @@ struct TTAtlantisState { const MemMapEntry *memmap; =20 MemoryRegion *memory; + MemoryRegion *dram; RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 1c75fb5d8d57..7a9f5872c7c0 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -82,12 +82,13 @@ static uint32_t next_phandle(void) =20 static void create_fdt_memory(void *fdt, TTAtlantisState *s) { - hwaddr size_lo =3D MACHINE(s)->ram_size; + hwaddr ram_size =3D memory_region_size(s->dram); + hwaddr size_lo =3D ram_size; hwaddr size_hi =3D 0; =20 if (size_lo > s->memmap[TT_ATL_DDR_LO].size) { size_lo =3D s->memmap[TT_ATL_DDR_LO].size; - size_hi =3D MACHINE(s)->ram_size - size_lo; + size_hi =3D ram_size - size_lo; } =20 create_fdt_socket_memory(fdt, s->memmap[TT_ATL_DDR_LO].base, size_lo, @@ -485,11 +486,14 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); MemoryRegion *ram_lo =3D g_new(MemoryRegion, 1); MemoryRegion *bootrom =3D g_new(MemoryRegion, 1); - ram_addr_t lo_ram_size; + ram_addr_t lo_ram_size, ram_size; int hart_count =3D machine->smp.cpus; =20 s->memory =3D get_system_memory(); =20 + s->dram =3D machine->ram; + ram_size =3D memory_region_size(s->dram); + s->memmap =3D tt_atlantis_memmap; =20 object_initialize_child(OBJECT(machine), "soc", &s->cpus, @@ -532,20 +536,20 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) * The high address is where RAM lives. It is always present and may be * up to 64GB. The low address is an alias of the first 2GB of that RA= M. */ - if (machine->ram_size > s->memmap[TT_ATL_DDR_HI].size) { + if (ram_size > s->memmap[TT_ATL_DDR_HI].size) { char *sz =3D size_to_str(s->memmap[TT_ATL_DDR_HI].size); error_report("RAM size is too large, maximum is %s", sz); g_free(sz); exit(EXIT_FAILURE); } =20 - memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", machine-= >ram, - 0, machine->ram_size); + memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", s->dram, + 0, ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_HI].base, ram_hi); =20 - lo_ram_size =3D MIN(machine->ram_size, s->memmap[TT_ATL_DDR_LO].size); - memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", machine->= ram, + lo_ram_size =3D MIN(ram_size, s->memmap[TT_ATL_DDR_LO].size); + memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", s->dram, 0, lo_ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_LO].base, ram_lo); --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142687691758.5892275380561; Sun, 30 Aug 2026 19:18:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rZl-0004cw-0n; Sun, 30 Aug 2026 22:16:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rZi-0004NX-IC for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:42 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rZg-0007eZ-LI for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:42 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2ceab75934dso33503085ad.2 for ; Sun, 30 Aug 2026 19:16:40 -0700 (PDT) Received: from donnager-debian.. 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Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/riscv/tt_atlantis.h | 4 ++++ hw/riscv/tt_atlantis.c | 15 ++++++--------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 2ec283d0fd7b..9ca98bfb8478 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -31,10 +31,14 @@ struct TTAtlantisState { =20 MemoryRegion *memory; MemoryRegion *dram; + MemoryRegion ram_hi; + MemoryRegion ram_lo; + RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; + MemoryRegion bootrom; }; =20 enum { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 7a9f5872c7c0..b80bdf54c40b 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -483,9 +483,6 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) { TTAtlantisState *s =3D TT_ATLANTIS_MACHINE(machine); =20 - MemoryRegion *ram_hi =3D g_new(MemoryRegion, 1); - MemoryRegion *ram_lo =3D g_new(MemoryRegion, 1); - MemoryRegion *bootrom =3D g_new(MemoryRegion, 1); ram_addr_t lo_ram_size, ram_size; int hart_count =3D machine->smp.cpus; =20 @@ -543,22 +540,22 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) exit(EXIT_FAILURE); } =20 - memory_region_init_alias(ram_hi, OBJECT(machine), "ram.high", s->dram, + memory_region_init_alias(&s->ram_hi, OBJECT(machine), "ram.high", s->d= ram, 0, ram_size); memory_region_add_subregion(s->memory, - s->memmap[TT_ATL_DDR_HI].base, ram_hi); + s->memmap[TT_ATL_DDR_HI].base, &s->ram_hi); =20 lo_ram_size =3D MIN(ram_size, s->memmap[TT_ATL_DDR_LO].size); - memory_region_init_alias(ram_lo, OBJECT(machine), "ram.low", s->dram, + memory_region_init_alias(&s->ram_lo, OBJECT(machine), "ram.low", s->dr= am, 0, lo_ram_size); memory_region_add_subregion(s->memory, - s->memmap[TT_ATL_DDR_LO].base, ram_lo); + s->memmap[TT_ATL_DDR_LO].base, &s->ram_lo); =20 /* Boot ROM */ - memory_region_init_rom(bootrom, NULL, "tt-atlantis.bootrom", + memory_region_init_rom(&s->bootrom, NULL, "tt-atlantis.bootrom", s->memmap[TT_ATL_BOOTROM].size, &error_fatal); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, - bootrom); + &s->bootrom); =20 /* UART1, the soc console (UART0 is for the boot microcontroller) */ serial_mm_init(s->memory, s->memmap[TT_ATL_UART1].base, 2, --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142673294917.4249704949942; Sun, 30 Aug 2026 19:17:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rZp-0004mu-Hd; Sun, 30 Aug 2026 22:16:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rZn-0004lz-AB for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:47 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rZl-0007fH-Pt for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:47 -0400 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-38dc4553f62so4201181a91.0 for ; Sun, 30 Aug 2026 19:16:45 -0700 (PDT) Received: from donnager-debian.. ([180.150.112.50]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-396b186807bsm20071240a91.12.2026.08.30.19.16.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2026 19:16:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788142604; x=1788747404; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date :message-id:reply-to:content-type; bh=yj3X6s5HDsl64/BQ6b/GU1IeAoNk6/eV2nZC5+pnfqY=; b=LBqLsmtDgmaS9I+kD7reIK91ezWFX1TtLgQ1UK2APgNRDhUry7PTbX07/nUJb9KOdh FUb9/uJfXjWsNiCK9jOu9CNwT+miMcNmX0F+x6F3yQfdXeZXUxK4FXYhi07LeCsO8wwy BVUByJEskjXwmdmxwQAAU6Lbl4m6j6pLggp85yv6aQP4yfZD6nD+r7nM5XLZkWJqElY9 +AOtOx64qE03s0Ca8c1QYfgQD9pfMSDm4ym/WIC346pDCI9N7Jt1ZtKpYxNH/QSmhwpf C+CrkSHoYNvHUKmL5xuqbU0vHwZBzy74dMAluea0dbDjeCf17fW5DKnYoP0aQq8u4USF srkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788142604; x=1788747404; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=yj3X6s5HDsl64/BQ6b/GU1IeAoNk6/eV2nZC5+pnfqY=; b=OVKiDBaAeuLwFeUBGeo4pL28gvmIEnG8ZOeaDef1aqcAISQs9ZnoUriLkyuFgeIHDS rE2qxx9Do0p3w+kh66WRCb28NkNvwjoJB3mStNeoNCBl0mXqMruR76uA4E1d5u4zhbSv 04oxCjZy5F4y3esdWY+FQGb6yd7aeqAgck95Uf2FyUGifKSvMMM7ESeP3tnM3qbiVNU7 +EfKq2XrKxAWU66W6kSA2Jem3v3x6O4KA0o6EQTx5vdAvu9zVU1RAzwUQOWx+f5Tjreq jFLWCFatb8Shyxzz+j50bHOwoLmXyKhL8vJNFLXkTJABnZqs4GQhfroJlNVYxWWbNS2k 2Ajw== X-Forwarded-Encrypted: i=1; AKwUvBw4DqjaInqtbzekmYrxLLFqI4QX1MBhwGenSdgsrLNJhsVMU1QlKTMy1EfXmSvuYySzStoEM6B5a377@nongnu.org X-Gm-Message-State: AFuF++kYrBGAPwat14migXznsY/rah+zCEkIwe7G7thSKZGM2pe36z68 ijKT6YUctaIInQvWloduNxxs13V3xB3CWAqg9UGM7ItK8Dbm3MRqvZYXuU4kNLNX X-Gm-Gg: AYBFou1rIDDx9847vqPNEntJtEdCKIoyVjvjJdRugB1UqrStqsO50I2wZ0ozrC3tMv8 aVseV2b/XLsSOIcOI8LVHM3fkWpW8G/JfMr67lmtttY/q7EcMexg2w7+B/hIrdFzUZtoM4Agrjn AN5jQj7b250RoQac65kWkvfG+VUqLqG57ykKpFwHJdmlj3qjupx+Y9vFcDQGZQg5Y0lS0+8qocC 5c3LnlTAXQ2vkseEI2DT0LR4g7+DkovpJ3lthVfw2oFoEn4y5BB23O0DmPvuz0gaBoQarV+IzLn JkJqru/OM1Q+lV30mK5+0EKByeogTCPFwDVvG5Hl65UFnLpM3j8qX/611z6pjly3FpFiPjVjuQO G3cLNAoxVLPJt53vipS9Br7OWsNrH9NkkB/7ZwCTtccek7dX2nKnuuXg/RwDDvZk9njhS7qju0x XNiWcBTxJfELgajT0iH7z5aTMXpHQD6JrZIGx8E/h+pooU95Cv14laFU/fwGQuHbpwIGnQV6Y7p N5E7kJmibITd0kzWiSDksMNGhHTYqTdt61wttthssNo9PLkMdLrASt9CnJTbZppi2eMz2BS9YUr E5yP2jgqy50I66R7XNV7 X-Received: by 2002:a17:90b:3c8d:b0:398:e969:87ef with SMTP id 98e67ed59e1d1-398e9698ae3mr4131221a91.24.1788142604336; Sun, 30 Aug 2026 19:16:44 -0700 (PDT) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza Cc: Portia Stephens , Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/16] hw/riscv: Add property to hart to allow private memory Date: Mon, 31 Aug 2026 11:44:55 +0930 Message-ID: <20260831021500.82565-15-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260831021500.82565-1-joel@jms.id.au> References: <20260831021500.82565-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=joel.stan@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1788142675712154100 Content-Type: text/plain; charset="utf-8" From: Portia Stephens There are platforms where CPUs have different mapping of system memory. The global system memory does not allow for this. This adds an optional property to assign a specific memory region to a hart. This allows for a machine to alias the hart's memory to system memory while the hart only views memory from its own memory region. Signed-off-by: Portia Stephens Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis --- include/hw/riscv/riscv_hart.h | 2 ++ hw/riscv/riscv_hart.c | 8 ++++++++ 2 files changed, 10 insertions(+) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 197fa1623115..c3cd05a2c877 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -42,6 +42,8 @@ struct RISCVHartArrayState { uint64_t *rnmi_irqvec; uint32_t num_rnmi_excpvec; uint64_t *rnmi_excpvec; + /* Optional private memory region for use instead of system memory */ + MemoryRegion *memory; RISCVCPU *harts; }; =20 diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 747754be6158..32fd39737ff6 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -53,6 +53,8 @@ static const Property riscv_harts_props[] =3D { DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, uint64_t), + DEFINE_PROP_LINK("memory", RISCVHartArrayState, memory, + TYPE_MEMORY_REGION, MemoryRegion *), }; =20 static void riscv_harts_cpu_reset(void *opaque) @@ -117,6 +119,12 @@ static bool riscv_hart_realize(RISCVHartArrayState *s,= int idx, object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_typ= e); qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); =20 + /* Use private memory instead of system_memory if provided */ + if (s->memory) { + object_property_set_link(OBJECT(&s->harts[idx]), "memory", + OBJECT(s->memory), &error_abort); + } + if (s->harts[idx].cfg.ext_smrnmi) { if (idx < s->num_rnmi_irqvec) { qdev_prop_set_uint64(DEVICE(&s->harts[idx]), --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1788142660443561.0653140311944; Sun, 30 Aug 2026 19:17:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1x0rZv-00055e-PU; Sun, 30 Aug 2026 22:16:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1x0rZt-0004sx-OB for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:53 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1x0rZr-0007hI-8w for qemu-devel@nongnu.org; Sun, 30 Aug 2026 22:16:53 -0400 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-38dfe7eb825so2400197a91.0 for ; Sun, 30 Aug 2026 19:16:50 -0700 (PDT) Received: from donnager-debian.. ([180.150.112.50]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-396b186807bsm20071240a91.12.2026.08.30.19.16.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2026 19:16:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788142610; x=1788747410; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date :message-id:reply-to:content-type; bh=cYrYRFsDEYadIwXO/tqyMC/amdwUYkmKIWK3I1LucWI=; b=QVZ7leiELLA1x/pVZ0DWls1RGk49OQR73EtgiCQNqVkllM/ShMJGzquzzsZreTEHPL y8ffh7FjaVb6yN2v86Od+AYsrOl4STRletv7F6HBM+lAWyr726WY7r1TeNy8RLl5Ov9E p4eZsDhMxaT4B4tlDH7Fctyl2tNDwqux0obHlEYc9yOP/J6XKcCz+wOkA6wTOgA7YgF+ 9JbFlL5HiLxZjaU6kVcR197VS+Tw3B5N4Qe8k2tSqm9NmoLYPINDbXNXazUDFdEDGa6e jMSqpEX4udvpZIGA5nfpS+VrWrwre4MHYJWRuR+KOJqak0qiHu1rB1q1TEuaKXk63MpD QLvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788142610; x=1788747410; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=cYrYRFsDEYadIwXO/tqyMC/amdwUYkmKIWK3I1LucWI=; b=NWodWidgpU7C+MCiFClq2deP665ONimRTkHpv5+7MGSaprLCVYbjvWE1ZGzpfO+cv/ rMLRlSFml8gqa4FIdstC+aEaaqy1PQiOSKT9OeSLas5ud8D+aXeKb0fL9IVHLWlhVrUk etvCKGDwaCVbMcEHo/CdmS5ugfLAG3AdOODOBYGT/fWcEtCdUZmM4qBBVOh7d+HpvD0l SaLhE7Jxr1Omtji4ARky/iFy0/lfvnXLir43ajNg9UEYngLkMZ8rEEd7gSQBvlBI58a4 wyGjyFbgv53zs++ErsToN04sPr9Gu0/E+ZPXgu7Y/cPumhCxeImf6TtoYQ8n9qDpCDW/ oh6w== X-Forwarded-Encrypted: i=1; AKwUvByAc6wPjtTH+VnQUcsKV9YvHkT1aYh/mqRw4TEOwIyAp7X1PzJvKOiH7BDjA5wHne910Ocn0/p6vPh7@nongnu.org X-Gm-Message-State: AFuF++mwJ41L8DiYIt+PGiZetSi1pQ388rPZA/h3CuRZhgDepVfQwEYj nD6u4TVkbVlpjOybz9epOV0o56EgTxgqg+2tp5ZDlPrFYAyiyvFCp0eW X-Gm-Gg: AYBFou3GUkNAdDtoLgtm2zjaME1sXVd0EUUFgykzmvUzBmVvKWELDmfpS9BD6Ko/mXm QfnpYt4CHdYNcEdmLCtGygVsB5YZygzUACP/6/bz1MFYKkR6eo0qyOtPZVR9fzyrd2Q7OYq2QIA 7GeMlfaGxuqpZQ/dKghXEpBhksSarCCqxNmPHbXFkwugxhulrTaypOcqMDt66RopykraLR+oOCi QeUhBJrXF6CvJK+L2AEGMwBHAIXmP04n6KkdWycEIrfpTpSlXQCAPxqdcx4vH0XUXUWTZ+5AEuE zESGgcuUDUL1gYfLPEBNEXZDfdToMRWSwvza00AUQCMSLemiQl6mn9M0uG2oHm5mIbrTt7YJJAv a9nk4VBbUo4UVMbvaIy6Eo/2D/wYN4nFvoBIxGxj1eR/vMgV7xPr/7d9Re/ExsbOiStEF0MpVLw YbTvPs3+2Me4gXo3AaBJ2QBiifamV7hiG+N2j6Icvw2YfXATF5+UE6go/8xawubXzkSiZ8w9MPP +Q4fqDdUY1mmj/kRCbYXYEljJm2w2apcKQyi+lCfmdKTjaBJEQF70ZSgTID5V3dXuIqvIEg6ehb qJxOQkUDxAmrQ0p2TEXtHbByAcnJ/po= X-Received: by 2002:a17:90b:5287:b0:398:9c07:8907 with SMTP id 98e67ed59e1d1-3989c0797c7mr23197729a91.24.1788142609842; Sun, 30 Aug 2026 19:16:49 -0700 (PDT) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza Cc: Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , Portia Stephens , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/16] hw/riscv/atlantis: Extract an Atlantis SoC device Date: Mon, 31 Aug 2026 11:44:56 +0930 Message-ID: <20260831021500.82565-16-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260831021500.82565-1-joel@jms.id.au> References: <20260831021500.82565-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=joel.stan@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1788142662323158500 Content-Type: text/plain; charset="utf-8" Introduce TYPE_TT_ATLANTIS_SOC and move the hart array, AIA, ACLINT, boot ROM, UART and I2C controllers into the new TTAtlantisSoCState. The machine keeps ownership of RAM, device tree generation, firmware loading, and the board-level I2C slaves. This makes it easier to compose the SoC into a more complex machine in the future. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 21 ++++- hw/riscv/tt_atlantis.c | 144 +++++++++++++++++++++++---------- 2 files changed, 119 insertions(+), 46 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 9ca98bfb8478..5d4e4d133bd9 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -19,14 +19,16 @@ #define TYPE_TT_ATLANTIS_MACHINE MACHINE_TYPE_NAME("tt-atlantis") OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisState, TT_ATLANTIS_MACHINE) =20 +#define TYPE_TT_ATLANTIS_SOC "tt-atlantis-soc" +OBJECT_DECLARE_SIMPLE_TYPE(TTAtlantisSoCState, TT_ATLANTIS_SOC) + #define TT_ATL_NUM_I2C 5 =20 -struct TTAtlantisState { +struct TTAtlantisSoCState { /*< private >*/ - MachineState parent; + DeviceState parent; =20 /*< public >*/ - Notifier machine_done; const MemMapEntry *memmap; =20 MemoryRegion *memory; @@ -39,6 +41,19 @@ struct TTAtlantisState { DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; MemoryRegion bootrom; + + uint32_t num_harts; + char *cpu_type; +}; + +struct TTAtlantisState { + /*< private >*/ + MachineState parent; + + /*< public >*/ + Notifier machine_done; + + TTAtlantisSoCState soc; }; =20 enum { diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index b80bdf54c40b..d2b29ff1a477 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -7,6 +7,7 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" #include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" @@ -14,6 +15,7 @@ =20 #include "hw/core/boards.h" #include "hw/core/loader.h" +#include "hw/core/qdev-properties.h" #include "hw/core/sysbus.h" =20 #include "target/riscv/cpu.h" @@ -67,7 +69,7 @@ static const MemMapEntry tt_atlantis_memmap[] =3D { [TT_ATL_DDR_HI] =3D { 0x100000000, 0x1000000000 }, }; =20 -static I2CBus *i2c_get_bus(TTAtlantisState *s, unsigned busnr) +static I2CBus *i2c_get_bus(TTAtlantisSoCState *s, unsigned busnr) { assert(busnr < TT_ATL_NUM_I2C); =20 @@ -80,7 +82,7 @@ static uint32_t next_phandle(void) return fdt_phandle++; } =20 -static void create_fdt_memory(void *fdt, TTAtlantisState *s) +static void create_fdt_memory(void *fdt, TTAtlantisSoCState *s) { hwaddr ram_size =3D memory_region_size(s->dram); hwaddr size_lo =3D ram_size; @@ -104,7 +106,7 @@ static void create_fdt_memory(void *fdt, TTAtlantisStat= e *s) } } =20 -static void create_fdt_aclint(void *fdt, TTAtlantisState *s, +static void create_fdt_aclint(void *fdt, TTAtlantisSoCState *s, uint32_t *intc_phandles) { g_autofree char *name =3D NULL; @@ -206,7 +208,7 @@ static void create_fdt_one_aplic(void *fdt, qemu_fdt_setprop_cell(fdt, name, "phandle", aplic_phandle); } =20 -static void create_fdt_pmu(void *fdt, TTAtlantisState *s) +static void create_fdt_pmu(void *fdt, TTAtlantisSoCState *s) { char pmu_name[] =3D "/pmu"; RISCVCPU *hart =3D &s->cpus.harts[0]; @@ -216,7 +218,7 @@ static void create_fdt_pmu(void *fdt, TTAtlantisState *= s) riscv_pmu_generate_fdt_node(fdt, hart->pmu_avail_ctrs, pmu_name); } =20 -static void create_fdt_cpu(void *fdt, TTAtlantisState *s, +static void create_fdt_cpu(void *fdt, TTAtlantisSoCState *s, uint32_t aplic_s_phandle, uint32_t imsic_s_phandle) { @@ -313,7 +315,7 @@ static void create_fdt_i2c(void *fdt, const MemMapEntry= *mem, uint32_t irq, qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0); } =20 -static void create_fdt_i2c_device(void *fdt, TTAtlantisState *s, int bus, +static void create_fdt_i2c_device(void *fdt, TTAtlantisSoCState *s, int bu= s, const char *compat, int addr) { hwaddr base =3D s->memmap[TT_ATL_I2C0 + bus].base; @@ -325,7 +327,7 @@ static void create_fdt_i2c_device(void *fdt, TTAtlantis= State *s, int bus, qemu_fdt_setprop_cell(fdt, name, "reg", addr); } =20 -static void finalize_fdt(void *fdt, TTAtlantisState *s) +static void finalize_fdt(void *fdt, TTAtlantisSoCState *s) { uint32_t aplic_s_phandle =3D next_phandle(); uint32_t imsic_s_phandle =3D next_phandle(); @@ -359,9 +361,9 @@ static void finalize_fdt(void *fdt, TTAtlantisState *s) create_fdt_i2c_device(fdt, s, 4, "ti,tmp105", 0x48); } =20 -static void create_fdt(TTAtlantisState *s) +static void create_fdt(TTAtlantisState *ams) { - MachineState *ms =3D MACHINE(s); + MachineState *ms =3D MACHINE(ams); int fdt_size =3D 0; =20 ms->fdt =3D create_board_device_tree("Tenstorrent Atlantis RISC-V Mach= ine", @@ -373,12 +375,12 @@ static void create_fdt(TTAtlantisState *s) =20 qemu_fdt_add_subnode(ms->fdt, "/aliases"); =20 - create_fdt_pmu(ms->fdt, s); + create_fdt_pmu(ms->fdt, &ams->soc); } =20 -static void load_fdt(TTAtlantisState *s) +static void load_fdt(TTAtlantisState *ams) { - MachineState *ms =3D MACHINE(s); + MachineState *ms =3D MACHINE(ams); char **node_path; Error *err =3D NULL; int fdt_size =3D 0; @@ -404,7 +406,7 @@ static void load_fdt(TTAtlantisState *s) g_strfreev(node_path); } =20 - create_fdt_memory(ms->fdt, s); + create_fdt_memory(ms->fdt, &ams->soc); } =20 static void mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev, @@ -418,10 +420,11 @@ static void mmio_map_unimplemented(MemoryRegion *memo= ry, SysBusDevice *dev, sysbus_mmio_get_region(dev, 0), -1= 000); } =20 -static void tt_atlantis_machine_done(Notifier *notifier, void *data) +static void tt_atlantis_machine_done(Notifier *n, void *data) { - TTAtlantisState *s =3D container_of(notifier, TTAtlantisState, machine= _done); - MachineState *machine =3D MACHINE(s); + TTAtlantisState *ams =3D container_of(n, TTAtlantisState, machine_done= ); + TTAtlantisSoCState *s =3D &ams->soc; + MachineState *machine =3D MACHINE(ams); hwaddr start_addr =3D s->memmap[TT_ATL_DDR_LO].base; hwaddr mem_size; target_ulong firmware_end_addr, kernel_start_addr; @@ -479,23 +482,39 @@ static void tt_atlantis_machine_done(Notifier *notifi= er, void *data) fdt_load_addr); } =20 -static void tt_atlantis_machine_init(MachineState *machine) +static void tt_atlantis_soc_init(Object *obj) { - TTAtlantisState *s =3D TT_ATLANTIS_MACHINE(machine); + TTAtlantisSoCState *s =3D TT_ATLANTIS_SOC(obj); + + object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); + + object_initialize_child(obj, "uart1", &s->uart1, + TYPE_UNIMPLEMENTED_DEVICE); =20 + for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { + object_initialize_child(obj, "i2c[*]", &s->i2c[i], + TYPE_DESIGNWARE_I2C); + } +} + +static void tt_atlantis_soc_realize(DeviceState *dev, Error **errp) +{ + TTAtlantisSoCState *s =3D TT_ATLANTIS_SOC(dev); ram_addr_t lo_ram_size, ram_size; - int hart_count =3D machine->smp.cpus; + int hart_count =3D s->num_harts; =20 s->memory =3D get_system_memory(); =20 - s->dram =3D machine->ram; + if (!s->dram) { + error_setg(errp, "'dram' link is not set"); + return; + } ram_size =3D memory_region_size(s->dram); =20 s->memmap =3D tt_atlantis_memmap; =20 - object_initialize_child(OBJECT(machine), "soc", &s->cpus, - TYPE_RISCV_HART_ARRAY); - object_property_set_str(OBJECT(&s->cpus), "cpu-type", machine->cpu_typ= e, + /* CPUs */ + object_property_set_str(OBJECT(&s->cpus), "cpu-type", s->cpu_type, &error_abort); object_property_set_int(OBJECT(&s->cpus), "hartid-base", 0, &error_abort); @@ -504,7 +523,9 @@ static void tt_atlantis_machine_init(MachineState *mach= ine) object_property_set_int(OBJECT(&s->cpus), "resetvec", s->memmap[TT_ATL_BOOTROM].base, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpus), errp)) { + return; + } =20 s->irqchip =3D riscv_create_aia(s->memory, true, TT_IMSIC_GUESTS, @@ -534,26 +555,27 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) * up to 64GB. The low address is an alias of the first 2GB of that RA= M. */ if (ram_size > s->memmap[TT_ATL_DDR_HI].size) { - char *sz =3D size_to_str(s->memmap[TT_ATL_DDR_HI].size); - error_report("RAM size is too large, maximum is %s", sz); - g_free(sz); - exit(EXIT_FAILURE); + g_autofree char *sz =3D size_to_str(s->memmap[TT_ATL_DDR_HI].size); + error_setg(errp, "RAM size is too large, maximum is %s", sz); + return; } =20 - memory_region_init_alias(&s->ram_hi, OBJECT(machine), "ram.high", s->d= ram, + memory_region_init_alias(&s->ram_hi, OBJECT(s), "ram.high", s->dram, 0, ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_HI].base, &s->ram_hi); =20 lo_ram_size =3D MIN(ram_size, s->memmap[TT_ATL_DDR_LO].size); - memory_region_init_alias(&s->ram_lo, OBJECT(machine), "ram.low", s->dr= am, + memory_region_init_alias(&s->ram_lo, OBJECT(s), "ram.low", s->dram, 0, lo_ram_size); memory_region_add_subregion(s->memory, s->memmap[TT_ATL_DDR_LO].base, &s->ram_lo); =20 /* Boot ROM */ - memory_region_init_rom(&s->bootrom, NULL, "tt-atlantis.bootrom", - s->memmap[TT_ATL_BOOTROM].size, &error_fatal); + if (!memory_region_init_rom(&s->bootrom, OBJECT(s), "tt-atlantis.bootr= om", + s->memmap[TT_ATL_BOOTROM].size, errp)) { + return; + } memory_region_add_subregion(s->memory, s->memmap[TT_ATL_BOOTROM].base, &s->bootrom); =20 @@ -570,26 +592,56 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) * Create an unimplemented device region so writes don't fault * and reads return zero, which keeps Linux happy. */ - object_initialize_child(OBJECT(s), "uart1", &s->uart1, - TYPE_UNIMPLEMENTED_DEVICE); mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->uart1), "tt-atlantis.uart1", s->memmap[TT_ATL_UART1].ba= se, s->memmap[TT_ATL_UART1].size); =20 /* I2C */ for (int i =3D 0; i < TT_ATL_NUM_I2C; i++) { - SysBusDevice *sbd; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->i2c[i]); =20 - object_initialize_child(OBJECT(s), "i2c[*]", &s->i2c[i], - TYPE_DESIGNWARE_I2C); - sbd =3D SYS_BUS_DEVICE(&s->i2c[i]); - sysbus_realize(sbd, &error_fatal); + if (!sysbus_realize(sbd, errp)) { + return; + } memory_region_add_subregion(s->memory, s->memmap[TT_ATL_I2C0 + i].base, sysbus_mmio_get_region(sbd, 0)); sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(s->irqchip, TT_ATL_I2C0_IRQ + = i)); } +} + +static const Property tt_atlantis_soc_props[] =3D { + DEFINE_PROP_STRING("cpu-type", TTAtlantisSoCState, cpu_type), + DEFINE_PROP_UINT32("num-harts", TTAtlantisSoCState, num_harts, 8), + DEFINE_PROP_LINK("dram", TTAtlantisSoCState, dram, + TYPE_MEMORY_REGION, MemoryRegion *), +}; + +static void tt_atlantis_soc_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D tt_atlantis_soc_realize; + device_class_set_props(dc, tt_atlantis_soc_props); + /* The SoC can only be instantiated from the machine */ + dc->user_creatable =3D false; +} + +static void tt_atlantis_machine_init(MachineState *machine) +{ + TTAtlantisState *ams =3D TT_ATLANTIS_MACHINE(machine); + TTAtlantisSoCState *s =3D &ams->soc; + + object_initialize_child(OBJECT(machine), "soc", &ams->soc, + TYPE_TT_ATLANTIS_SOC); + object_property_set_str(OBJECT(&ams->soc), "cpu-type", machine->cpu_ty= pe, + &error_abort); + object_property_set_int(OBJECT(&ams->soc), "num-harts", machine->smp.c= pus, + &error_abort); + object_property_set_link(OBJECT(&ams->soc), "dram", OBJECT(machine->ra= m), + &error_abort); + qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); =20 /* I2C peripherals: qemu specific */ i2c_slave_create_simple(i2c_get_bus(s, 0), "ds1338", 0x6f); @@ -597,13 +649,13 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) =20 /* Load or create device tree */ if (machine->dtb) { - load_fdt(s); + load_fdt(ams); } else { - create_fdt(s); + create_fdt(ams); } =20 - s->machine_done.notify =3D tt_atlantis_machine_done; - qemu_add_machine_init_done_notifier(&s->machine_done); + ams->machine_done.notify =3D tt_atlantis_machine_done; + qemu_add_machine_init_done_notifier(&ams->machine_done); } =20 static void tt_atlantis_machine_class_init(ObjectClass *oc, const void *da= ta) @@ -623,6 +675,12 @@ static void tt_atlantis_machine_class_init(ObjectClass= *oc, const void *data) =20 static const TypeInfo tt_atlantis_types[] =3D { { + .name =3D TYPE_TT_ATLANTIS_SOC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(TTAtlantisSoCState), + .instance_init =3D tt_atlantis_soc_init, + .class_init =3D tt_atlantis_soc_class_init, + }, { .name =3D MACHINE_TYPE_NAME("tt-atlantis"), .parent =3D TYPE_MACHINE, .class_init =3D tt_atlantis_machine_class_init, --=20 2.47.3 From nobody Sat Sep 26 21:37:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([180.150.112.50]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-396b186807bsm20071240a91.12.2026.08.30.19.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2026 19:16:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1788142615; x=1788747415; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date :message-id:reply-to:content-type; bh=n+dEv2CXGdQUWUzHVbk1BheHXV911tV5Sryp6N+Qyq0=; b=bSqLAIyamRpKsvyp00JEi9ezzlb3n3wMuUm/Y7qLygiL6/ngPfC4E7jAdumH2jobkG YAAPQFE0qpJ2HXwcBSG/Q1+6FDS4esTmGJ9LXklbgkx4oweOzPjXe1tc68XzB94s/Ks1 IJ1/wBTRKNaVGIVMx+tk6cfuhD2RA4bGfQb6K/D5LUXWQgHL3q1ZL4QVEtln8wwfZXyF ZNSbZNF1iOyiZgp3/SLpl9/IZydZ8K5sKONzFpyevWQuU/QmylK3jTuemiZZXe2gzjBV MiyusKfi8tmPbADO1QZQanMr6K5r6UG+w5lk9flWOqVY6idlyVQSF2NiupPcF16TSXtg agcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788142615; x=1788747415; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=n+dEv2CXGdQUWUzHVbk1BheHXV911tV5Sryp6N+Qyq0=; b=TXqN9dWOhCrq19XiYYWgxuQBme8sqjUqtWLE7kMZfIotlLec4Ym9PWVBfPllgaJ9xb XC4RhOBaxiPvaxWmRtRklo/MXYqP+Eec9r0KhECSx5y1UUobSqlXVYk/u6vLPsZYK9cf 7J+nj0GiN9rgHSXQDAgYs4gR231BovJULguAPYl+oA/sa+yPwoH/1eHpeQzSodXJe+/0 DoO8Syeds+pPjN8sbPMP66ex2FkvJgyc12QffUMbbjN2Ct35CIJqpGew92RfuwbFOVy3 LtoRRnwRwAkgkMnl0RzEvlcW+yHgFe04triH/oDTHX24Herl1xmpT+YVfZKt/0iwrwF2 /Gmg== X-Forwarded-Encrypted: i=1; AKwUvBzSbvFhjnsvtDV+MNvg+M9eyaHM7CgCFxkQV7VCUCBCu9hG2Vl3lEm7cLTzfcaekuFLBnF8afX7nhAL@nongnu.org X-Gm-Message-State: AFuF++mat3lXPeczu9tYGUFROupI8r4nFE3rlzJmqzx29tgvYXpf48Og JJGunO9pibsuXNIHH05vSBdGY8UotlyzBcWPckpq6pe/HEu8+5YokRZh X-Gm-Gg: AYBFou2Zfhnnd3yH8Is5cRnkrGkOfuXLi530cP9w1eWoAfjiRcUS+sNPRu1o2LA692c fSG2m9nWN5QSdGm+/HWnsRHcHbr/CWHUeno0HToQY4P0BZNm9xKI7G5X+ZraVs/9IqsnWuK0VhZ 6rgzTxj6zxiy3IYkgd4LbDUcqLBk9vkXipnDrw+zLfe7FGGpCCcwytrTeKa03EJNPLy1c7ElBSn QbqcftDfBiYvtnF81ZcqoIlJKXlzLELLTEpLjetXon/Ypj8cFKkqS+xE6Y0d7k+cWUfXBRJVcF2 q/ukVZXGhOHp4f5QpMCkDUgOWj7YvmZwDiPb3T20RFN/wocdGbNh/iHZf+sqop1UQSwRuNga3Av 4i6p37R5LwnZVm0I/UIYs/Cd9qgRuWcBN+5GeeYxjRgvE6R+1Th2QACC7hyyami59uFxv/HD7ZE c+FmvDjmHVXC7lK72aBZ6JLqAkhpssb01Ny9IolcepQDHBSjv5MlsPK+AEt5MaPdHxC4lDXfATf Dd2FS9BFy3su31cxyiv7dHQ6wBaI4UJNRXJwFriQIW4DqMQakYGjVoFMxDRGC5VTwDy+9Wcs7a1 QObRyDFp+8IDrb493Rp1 X-Received: by 2002:a17:90b:264d:b0:398:dcf6:d40e with SMTP id 98e67ed59e1d1-398f86d88a2mr380104a91.17.1788142615014; Sun, 30 Aug 2026 19:16:55 -0700 (PDT) From: Joel Stanley To: Alistair Francis , Daniel Henrique Barboza Cc: Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , Portia Stephens , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/16] hw/riscv/atlantis: Map the SoC through a memory container Date: Mon, 31 Aug 2026 11:44:57 +0930 Message-ID: <20260831021500.82565-17-joel@jms.id.au> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260831021500.82565-1-joel@jms.id.au> References: <20260831021500.82565-1-joel@jms.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=joel.stan@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1788142678280158500 Content-Type: text/plain; charset="utf-8" Give the Atlantis SoC a 'memory' link property. The machine creates a container MemoryRegion, maps it at address 0 of system memory, and passes it to the SoC together with the machine RAM. The SoC maps devices into the 'memory' container instead of system memory, allowing TTAtlantisSoCState to be composed together with other SoCs in the future. This prepares the machine for adding other microcontrollers that share the memory bus with the Ascalon complex (aka the Atlantis SoC), but with their own view of the address map. Signed-off-by: Joel Stanley Reviewed-by: Alistair Francis --- include/hw/riscv/tt_atlantis.h | 1 + hw/riscv/tt_atlantis.c | 17 +++++++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index 5d4e4d133bd9..3923308b7c89 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -53,6 +53,7 @@ struct TTAtlantisState { /*< public >*/ Notifier machine_done; =20 + MemoryRegion soc_memory; TTAtlantisSoCState soc; }; =20 diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index d2b29ff1a477..b78b4a5ea31e 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -503,8 +503,10 @@ static void tt_atlantis_soc_realize(DeviceState *dev, = Error **errp) ram_addr_t lo_ram_size, ram_size; int hart_count =3D s->num_harts; =20 - s->memory =3D get_system_memory(); - + if (!s->memory) { + error_setg(errp, "'memory' link is not set"); + return; + } if (!s->dram) { error_setg(errp, "'dram' link is not set"); return; @@ -523,6 +525,8 @@ static void tt_atlantis_soc_realize(DeviceState *dev, E= rror **errp) object_property_set_int(OBJECT(&s->cpus), "resetvec", s->memmap[TT_ATL_BOOTROM].base, &error_abort); + object_property_set_link(OBJECT(&s->cpus), "memory", OBJECT(s->memory), + &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpus), errp)) { return; } @@ -614,6 +618,8 @@ static void tt_atlantis_soc_realize(DeviceState *dev, E= rror **errp) static const Property tt_atlantis_soc_props[] =3D { DEFINE_PROP_STRING("cpu-type", TTAtlantisSoCState, cpu_type), DEFINE_PROP_UINT32("num-harts", TTAtlantisSoCState, num_harts, 8), + DEFINE_PROP_LINK("memory", TTAtlantisSoCState, memory, + TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_LINK("dram", TTAtlantisSoCState, dram, TYPE_MEMORY_REGION, MemoryRegion *), }; @@ -633,12 +639,19 @@ static void tt_atlantis_machine_init(MachineState *ma= chine) TTAtlantisState *ams =3D TT_ATLANTIS_MACHINE(machine); TTAtlantisSoCState *s =3D &ams->soc; =20 + memory_region_init(&ams->soc_memory, OBJECT(machine), + "tt-atlantis.soc-memory", UINT64_MAX); + memory_region_add_subregion(get_system_memory(), 0, &ams->soc_memory); + object_initialize_child(OBJECT(machine), "soc", &ams->soc, TYPE_TT_ATLANTIS_SOC); object_property_set_str(OBJECT(&ams->soc), "cpu-type", machine->cpu_ty= pe, &error_abort); object_property_set_int(OBJECT(&ams->soc), "num-harts", machine->smp.c= pus, &error_abort); + + object_property_set_link(OBJECT(&ams->soc), "memory", + OBJECT(&ams->soc_memory), &error_abort); object_property_set_link(OBJECT(&ams->soc), "dram", OBJECT(machine->ra= m), &error_abort); qdev_realize(DEVICE(&ams->soc), NULL, &error_fatal); --=20 2.47.3